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Thousands of conductance levels in memristors integrated on CMOS


Neural networks based on memristive devices1,2,3 have the ability to improve throughput and energy efficiency for machine learning4,5 and artificial intelligence6, especially in edge applications7,8,9,10,11,12,13,14,15,16,17,18,19,20,21. Because training a neural network model from scratch is costly in terms of hardware resources, time and energy, it is impractical to do it individually on billions of memristive neural networks distributed at the edge. A practical approach would be to download the synaptic weights obtained from the cloud training and program them directly into memristors for the commercialization of edge applications. Some post-tuning in memristor conductance could be done afterwards or during applications to adapt to specific situations. Therefore, in neural network applications, memristors require high-precision programmability to guarantee uniform and accurate performance across a large number of memristive networks22,23,24,25,26,27,28. This requires many distinguishable conductance levels on each memristive device, not only laboratory-made devices but also devices fabricated in factories. Analog memristors with many conductance states also benefit other applications, such as neural network training, scientific computing and even ‘mortal computing’25,29,30. Here we report 2,048 conductance levels achieved with memristors in fully integrated chips with 256 × 256 memristor arrays monolithically integrated on complementary metal–oxide–semiconductor (CMOS) circuits in a commercial foundry. We have identified the underlying physics that previously limited the number of conductance levels that could be achieved in memristors and developed electrical operation protocols to avoid such limitations. These results provide insights into the fundamental understanding of the microscopic picture of memristive switching as well as approaches to enable high-precision memristors for various applications.

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Fig. 1: High-precision memristor for neuromorphic computing.
Fig. 2: Direct observation of the evolution of conduction channels in the denoising process using C-AFM.
Fig. 3: Trapped-charge-induced conductance change in incomplete conduction channels.
Fig. 4: Mechanism of denoising using subthreshold voltage, identified using C-AFM measurements and phase-field theory simulations.

Data availability

The data that support the findings of this study are available from the corresponding author upon reasonable request.

Code availability

The algorithm for memristor high-precision programming is included in the Supplementary Information. The code for physical modelling and simulations is available at GitHub (


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J.J.Y., W.S. and Y.Z. were partially supported by a subcontract (GR1055585 53-4502-0003) from the University of Massachusetts Amherst, with the sponsor being TetraMem. R.M., Q.X. and J.J.Y. were partially supported by the Air Force Office of Scientific Research through the Multidisciplinary University Research Initiative programme under contract no. FA9550-19-1-0213, the US Air Force Research Laboratory (prime contract nos. FA8650-21-C-5405 and FA8750-22-1-0501) and by the National Science Foundation under contract no. 2023752. J.W. and H.W. acknowledge the support by the Army Research Office (grant no. W911NF2120128) and the National Science Foundation (grant no. CMMI-2240407). H.T. and J.L. acknowledge the support by the National Science Foundation (grant no. CMMI-1922206). We thank A. Tan for proofreading the manuscript.

Author information

Authors and Affiliations



J.J.Y. and M.R. conceived the concept. J.J.Y. and Q.X. supervised the entire project. J.J.Y., M.R., Q.X., H.T., J.W. and W.S. designed the experiments and simulations. M.R., M.Z., R.M. and H.J. fabricated the devices. M.R., W.S., Y.Z., B.C., X.J. and Z.W. carried out the electrical measurements. H.T., M.R. and J.L. designed and carried out the simulation. J.W., M.R., H.L., H.-Y.C. and H.W. designed and carried out the C-AFM studies. W.Y., F.K., F.Y., Z.W., M.W., M.H., Q.X., N.G. and J.J.Y. helped with experiments and data analysis. M.R., H.T. and J.J.Y. wrote the paper. All authors discussed the results and implications and commented on the manuscript at all stages.

Corresponding author

Correspondence to J. Joshua Yang.

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Competing interests

J.J.Y. and Q.X. are co-founders and paid consultants of TetraMem.

Peer review

Peer review information

Nature thanks Yiyu Shi, Ilia Valov and Yuchao Yang for their contribution to the peer review of this work. Peer reviewer reports are available.

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Supplementary information

Supplementary Information

This file contains Supplementary Figs. 1–15, a discussion on the probable RTN-responsible defect and an analysis of electronic and atomic noise effects.

Peer Review File

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Rao, M., Tang, H., Wu, J. et al. Thousands of conductance levels in memristors integrated on CMOS. Nature 615, 823–829 (2023).

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