Vertical organic electrochemical transistors for complementary circuits

Organic electrochemical transistors (OECTs) and OECT-based circuitry offer great potential in bioelectronics, wearable electronics and artificial neuromorphic electronics because of their exceptionally low driving voltages (<1 V), low power consumption (<1 µW), high transconductances (>10 mS) and biocompatibility1–5. However, the successful realization of critical complementary logic OECTs is currently limited by temporal and/or operational instability, slow redox processes and/or switching, incompatibility with high-density monolithic integration and inferior n-type OECT performance6–8. Here we demonstrate p- and n-type vertical OECTs with balanced and ultra-high performance by blending redox-active semiconducting polymers with a redox-inactive photocurable and/or photopatternable polymer to form an ion-permeable semiconducting channel, implemented in a simple, scalable vertical architecture that has a dense, impermeable top contact. Footprint current densities exceeding 1 kA cm−2 at less than ±0.7 V, transconductances of 0.2–0.4 S, short transient times of less than 1 ms and ultra-stable switching (>50,000 cycles) are achieved in, to our knowledge, the first vertically stacked complementary vertical OECT logic circuits. This architecture opens many possibilities for fundamental studies of organic semiconductor redox chemistry and physics in nanoscopically confined spaces, without macroscopic electrolyte contact, as well as wearable and implantable device applications.

semiconductor channel. The vOECT fabrication process is illustrated in Fig. 1a and details can be found in the Methods. The key to this process is the use of a redox-active p-type (gDPP-g2T) or n-type (Homo-gDPP) semiconducting polymer blended with a redox-inert and photocurable polymer component (cinnamate-cellulose polymer (Cin-Cell)) as the OECT channel (see the structures in Fig. 1b, the synthesis process in the Methods and Extended Data Fig. 1). On the basis of the control experiments (vide infra) the optimal semiconducting polymer:Cin-Cell weight ratio was found to be 9:2. A vOECT geometry cross-section and selected optical and scanning electron microscopy (SEM) images (Fig. 1c,d) indicate that the channel length (L) is the semiconductor layer thickness (approximately 100 nm), the widths of the bottom and the top electrodes define the channel width (W) and the nominal depth (d) of the semiconductor, respectively. cOECTs and vOECTs that use polymers without ion-conducting ethylene glycol side chains were also fabricated as controls; their performance is marginal (Extended Data Fig. 2).
Before evaluation of the device, the morphology and microstructure of the semiconducting polymer:Cin-Cell blend were characterized. As shown in Extended Data Fig. 3a,b, the pristine gDPP-g2T and HOMO-gDPP films are continuous and smooth (root-mean-square roughness, σ r.m.s. ≈ 1 nm), whereas both polymer blends with Cin-Cell are rougher after ultraviolet (UV) cross-linking/patterning (σ r.m.s. ≈ 3 nm) with evidence of phase separation in atomic force microscopy (AFM) (Fig. 1e), in which the Cin-Cell forms pillar-like structures that should enhance the structural robustness and stability. Thus, the Cin-Cell in the semiconducting matrix acts not only as a photopatterning component of the channel, but, most importantly, as an OECT structural stabilizer (vide infra). The two-dimensional grazing incidence wide-angle X-ray scattering (2D-GIWAXS, Extended Data Fig. 3c-e) patterns of the pure polymer and polymer:Cin-Cell mixture films are similar, corroborating phase separation and demonstrating that Cin-Cell addition does not substantially alter the overall film texturing and the polymer chain order.
Next, the vOECTs and cOECTs were tested and the performance parameters were extracted following standard procedures (Extended Data Table 1) 7,21 . Before discussing the results, note that control vOECTs based on semiconducting polymers without ethylene glycol side chains exhibit a negligible transistor response, demonstrating that the hydrophilic ion-complexing polymer facilitates ion penetration across the nanoscopic thin electrolyte-blend interface (Extended Data Fig. 2b,c). Furthermore, the performance of control vOECTs with varying Cin-Cell weight contents indicate (Extended Data Fig. 2d-g) that the device yield without Cin-Cell is low and, most importantly, that such devices are unstable after very few repeated gate voltage (V G ) cycles, mainly reflecting top electrode delamination, whereas those that use a semiconducting polymer:Cin-Cell weight ratio of more than 9:2 exhibit poor performance (low current on (I ON ) and large hysteresis), because of reduced redox-active polymer content and constricted ion diffusion. Consequently, all of the data reported here are for cross-linked semiconducting polymer:Cin-Cell blends with a 9:2 weight ratio.
The vOECT and cOECT transfer characteristics and the corresponding g m -subthreshold swing (SS) plots (Fig. 2a-d Fig. 4) demonstrate extraordinary performances for both p-and n-type vOECTs, achieving maximum drain currents (I ON ) of (8.2 ± 0.5) × 10 −2 A (drain voltage (V D ) = −0.5 V, V G = −0.5 V) and (2.5 ± 0.1) × 10 −2 A (V D = +0.5 V, V G = +0.7 V), and g m values as high as 384.1 ± 17.8 mS and 251.2 ± 7.6 mS, respectively (Fig. 2e). Note that despite the ultra-small channel lengths (L ≈ 100 nm), the I ON /current off (I OFF ) ratios of both devices are impressive (≥10 6 ), exclusively due to the higher I ON and low I OFF . All of the p-and n-type vOECTs retain stable turn-on voltages (V ON ) of +0. 10 (refs. 7,8,14,15,21,23-32 ). Importantly, the present vOECT structures also have reduced footprints because the contacting lines also function as source and drain contacts, eliminating the need for extra source-drain pads overlapping with the channel materials that are required in cOECTs. This vertical architecture and blending strategy with the Cin-Cell is also applicable to other mixed ionic-electronic semiconductors, with the vOECTs based on two p-type (Pg2T-T and PIBET-AO) and two n-type (polyethylene glycol-N2200 (PEG-N2200) and BTI2) polymers exhibiting similarly enhanced transistor performance versus their planar counterparts (Extended Data Fig. 5). To our knowledge, there are no examples of truly vertical electrochemical devices in which transistor behaviour is observed throughout the entire semiconductor bulk by using ion-impermeable contacts. Previously reported pioneering organic transistor architectures with vertical source-drain arrangements functioned as OECTs only when using permeable (for example, Ag nanowires) electrodes 22,26,33 , or when operated as electrical double-layer transistors or field-effect transistors. Therefore, bulk ion penetration and redox reactions are not involved, and only a small semiconductor volume under the top contact functions as the charge-carrying channel 34-38 . In contrast, the present approach uses simple thermal evaporation of dense and thick (150 nm) Au electrodes through a shadow mask, in combination with a photopatternable semiconductor layer, to create a structure with excellent ion intercalation. By using a semi-transparent Au top electrode (Extended Data Fig. 6a-c), Supplementary Video 1 demonstrates that the electrochromic switch associated with the redox chemistry encompasses the entire semiconductor area between the top and bottom electrodes and is not confined to the two narrow regions of the semiconductor that are in direct contact with the electrolyte. Evidence for bulk doping is further supported by the following observations: (1) I ON and g m of the vOECTs with different top electrode widths but identical bottom electrode widths, thus meaning an equal electrolyte-semiconductor interfacial area but a different semiconductor area or mass available for doping or de-doping, increase linearly (Extended Data Fig. 6d-f), illustrating that doping is not limited to the semiconductor-electrolyte interface. (2) Depletion-mode PEDOT:PSS vOECTs exhibit excellent switching behaviour and can be efficiently turned off (Extended Data Fig. 6g), which would be impossible if only interfacial redox chemistry was occurring in the vOECTs. (3) The measured saturation I ON values of the present vOECTs would carry unreasonably large electrical current densities (>10 7 A cm −2 ) if the channel were only few nanometres thick, as in typical electrical double-layer transistors. (4) Finally, devices based on very hydrophobic blends, which do not support ion intercalation across the nanoscopic interface, are non-functional (vide supra, Extended Data Fig. 2c).

and Extended Data
The present vOECTs also exhibit good transistor behaviour even when operated at a V D of only ±0.001 V (Extended Data Fig. 7a,b). Note, especially for the n-type vOECTs, V ON shifts from +0.43 to +0.21 V when V D is only increased from +0.001 to +0.1 V because of the drain-induced barrier lowering, which is a short channel effect 22 . For n-type cOECTs reported in the literature, and here specifically for Homo-gDPP cOECT control (Extended Data Fig. 4h), the energetic mismatch between the n-type semiconductor LUMO level and the Au electrode work function results in a very high V ON (>+0.4 V), and the limited electrochemical window of the aqueous electrolyte prevents the application of large V G biases. This is one of the key limitations of current n-type cOECTs 39 and it is where drain-induced barrier lowering plays a key role in the n-type vOECT performance enhancement seen here. Common issues of short channel transistors, such as loss of saturation 40 , V T roll-off and reduced current modulation 22 , which are equally as important, are absent in the vOECTs ( Fig. 2 and Extended Data Fig. 7c,d). This result is possible only if the redox processes modulate the carrier concentration of the entire semiconducting layer 2,41 . The low SS of approximately 60 mV per decade measured for both vOECTs (Fig. 2b,d) provides more convincing proof of the extremely effective gating in the present vertical architecture. Furthermore, unlike cOECTs in which the region with SS approximately 60 mV per decade, if achieved, is narrow (Extended Data Fig. 4g,h), the present vOECTs have a very wide subthreshold region (0.0 ≈ −0.2 V for gDPP-g2T and +0.3 ≈ +0.6 V for Homo-gDPP) with SS near or equalling the approximately 60 mV per decade thermal limit. The wide subthreshold region is particularly useful for applications in which high voltage gain and low power consumption are vital 42,43 . The cycling stability along with the transient response of the OECTs were next assessed. As shown in Fig. 3a,b, for both p-and n-type vOECTs, more than 50,000 stable switching cycles are recorded, which is an order of magnitude higher than for literature values of OECTs, especially for n-type devices 21,44 . Note that the stability of the ubiquitous PEDOT:PSS in depletion-mode vOECTs is also greatly stabilized compared to that in cOECT architectures (Extended Data Fig. 7e,f). Furthermore, the vOECT turn-on transient time (τ ON ) is less than 0.5 ms for both devices (Fig. 3c,d), and is comparable to those of the corresponding precisely patterned cOECTs (Extended Data Fig. 7g,h).
To validate the fast switching process and to understand the underlying mechanism, bandwidth and electrochemical impedance spectroscopy (EIS) measurements for both cOECTs and vOECTs were carried out (

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Video 2). On the basis of these results, it is fast bulk redox instead of interfacial doping near the semiconductor-electrolyte interface that is established, in which the short channel length leads to a strong electric field in the channel that effectively enhances the ion drift velocity, thereby leading to fast doping. Consequently, even in vOECTs for which the ion diffusion length is greater than 15 µm, the vOECT response times are amongst the shortest of the known n-type OECTs and are comparable to current state-of-the-art p-type OECTs, without extensive vOECT electrolyte or electrode patterning optimization 7,8,14,15,21,[23][24][25][26][27][28][29]45 .
So far, complementary logic has not been demonstrated for any type of vertical organic transistor architecture, mainly because of immaturity of the fabrication processes 22 . Here vertically stacked complementary inverters (VSCIs) are possible because of the unique vOECT   g-i, Photograph of NAND (g) and NOR (h) circuits, and the corresponding voltage input/output characteristics (i). j, Photograph of a rectifier and the corresponding output characteristics (k). Note, in photographs g,h and i, the electrolyte and Ag/AgCl are omitted to provide a better view of the channel areas.
operation mechanism, simple fabrication process and high stability of the present devices. Figure 4a shows a schematic of the VSCI, in which the n-type vOECT is located directly on top of the p-type vOECT. Such three-dimensional geometries enable much higher integration densities that require a 50% smaller footprint per inverter (Fig. 4b).
The voltage output characteristics indicate that the VSCI possesses a sharp voltage transition with a gain of up to approximately 150 (driving voltage = +0.7 V, Fig. 4c) and is stable for more than 30,000 switching cycles (Fig. 4d), further corroborating the excellent stability of both the n-type and p-type vOECTs. Thus, the present VSCI can also be used as an effective ion sensor over a wide concentration range (1 µM to approximately 0.1 M of KCl aqueous solution, Extended Data Fig. 8e,f), for which the transition voltage of the inverter can be effectively modulated to near half of voltage drain drain, V DD /2.
In addition, a five-stage ring oscillator was fabricated based on the present VSCI ( Fig. 4e and Extended Data Fig. 9), and the output signal begins to oscillate between 0.0 and +0.7 V at a frequency of 17.7 Hz (V DD = +0.7 V, Fig. 4f). This corresponds to a propagation delay of approximately 5.6 ms for each inverter. Finally, NAND and NOR logic gates operating between 0.0 and +0.7 V (Fig. 4g-i and Extended Data Fig. 9) as well as a VSCI-based rectifier (0.35 V amplitude, Fig. 4j,k and Extended Data Fig. 9) were fabricated, demonstrating a versatile library of circuitry elements. Note that previous cOECT-based ring oscillators, NANDs and NORs were fabricated with unipolar p-type cOECTs 17,46-48 , whereas complementary circuits were limited at the preliminary stage of an inverter because of the low performance of the n-type cOECTs 12,14 . Thus, the present vOECTs enable not only VSCIs, which far outperform the corresponding state-of-the-art cOECT inverters 17,49,50 , but they also facilitate the integration of this electrochemical technology into more complex complementary electronics.
In summary, this work reports vOECTs that demonstrate unprecedented performances for both p-and n-type operation modes. The device architecture demonstrated here is enabled by the synthesis of new electro-active and ion-permeable semiconducting polymers and by the interface engineering of electro-active blend layers. The devices are accessible by conventional fabrication processes and provide high fidelity and stable performance characteristics. They open up opportunities for fundamentally new system designs in diverse applications including low-cost diagnostics, brain-machine interfaces, implantable and wearable devices, prosthetics and intelligent soft robotics, for which small effective footprints along with high g m and low driving voltage metrics are essential requirements. Moreover, vOECTs offer a new design paradigm for flexible and stretchable complementary devices and related logic circuits.

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After cooling to room temperature, the mixture was poured into 100 ml of MeOH + 1 ml of concentrated HCl. The resulting precipitate was collected by filtration and then purified by Soxhlet extraction using methanol, acetone, hexane and then chloroform. The chloroform portion was concentrated and then poured into MeOH (approximately 100 ml). The resulting precipitate was collected by vacuum filtration as a black solid (106.51 mg, yield 86%). 1  Synthesis of polymer Homo-gDPP. The polymer Homo-gDPP was synthesized by using the same method as used for gDPP-g2T. Compound 4 (199.00 mg, 0.21 mmol), compound 6 (124.57 mg, 0.21 mmol), Pd 2 (dba) 3 (5.00 mg) and P(o-tol) 3 (13.00 mg) were used as starting materials. The pure polymer was obtained as a black solid (100.00 mg, yield 62%).

Materials characterization
The 1 H and 13 C NMR spectra of the intermediates were recorded on a Bruker Ascend 500 MHz spectrometer by using deuterochloroform (CDCl 3 ) as the solvent at room temperature. The 1 H spectra of the polymers were recorded on a Bruker Ascend 500 MHz spectrometer by using dideutero-1,1,2,2-tetrachloroethane (C 2 D 2 Cl 4 ) at 100 °C, which was also used to estimate the molecular weight. The purity of the polymers was verified by elemental analysis carried out at Midwest Microlabs Inc.

VT-NMR and M n estimation by end-group analysis.
The solutions for the NMR experiments were prepared by dissolving approximately 5 mg of polymer in 0.7 ml of C 2 D 2 Cl 4 . The solutions were heated at 100 °C for 16 h before the measurements were taken to ensure complete dissolution of the polymer. The measurements were performed on a 400 MHz Bruker Avance III HD Nanobay at 100 °C, and the spectra were referenced to C 2 DHCl 4 at 5.90 ppm. End-groups were identified based on literature compounds of similar structure 55,56 . Calculation of the M n from the end-group analysis is based on equation (1), which is described in the literature 57 .

OECT and complementary circuit fabrication
Semiconductor solution preparation. The gDPP-g2T, Homo-gDPP and Cin-Cell were first dissolved in chloroform at a concentration of 20 mg ml −1 and were filtered through a 0.45 µm polyvinylidene difluoride filter. Then, the gDPP-g2T or Homo-gDPP solution was mixed with the Cin-Cell solution in a volume ratio of 9:2 for device fabrication by using the blends. For Pg2T-T, PIBET-AO, PEG-N2200 and BTI2, they were also first dissolved in chloroform at a concentration of 20 mg ml −1 and were filtered through a 0.45 µm polyvinylidene difluoride filter, then mixed with the Cin-Cell solution in a volume ratio of 9:2. For PEDOT:PSS (Xi'an Polymer Light Technology Corp.), a solution containing 1 ml of PH1000 (solid content approximately 1.3%, PEDOT content approximately 0.37%), 1 polyethylene glycol dimethacrylate (1.2:1 weight ratio versus PEDOT), 5 wt% of Irgacure 2959 (versus polyethylene glycol dimethacrylate) and 1 wt% of Capstone FS-30 (versus PH1000) 58 was prepared.

Conventional OECT fabrication.
A Si wafer with a 300-nm-thick SiO 2 layer was used as the substrate. It was ultrasonically cleaned, first in an isopropyl alcohol bath for 20 min and then with oxygen plasma for 5 min. The S1813 photoresist was spin-coated at 4,000 rpm for 45 s, followed by annealing at 110 °C for 60 s and was then exposed under a maskless aligner system (MLA150; Heidelberg Instruments), developed in AZ400k (Microchemicals) for 40 s, rinsed with deionized water and blow-dried. Next, 3 nm of Cr and 50 nm of Au were deposited by thermal evaporation and were developed by soaking in acetone for 5 min to remove the S1813. Here, the patterned planar Au source-drain electrodes defined the channel dimension of W = 100 µm and L = 10 µm. The p-or n-type semiconductor blend solution was then spin-coated at 3,000 rpm for 20 s and was UV cross-linked for 30 s (Inpro Technologies F300S). At last, a droplet (approximately 1-20 µl, based on the channel area) of phosphate buffer solution (PBS, 1×) was applied onto the electrode overlapping area, and an Ag/AgCl electrode was inserted in the droplet acting as the OECT gate electrode. For the well-patterned cOECTs, the fabrication process can be found in the literature 59 , and the devices have patterned semiconductor areas (100 × 20 µm 2 , in which the channel length is 10 µm, the channel width is 100 µm, the channel thickness is 100 nm and the overlap with the source and/or drain is 5 µm on each side) and encapsulated source-drain electrodes.
Vertical OECT fabrication. An illustration of the vOECT fabrication process can be also found in Fig. 1a. The vOECTs were also fabricated on a pre-cleaned Si/300 nm SiO 2 wafer. First, 3 nm of Cr and 150 nm of Au (rate approximately 0.5-2.0 Å s −1 ) were thermally evaporated with a shadow mask as the bottom source electrode. Next, the semiconductor blend solution was spin-coated on the substrate at 3,000 rpm for 20 s. The semiconducting layer was then UV cross-linked for 30 s (Inpro Technologies F300S). Note that the semiconducting layer can be further patterned by developing it in chloroform for 3 s and blow-drying if cross-linked with a photomask. The top drain electrode (150 nm Au) was then thermally evaporated (rate approximately 0.5-2.0 Å s −1 ) with a shadow mask while maintaining the substrate at a temperature of approximately 20 °C with a back water-cooling system. Finally, a droplet (approximately 1-20 µl, based on the channel area) of PBS (1×) was applied on the electrode overlapping area, and an Ag/AgCl electrode was inserted in the droplet acting as the OECT gate electrode. Control devices using the pure semiconductors were fabricated following the same procedure but by using pure polymer solutions and without UV exposure.

Complementary inverter fabrication.
An illustration of the fabrication process can be found in Extended Data Fig. 9a. For the inverter fabrication, a layer of the opposite type of semiconductor blend was spin-coated (3,000 rpm for 20 s) directly onto the first vOECT (before applying the PBS electrolyte and the Ag/AgCl electrode), and was UV cross-linked for 30 s. Next, the third Au electrode (150 nm) was evaporated with a shadow mask as describe above. Note that the third Au electrode was carefully aligned to overlap with the active area of the bottom vOECT. Finally, a droplet (approximately 1-20 µl, based on the channel area) of PBS (×1) was applied on the electrode overlapping area, and an Ag/AgCl electrode was inserted in the droplet acting as V IN of the inverter.
Complementary ring oscillator fabrication. An illustration of the fabrication process can be found in Extended Data Fig. 9b. The five-stage ring oscillator was also fabricated on a pre-cleaned Si/300 nm SiO 2 wafer. First, 3 nm Cr and 150 nm Au were thermally evaporated with a shadow mask as the bottom electrode (V DD ). Next, the p-type gDPP-g2T:Cin-Cell mixture solution was spin-coated on the substrate at 3,000 rpm for 20 s and was cross-linked under UV light for 30 s with a shadow mask. The film was patterned by immersing it in chloroform for 3 s and blow-drying. Next, 150 nm Au were thermally evaporated with a shadow mask as the middle electrode (V OUT ). The n-type Homo-gDPP:Cin-Cell mixture was then spin-coated and photopatterned in the same way as for the p-type polymer blend. Then, 150 nm Au top electrode (ground, GND) was thermally evaporated with a shadow mask. Pure Cin-Cell solution was then spin-coated at 5,000 rpm for 20 s, cross-linked under UV light for 60 s with a shadow mask and developed in chloroform for 3 s, to leave openings for the active channel areas and V OUT electrodes. A Ag/AgCl paste (Creative Materials, 125-20) was applied on the V OUT electrodes of each inverter and vacuum dried for 30 min. Finally, a drop of PBS electrolyte (approximately 2 µl) was applied on each V OUT electrode and its adjacent inverter active channel area. NAND and NOR fabrication. An illustration of the fabrication process can be found in Extended Data Fig. 9c,d. NAND and NOR logic gates were also fabricated on a pre-cleaned Si/300 nm SiO 2 wafer. First, 3 nm Cr and a 150 nm Au were thermally evaporated with a shadow mask as the bottom electrode. Next, the p-type gDPP-g2T:Cin-Cell mixture solution was spin-coated on the substrate at 3,000 rpm for 20 s and was cross-linked under UV light for 30 s with a shadow mask. The film was patterned by immersing in chloroform for 3 s and blow-dried. Next, 150 nm Au were thermally evaporated with a shadow mask as the middle electrode (V OUT ). The n-type Homo-gDPP:Cin-Cell mixture was then spin-coated and photopatterned in the same way as for the p-type polymer blend but with a different shadow mask. Then, 150 nm Au top electrode was thermally evaporated with a shadow mask. Pure Cin-Cell solution was spin-coated at 5,000 rpm for 20s, cross-linked under UV light for 60 s with a shadow mask and developed in chloroform for 3 s, to leave openings for the active channel areas. Finally, two drops of PBS electrolyte (approximately 2 µl) were applied on each V IN area along with two Ag/AgCl electrodes as V IN-A and V IN-B , respectively.
Rectifier fabrication. An illustration of the fabrication process can be found in Extended Data Fig. 9e. The rectifier was also fabricated on a pre-cleaned Si/300 nm SiO 2 wafer. First, 3 nm Cr and 150 nm Au were thermally evaporated with a shadow mask as the bottom electrode (V OUT ). Next, the p-type gDPP-g2T:Cin-Cell mixture solution was spin-coated on the substrate at 3,000 rpm for 20 s and was cross-linked under UV light for 30 s with a shadow mask. The film was patterned by immersing it in chloroform for 3 s and blow-drying. Next, 150 nm Au were thermally evaporated with a shadow mask as middle electrode (V IN+ and V IN− ). The n-type Homo-gDPP:Cin-Cell mixture was then spin-coated and photopatterned as that of the p-type polymer blend. Then, 150 nm Au top electrode (GND) was thermally evaporated with a shadow mask. Pure Cin-Cell solution was then spin-coated at 5,000 rpm for 20 s, cross-linked under UV light for 60 s with a shadow mask and developed in chloroform for 3 s to leave openings for the active channel areas and V IN electrodes. A Ag/AgCl paste (Creative Materials, 125-20) was applied on the V IN electrodes and was vacuum dried for 30 min. Finally, two drops of PBS electrolyte (approximately 2 µl) were applied on each V IN electrode and its adjacent active channel area.

Device characterization
Transistor measurement. The electrical characterization of the OECTs and inverters was carried with an Agilent B1500A semiconductor parameter analyser in ambient conditions. The voltage sweeping speed was 0.1 V s −1 for the OECT measurements. For the transistor and inverter cycling tests, the voltage pulse was generated by a Keysight waveform generator (33500B), whereas the current-voltage variation was monitored with an Agilent B1500A. During the cycling tests, to maintain a relatively stable PBS electrolyte concentration, a PDMS mould was placed on top of the device active area to confine the electrolyte displacement and to slow water evaporation. Transient time measurements were carried out with an FS-Pro (PDA) semiconductor parameter analyser. For the ring oscillator characterization, a constant V DD of +0.7 V was applied with an Agilent B1500A, and the V OUT was monitored by an oscilloscope (Tektronix, TDS 2014). For NAND and NOR characterization, square pulses (from 0.0 to ±0.7 V) with a frequency of 5 Hz and 10 Hz were applied as V IN-A and V IN-B , respectively, by a Keysight waveform generator (33500B), and V OUT was monitored by an Agilent B1500A. For rectifier characterization, two sinusoidal V IN (V IN+ and V IN− have a phase difference of 180°) with an amplitude of 0.35 V were generated by a Keysight waveform generator (33500B), and the V OUT was monitored by an Agilent B1500A. All measurements were carried out in ambient conditions. EIS measurements. All measurements were conducted by using a PalmSens4 potentiostat (PalmSens) with an Ag/AgCl pellet (Warner Instruments) as the reference and counter electrode, and a gold electrode coated with active materials as the working electrode. For measurements on the vertical structure, details can be found in Extended Data Fig. 7, which were performed in PBS (1×) electrolyte with a direct current offset as 0.5 V (for the p-type material) and −0.7 V (for the n-type material), superimposed by a 10 mV alternating current (a.c.) oscillation. The frequency of the a.c. oscillation ranges from 0.1 to 10 5 Hz.
Bandwidth measurements. Bandwidth measurements were conducted by accessing the g m of the OECT as a function of the frequency of the gate voltage oscillation. The National Instruments (NI) SMU unit (NI PXIe-4143) was used for sourcing and measuring the drain-source voltage and current, as well as the gate current. The gate voltage was applied by using the data acquisition (DAQ) card from NI (NI PXIe-6363)] and was measured with a NI BNC-2110. During the measurement, V DS is equal to −0.5 V (p-type) and 0.5 V(n-type), whereas V G is equal to −0.5 V (p-type) and 0.7 V (n-type), superimposed by a 10 mV a.c. oscillation. The frequency of the a.c. oscillation ranges from 1 to 10 4 Hz. All measurements were automated by using a custom LabVIEW programme (NI) and the data were processed by using the MATLAB software (Mathworks).

Semiconductor film characterization
SEM characterizations were carried out on a Hitachi SU8030 FE-SEM. AFM characterizations were acquired with a Bruker ICON System. GIWAXS measurements were performed at Beamline 8-ID-E1 at the Advanced Photon Source (APS) at Argonne National Laboratory. Samples were irradiated with a 10.9 keV X-ray beam at an incidence angle 0.125° to 0.135° in a vacuum for two summed exposures of 2.5 s (totalling 5 s of exposure), and scattered X-rays were recorded by a Pilatus 1 M detector located 228.16 mm from the sample at two different heights.

Discussion of the calculated mobilities of cOECT and vOECTs
The carrier mobilities of both the gDPP-g2T:Cin-Cell and Homo-gDPP:Cin-Cell were measured in vertical and planar OECTs 59 . For the planar or conventional architecture, the carrier mobility of the p-type cOECT is found to be 1.69 ± 0.19 cm 2 V −1 s −1 , which is comparable to other high-performance p-type OECTs. The n-type cOECT exhibits a high mobility of 0.13 ± 0.03 cm 2 V −1 s −1 , which is among the highest reported up until now. However, for the vertical devices, the calculated carrier mobilities are much lower, (3.33 ± 0.27) × 10 −3 cm 2 V −1 s −1 and (3.06 ± 0.61) × 10 −3 cm 2 V −1 s −1 for the p-type and n-type vOECTs, respectively.
The much lower and similar carrier mobilities in the vOECTs probably originate from the large series resistance from the source-drain electrodes and, to a lesser extent, the non-optimal polymer morphology of the spin-coated films, which typically enhances in-plane rather than out-ofplane organic semiconductor charge transport. Because the measured channel resistance in the vertical structure in the on-state is less than 10 Ω, series resistances originating at the electrode-semiconductor interface and within the electrode contact will reduce the measured drain current notably 16 . Overall, these observations indicate that further optimization of charge injection and connecting-line conductivity, and the use of organic semiconductors that favour vertical charge transport as in those for organic photovoltaics, will probably enhance the current densities even further. Nevertheless, to properly evaluate the true carrier mobilities for the unconventional vertical architecture reported here, additional modelling and simulation efforts are required. This would be of great interest to the entire community.

Data availability
Source data are provided with this paper. Additional data related to this work are available from the corresponding authors upon request.