Digital logic circuits are based on complementary pairs of n- and p-type field effect transistors (FETs) via complementary metal oxide semiconductor technology. In three-dimensional (3D) or bulk semiconductors, substitutional doping of acceptor or donor impurities is used to achieve p- and n-type FETs. However, the controllable p-type doping of low-dimensional semiconductors such as two-dimensional (2D) transition-metal dichalcogenides (TMDs) has proved to be challenging. Although it is possible to achieve high-quality, low-resistance n-type van der Waals (vdW) contacts on 2D TMDs1,2,3,4,5, obtaining p-type devices by evaporating high-work-function metals onto 2D TMDs has not been realized so far. Here we report high-performance p-type devices on single- and few-layered molybdenum disulfide and tungsten diselenide based on industry-compatible electron beam evaporation of high-work-function metals such as palladium and platinum. Using atomic resolution imaging and spectroscopy, we demonstrate near-ideal vdW interfaces without chemical interactions between the 2D TMDs and 3D metals. Electronic transport measurements reveal that the Fermi level is unpinned and p-type FETs based on vdW contacts exhibit low contact resistance of 3.3 kΩ µm, high mobility values of approximately 190 cm2 V−1 s−1 at room temperature, saturation currents in excess of 10−5 A μm−1 and an on/off ratio of 107. We also demonstrate an ultra-thin photovoltaic cell based on n- and p-type vdW contacts with an open circuit voltage of 0.6 V and a power conversion efficiency of 0.82%.
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Improvements in 2D p-type WSe2 transistors towards ultimate CMOS scaling
Scientific Reports Open Access 27 February 2023
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M.C. and Y.W. received funding from the European Research Council (ERC) Advanced Grant under the European Union’s Horizon 2020 research and innovation programme (grant agreement GA 101019828-2D- LOTTO]), Leverhulme Trust (RPG-2019-227), EPSRC (EP/ T026200/1, EP/T001038/1) and Royal Society Wolfson Merit Award (WRM\FT\180009). H.Y.J. acknowledges support from the National R&D Program through the National Research Foundation of Korea funded by the Ministry of Science and ICT (2022M3H4A1A01013228).
The authors declare no competing interests.
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Extended data figures and tables
Extended Data Fig. 1 Au contacts on MoS2 and WSe2.
a, Cross-sectional STEM image of a Au-WSe2 device showing cleaning van der Waals interface. Scale bar = 5 nm. b, Transfer curves of WSe2 device with Au contact showing p-type results. W = 4 µm, L = 1.5 µm. c, Output curves of WSe2 device with Au contacts. The non-linear I-V curves indicate high Schottky barrier with Au contacts for WSe2. d, Transfer curves of MoS2 device with Au contacts on PMMA/SiO2 substrate showing ambipolar behavior with dominant electron current. W = 8 µm, L = 10 µm. e, Output curves of MoS2 device with Au contacts.
Extended Data Fig. 2 Pd contacts on WSe2.
a, Left and right, cross-sectional STEM of the Pd-WSe2 interface. Scale bar = 1 nm. b, XPS of Pd-WSe2 interface showing the presence of PdSe2 peaks, indicating reaction between the deposited metal and the Se atoms.
Extended Data Fig. 3 Low temperature measurements.
a, Transfer curves of MoS2 device with Pd contacts on PMMA/SiO2 substrate at different temperatures. The hole transport part showed a more obvious temperature dependence compared to the electron branch, indicating thermally activated transport for holes and tunnel dominant transport for electrons due to higher Schottky barrier for electrons. b, Transfer curves from a plotted linearly. c, Schottky barrier extraction for holes in multilayer MoS2 with Pd contacts. d, Transfer curves of WSe2 device with Pt contacts at different temperatures. e, Transfer curves from d plotted linearly. f, Schottky barrier extraction for holes in multilayer WSe2 with Pt contacts.
Extended Data Fig. 4 Hysteresis in WSe2 FETs.
Forward (red) and reverse (black) scans for multi-layer (a) and monolayer (b) WSe2 FETs with Pt electrodes on SAM treated SiO2. c, Transfer characteristics of the same monolayer WSe2 FET measured in air and vacuum. It can be clearly seen that the hysteresis decreases in vacuum suggesting it is caused by adsorbates and not any defects at the contacts.
Extended Data Fig. 5 Pt on WSe2 without optimized deposition parameters.
a, Cross-sectional STEM of Pt/WSe2 interface without optimization of the deposition conditions. b, Transfer curve of WSe2 FET with damaged interface showing very poor p-type characteristics.
Extended Data Fig. 6 Device performance of MoS2 with Pt contacts and WSe2 with Pd contacts.
a, Transfer curves for MoS2 device with Pt contacts showing ambipolar characteristics with higher electron branch. W = 4 µm, L = 10 µm. b, Output curves of MoS2 device with Pt contacts. c, Transfer curves of WSe2 device with Pd contacts showing ambipolar characteristics with higher hole branch. W = 38 µm, L = 10 µm. d, Output curves of WSe2 device with Pd contacts showing non-ideal characteristics.
Extended Data Fig. 7 Work function measurements of Pd and Pt thin films on TMDs.
a, AFM image of ~3 nm Pt deposited on cleaved MoS2 crystal. b, Height profile of the blue line in the AFM image showing uniform growth of Pt on MoS2. c, UPS result of Pd thin film on MoS2 showing work function ~5.2 eV. d, UPS result of Pt thin film on WSe2 showing work function ~5.0 eV.
Extended Data Fig. 8 Properties of MoS2 FETs with Pd (a-f) and Pt (g-l) contacts on different substrates.
a, b, Transfer and output curves of MoS2 FET with Pd contacts on SiO2. W = 4 µm, L = 1 µm. c, d, Transfer curves of MoS2 FET with Pd contacts on hBN. W = 3 µm, L = 1.5 µm. e, f, Transfer and output curves of MoS2 FETs with Pd contacts on PMMA. W = 16 µm, L = 10 µm. g, h, Transfer and output curves of MoS2 FET with Pt contacts on SiO2. W = 6 µm, L = 0.8 µm. i, j, Transfer and output curves of MoS2 FET with Pt contacts on hBN. W = 2.5 µm, L = 1 µm. k, l, Transfer and output curves of MoS2 FET with Pt contacts on PMMA. W = 25 µm, L = 10 µm. It can be seen that Pd contacts lead to higher hole current for MoS2 FETs compared to Pt contacts and the substrates have some influence on the hole injection level.
Extended Data Fig. 9 Properties of WSe2 FETs with Pd (a-f) and Pt (g-l) contacts on different substrates.
a, b, Transfer and output curves of WSe2 FET with Pd contacts on SiO2. W = 6.5 µm, L = 1 µm. c, d, Transfer and output curves of WSe2 FET with Pd contacts on hBN. W = 6.5 µm, L = 0.8 µm. e, f, Transfer and output curves of WSe2 FET with Pd contacts on PMMA. W = 25 µm, L = 10 µm. g, h, Transfer and output curves of WSe2 FET with Pt contacts on SiO2. W = 4 µm, L = 0.8 µm. i, j, Transfer and output curves of WSe2 FET with Pt contacts on hBN. W = 1.8 µm, L = 2.5 µm k, l, Transfer and output curves of WSe2 FET with Pt contacts on PMMA. W = 5 µm, L = 10 µm. The results show poor p-type performance of WSe2 FETs with Pd contacts on all different substrates.
Extended Data Fig. 10 WSe2 FETs with different contacts on different substrates.
The scatter plots show the ratio of electron to hole current (Ielectron/Ihole) of WSe2 FETs fabricated on different substrates (SiO2, hBN, PMMA and SAM treated SiO2 substrate) using different contacts (In, Au, Pd and Pt). The results excluded the p-type characteristics originate from SAM doping as the trend shows the polarity clearly varies with different contacts.
Extended Data Fig. 11 CVD grown WSe2 and MoS2.
a, Optical image of CVD grown WSe2 on SiO2. Scale bar = 10 μm. b, Raman of WSe2 showing pristine WSe2. c, PL of monolayer WSe2 showing a peak at ~ 1.65 eV. d, Optical image of CVD grown MoS2 on SiO2. Scale bar = 20 μm. e, Raman of MoS2 showing pristine MoS2. f, PL of MoS2 with a peak at ~1.83 eV.
Extended Data Fig. 12 Schottky barrier height for monolayer WSe2.
a, Transfer curves of monolayer WSe2 FET device with Pt contacts on SAM treated SiO2 substrate measured at different temperatures. b, Transfer curves from a plotted linearly. c, The extracted Schottky barrier height for the monolayer WSe2 is ~400 meV, which is 200 meV higher than multilayer WSe2 FETs due to higher valence band edge of monolayer WSe2.
Extended Data Fig. 13 The influence of deposition rate on metal/2D TMD interface.
a, Optical microscope image of a device where the metal (Au in this case) was deposited at a deposition rate of 0.1 Å/s. To achieve 50 Å, the deposition was conducted for just over eight minutes. The radiative heat emitted from the evaporation crucible causes severe damage to the device. b, Cross-sectional atomic resolution ADF STEM image shows that the interface is damaged in this case (arrow indicating mixing of Au atoms with the S atoms of MoS2. c, d, In contrast, when the deposition is done quickly (deposition rate = 2 Å/s) and in multiple steps, the device is undamaged and the interface shown in panel d is ultra-clean.
Extended Data Fig. 14 Evaporation procedures for clean high work function contacts.
a, Summary of e-beam evaporation current and voltage applied to deposit Au, Pd and Pt at 0.1 Å/s and 2 Å/s. The irradiation energy supplied to the device for high rate deposition is much lower than for low rate deposition. b, Comparison of substrate temperature versus time for 300 Å Pt depositions done in single and multiple steps. The left figure (single step deposition) shows that during deposition, the temperature of the holder gradually increases with time. For deposition with steps, the chamber and substrate holder were allowed to cool to room temperature before running the next deposition. Thus, the temperature of the sample remained lower than deposition without steps.
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Wang, Y., Kim, J.C., Li, Y. et al. P-type electrical contacts for 2D transition-metal dichalcogenides. Nature 610, 61–66 (2022). https://doi.org/10.1038/s41586-022-05134-w
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