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An on-chip photonic deep neural network for image classification


Deep neural networks with applications from computer vision to medical diagnosis1,2,3,4,5 are commonly implemented using clock-based processors6,7,8,9,10,11,12,13,14, in which computation speed is mainly limited by the clock frequency and the memory access time. In the optical domain, despite advances in photonic computation15,16,17, the lack of scalable on-chip optical non-linearity and the loss of photonic devices limit the scalability of optical deep networks. Here we report an integrated end-to-end photonic deep neural network (PDNN) that performs sub-nanosecond image classification through direct processing of the optical waves impinging on the on-chip pixel array as they propagate through layers of neurons. In each neuron, linear computation is performed optically and the non-linear activation function is realized opto-electronically, allowing a classification time of under 570 ps, which is comparable with a single clock cycle of state-of-the-art digital platforms. A uniformly distributed supply light provides the same per-neuron optical output range, allowing scalability to large-scale PDNNs. Two-class and four-class classification of handwritten letters with accuracies higher than 93.8% and 89.8%, respectively, is demonstrated. Direct, clock-less processing of optical data eliminates analogue-to-digital conversion and the requirement for a large memory module, allowing faster and more energy efficient neural networks for the next generations of deep learning systems.

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Fig. 1: Conventional and photonic–electronic deep neural networks.
Fig. 2: Photonic–electronic neuron implementation.
Fig. 3: The implemented photonic classifier chip.
Fig. 4: Image classification demonstration.

Data availability

The data that support the plots in Fig. 4 can be accessed at

Code availability

Codes that are used in this paper are available from the corresponding author on reasonable request.


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This work was supported by the Office of Naval Research of the United States under award number N00014-19-1-2248.

Author information

Authors and Affiliations



F. Ashtiani and F. Aflatouni conceived the design idea. F. Ashtiani designed, simulated and laid out the photonic chip. F. Ashtiani and A.J.G. conducted the measurements. F. Aflatouni supervised the project. F. Ashtiani and F. Aflatouni wrote the manuscript.

Corresponding author

Correspondence to Firooz Aflatouni.

Ethics declarations

Competing interests

F. Aflatouni and F. Ashtiani have filed a patent on the proposed PDNN architecture (publication number WO2022020437A1).

Peer review

Peer review information

Nature thanks Wolfram Pernice and the other, anonymous, reviewer(s) for their contribution to the peer review of this work.

Additional information

Publisher’s note Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Extended data figures and tables

Extended Data Fig. 1 Image formation and measurement setup.

a, The input pixel array aperture and grating coupler (pixel) design are shown. The printed circuit board (PCB) is tilted (by about 12°) to maximize the pixel efficiency at 1,532 nm. b, Classification measurement setup. Laser 1, emitting at 1,532 nm, serves as the light source for image formation on the input pixel array (in the classification phase) or the calibration array (in the training phase), whereas laser 2, emitting at 1,559.93 nm, is used as the supply light. The target objects (dataset) are printed on a transparency film mounted on a custom-fabricated frame. A high-precision XY positioner is used for scanning through the dataset. A microcontroller is used to write the weights into the photonic chip and to implement MRM alignment control loops.

Extended Data Fig. 2 PDNN chip training and threshold calculations.

a, The implemented algorithm to find and revise the threshold values to properly separate N different classes. A linear combination of the network output, in this case, the differential output defined as Vout = Out1 − Out2, is measured and compared with different threshold levels. The threshold values (THj) are revised one by one as measured network differential output values (Vout,i) are sequentially passed into the algorithm.

Extended Data Fig. 3 Propagation time measurement.

a, Propagation time measurement setup and packaging. b, Calibration setup using a test structure, which consists of a grating coupler and a PD. c, Two detected pulses at nodes A and B showing an end-to-end system delay of about 570 ps. d, Measurement setup used to show the effect of the forward-biased MRM response on the pulse shape.

Extended Data Fig. 4 Comparison with the state of the art.

Image classification schemes implemented using optical and electronic neural networks.

Extended Data Fig. 5 Scalability and computation time enhancement methods.

a, An N-layer photonic neural network, in which each layer has its dedicated supply light, allowing scalability to a deep network with a large number of layers. Bandwidth enhancement by absorbing the parasitic capacitance of PDs in a lumped-element transmission line (b) and using one PD per neuron (after optical combining) (c).

Extended Data Fig. 6 Micro-ring alignment algorithm and characterization.

a, The implemented algorithm flow chart for micro-ring alignment. The cost function to be minimized is VSUM, which is the sum of the outputs of the second and third layers (that is, Hi and Oi). All micro-rings are thermally tuned to find the optimal heater voltages that correspond to the same resonance wavelength for all seven rings. b, In case of no input illumination, the outputs of the neurons of the first layer (Ii) are zero. If micro-rings are properly aligned, the outputs of the neurons of the second and third layers remain low. c, In the case that the optical input is uniformly illuminating the input pixel array, if all rings are aligned, I1 to I4 will increase, shifting the resonance wavelengths of the MRMs, which results in a large change in the outputs of the neurons of the second and third layers.

Extended Data Fig. 7 Electronic control circuit block diagram.

The microcontroller sends the clock and data signals to the serial DACs, whereas the outputs of the DACs are connected to their corresponding drivers to drive the on-chip photonic devices (PIN attenuators, ring PN junctions and micro-ring thermal phase shifters).

Extended Data Table 1 Performance metrics of the different on-chip devices
Extended Data Table 2 Performance comparison with state-of-the-art optical and electronic implementations
Extended Data Table 3 List of equipment and devices

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Ashtiani, F., Geers, A.J. & Aflatouni, F. An on-chip photonic deep neural network for image classification. Nature 606, 501–506 (2022).

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