The scaling of silicon metal–oxide–semiconductor field-effect transistors has followed Moore’s law for decades, but the physical thinning of silicon at sub-ten-nanometre technology nodes introduces issues such as leakage currents1. Two-dimensional (2D) layered semiconductors, with an atomic thickness that allows superior gate-field penetration, are of interest as channel materials for future transistors2,3. However, the integration of high-dielectric-constant (κ) materials with 2D materials, while scaling their capacitance equivalent thickness (CET), has proved challenging. Here we explore transferrable ultrahigh-κ single-crystalline perovskite strontium-titanium-oxide membranes as a gate dielectric for 2D field-effect transistors. Our perovskite membranes exhibit a desirable sub-one-nanometre CET with a low leakage current (less than 10−2 amperes per square centimetre at 2.5 megavolts per centimetre). We find that the van der Waals gap between strontium-titanium-oxide dielectrics and 2D semiconductors mitigates the unfavourable fringing-induced barrier-lowering effect resulting from the use of ultrahigh-κ dielectrics4. Typical short-channel transistors made of scalable molybdenum-disulfide films by chemical vapour deposition and strontium-titanium-oxide dielectrics exhibit steep subthreshold swings down to about 70 millivolts per decade and on/off current ratios up to 107, which matches the low-power specifications suggested by the latest International Roadmap for Devices and Systems5.
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Inorganic Halide Perovskite Quantum Dots: A Versatile Nanomaterial Platform for Electronic Applications
Nano-Micro Letters Open Access 29 December 2022
Nature Communications Open Access 18 July 2022
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The data needed to evaluate the conclusions in this work are publicly available online at https://doi.org/10.5281/zenodo.6245863. Additional data related to this paper may be requested from the corresponding authors upon reasonable request.
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We thank the Australian Research Council Discovery Project of DP19010366 for the financial support; the facilities, as well as the scientific and technical assistance, of the NSW Node of the Australian National Fabrication Facility (ANFF) and the Research and Prototype Foundry Core Research Facility at the University of Sydney, part of the ANFF; and the units and facilities within the Mark Wainwright Analytical Centre at UNSW Sydney for the assistance in material analyses. Z.W. thanks L.Li in Peking University for providing assistance in the TCAD simulation; L.-J.L. and Y.W. thank the support from the University of Hong Kong; and Y.-P.C. acknowledges the financial support from Ministry of Science and Technology (MOST) of Taiwan (contract numbers MOST 110-2119-M-002-015-MBK and MOST 110-2622-8-002-014).
J.-K.H., J.S., J.Z. and S.L. are co-inventors on a patent application (Australian provisional filing numbers 2021902514 and 2022900344) related to the research presented in this paper.
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Extended data figures and tables
a, b, AFM topography and cross-sectional height profile of an as-grown SrTiO3 film indicating an atomically smooth surface with unit cell step terraces. The scale bar is 1 µm. c, 2θ–ω X-ray diffraction the scan of SrTiO3/Sr3Al2O6/epi-SrTiO3 heterostructure. d, The experimental and fitted XRR curves, where the fitting adequately describes the true structure (SrTiO3/Sr3Al2O6/epi-SrTiO3). e, X-ray SLD model used to fit the experimental data. The model represents SrTiO3/Sr3Al2O6 (9.9nm)/epi-SrTiO3 (2.1nm).
a-d, 10 u.c., 20 u.c., 40 u.c., and 80 u.c. thick SrTiO3 thin films and selected cross-sectional height profiles showing the thickness, respectively. The scale bar indicates 1 µm. e, Thicknesses extracted from various AFM measurements of the transferred thin film. Note that the theoretical thickness of one u.c. thick SrTiO3 is 0.3905 nm (ref. 22).
a, RSM of transferred 80 u.c. SrTiO3 film around (002), (103), and (013) planes. b, Relative values shown in (a) and extracted lattice parameters. QX, QZ: reciprocal space coordinates. c, High-resolution XPS spectra and analysis of the released SrTiO3 film at Sr 3d, Ti 2p, and O 1s regions. The fitted Ti 2p and Sr 3d spectra indicate that there is no second phase presenting in the membranes while the O 1s spectra were extracted to both intrinsic O in the SrTiO3 and extrinsic O in hydroxyls absorbed on the surface48. d, Binding energy and stoichiometric analysis of XPS results49.
a, PL spectra and b, Raman spectrum of the as-grown CVD MoS2 monolayer before and after transferring on SrTiO3. Note the Raman frequency differences between E12g and A1g are less than 20 cm−1, indicating the monolayer nature50. c, Optical micrograph of the MoS2 FET at channel region. d, PL intensity mapping of the corresponding area. The scale bars indicate 4 µm.
a, MoS2 MOS capacitor measurements on 16.4 nm (40 u.c.) thick SrTiO3 layer. The accumulation capacitance of 3.45 μF/cm2 corresponds to ~ 1 nm CET. b, Transfer curves of MoS2 transistor with a 40 u.c. thick SrTiO3 gate dielectric. The sequential color column displays the results of the device swept from 1st to 115th times, and the red lines show the results of the first 10 sweeps from the same device after one-month storage.
a, Time to breakdown (TBD) of MOS devices with a 40 u.c. thick SrTiO3 dielectric at various voltage stresses. b, TBD versus stress voltage characteristics, where the black dash-line represents the E model fitting for lifetime prediction.
a, b, Transfer characteristic of the short-channel device with LCH = 55 nm and 25 nm, respectively. The scale bars indicate 50 nm.
a, b, Simulated equipotential contours of short-channel (10 nm) MoS2 FETs without vdW gap (a) and with 3Å vdW gap (b), where source and gate are grounded, VD = 1V, and SrTiO3 dielectric is set as 1 nm EOT according to our experimental results. c, Calculated conduction band diagrams of short-channel MoS2 FETs with 1 nm EOT gate dielectrics of SiO2 (κ = 3.9), HfO2 (κ = 22), and SrTiO3 (κ = 75), where 3 Å vdW gap was used. d, Corresponding transfer characteristics of simulated short-channel MoS2 FETs. e, Extracted SS values of the transfer characteristics with various vdW gap thicknesses.
a, Photograph of the experiment setup for mechanical bending of MoS2 FETs, where the samples are bent to a tensile strain of 0.54%. The strain at a given bending radius can be approximated by strain = d/2r where d is substrate thickness (0.125 mm) and r is the radius of curvature (11.5 mm)51. Inset is the photograph of MoS2 FET arrays on flexible and transparent PET substrate. b, Measured transfer characteristics of the device under flat, strained, and resumed conditions.
a-c, Evolution of RHEED patterns during the preparation of SrTiO3/Sr3Al2O6/epi-SrTiO3 heterostructure. d, RHEED intensity oscillations in the deposition process accordingly, which indicate the typical layer-by-layer 2D growth mode.
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Huang, JK., Wan, Y., Shi, J. et al. High-κ perovskite membranes as insulators for two-dimensional transistors. Nature 605, 262–267 (2022). https://doi.org/10.1038/s41586-022-04588-2
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