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Vertical MoS2 transistors with sub-1-nm gate lengths


Ultra-scaled transistors are of interest in the development of next-generation electronic devices1,2,3. Although atomically thin molybdenum disulfide (MoS2) transistors have been reported4, the fabrication of devices with gate lengths below 1 nm has been challenging5. Here we demonstrate side-wall MoS2 transistors with an atomically thin channel and a physical gate length of sub-1 nm using the edge of a graphene layer as the gate electrode. The approach uses large-area graphene and MoS2 films grown by chemical vapour deposition for the fabrication of side-wall transistors on a 2-inch wafer. These devices have On/Off ratios up to 1.02 × 105 and subthreshold swing values down to 117 mV dec–1. Simulation results indicate that the MoS2 side-wall effective channel length approaches 0.34 nm in the On state and 4.54 nm in the Off state. This work can promote Moore’s law of the scaling down of transistors for next-generation electronics.

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Fig. 1: Comparison of the 0.34 nm Lg side-wall transistor with other typical structure transistors.
Fig. 2: The 0.34 nm gate-length side-wall monolayer MoS2 transistor device structure and characterization.
Fig. 3: Electrical characterization of 0.34 nm gate-length side-wall transistors.
Fig. 4: TCAD simulation results and benchmark.

Data availability

The data that support the findings of this study are available from the corresponding author upon reasonable request.


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We thank W.-Z. Bao from Fudan University for valuable discussions. This work was supported by the National Natural Science Foundation of China (grant nos. 62022047, 61874065, U20A20168 and 51861145202), the National Key R&D Program (grant no. 2021YFC3002200 and 2020YFA0709800), The Beijing Natural Science Foundation (grant no. M22020), the Fok Ying-Tong Education Foundation (grant no. 171051), the Beijing National Research Center for Information Science and Technology Youth Innovation Fund (grant no. BNR2021RC01007), State Key Laboratory of New Ceramic and Fine Processing of Tsinghua University (grant no. KF202109) and the Research Fund from Beijing Innovation Center for Future Chip, Center for Flexible Electronics Technology  of Tsinghua University and the Independent Research Program of Tsinghua University (grant no. 20193080047).

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Authors and Affiliations



H.T. and T.-L.R. proposed the idea and the project. H.T. and F.W. designed the experiment. Y. Shen and Y. Sun performed the simulation. F.W., Z.H., G.G. and J.R. performed the device fabrication and characterization. Y.Y. provided suggestions to the manuscript. T.-L.R. and H.T. supervised the project. All the authors discussed the results and commented on the manuscript.

Corresponding authors

Correspondence to He Tian or Tian-Ling Ren.

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The authors declare no competing interests.

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Nature thanks Dennis Lin and the other, anonymous, reviewers(s) for their contribution to the peer review of this work.

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Extended data figures and tables

Extended Data Fig. 1 As-fabricated, Al-contacted graphene transistors.

(a, b) The IDS-VGS transfer curves and IDS-VDS output curves. The electrical conductivity is ~106 S/m at VGS = 0 V. (c) The optical image. After Al deposition and lift-off process, the samples were stored at 10−5 bar vacuum to avoid oxidization. (d) The device structure diagram. The channel width and channel length are 8 μm and 22 μm, respectively.

Extended Data Fig. 2 The quality verification of self-oxidized AlOx.

(a) The I-V curves another 10 devices. The 2.4 V voltage drop between graphene and Al is a safe value for the measurements. (b) A typical optical image of the measured structure. (c) The diagram of the measured structure. After Al deposited on graphene, the samples are stored in clean atmosphere condition for more than 3 days. Then, Al is surrounded by dense AlOx layer, and Pt is deposited after EBL process.

Extended Data Fig. 3 The EDS mapping of 0.34 nm gate-length side-wall transistor.

(a) The TEM image of this EDS mapping region in BF mode. (b–i) The EDS mapping of carbon (C), oxygen (O), aluminum (Al), silicon (Si), sulfur (S), titanium (Ti), molybdenum (Mo) and hafnium (Hf). The mapping of Mo and S verifies the presence of the 2D MoS2 channel. The C element seen on the top of MoS2 can be attributed to the organic residue like PMMA or contaminants from fabrication.

Extended Data Fig. 4 Back-gated planar MoS2 transistors.

(a) The measured structure. The channel width and channel length are 4 μm and 5 μm, respectively. (b–p)The IDS-VBG transfer curves under different VDS bias of the 15 typical back-gated planar MoS2 transistors. The MoS2 channel is highly n-doped when VBG = 50 V.

Extended Data Fig. 5 The tunability of the Al screening layer of the 0.34 nm gate-length side-wall transistor.

(a) The measured structure and signal input. (b) The IDS-VBS characteristics under different VAl bias, when graphene gate is fixed at 0 V.

Extended Data Fig. 6 The detailed tunability of the Al screening layer.

(a) The basic 0.34 nm graphene side-wall edge gated MoS2 transistor and signal input, the Al screening layer is connected to ground. (b) The IDS-VGr characteristics at VBS = 0 V and VAl = 0 V. The VDS varies from 10 mV to 3.0 V. (c) The 0.34 nm graphene side-wall edge gated MoS2 transistor and signal input, the Al screening layer is fixed at different bias. (d) The IDS-VGr characteristics at VDS = 0 V and VAl = 0 V. The VAl varies from –2.0 V to 2.0 V with 0.5 V step. (e) The Al side-wall gated MoS2 transistor and signal input, the graphene layer is connected to ground. (f) The IDS-VAl characteristics at VBS = 0 V and VGr = 0 V. The VDS varies from 10 mV to 3.0 V.

Extended Data Fig. 7 The reproducibility of the 0.34 nm gate-length side-wall transistors.

Additional 49 devices are measured at VBS = 50 V, VAl = 0 V and VDS = 1 V. From additional device 1 to device 28, the measured 0.34 nm gate-length side-wall transistors are with Lch = 1 μm; from additional device 29 to device 49, the measured 0.34 nm gate-length side-wall transistors are with Lch = 0.5 μm.

Extended Data Fig. 8 TCAD simulation for extracting the effective gate length in the Off state.

(a) The simulated transfer curve under VBS = 50 V, VAl = 0 V and VDS = 50 mV. (b) The carrier density along vertical MoS2 channel. By definition of Ioff = 10−12A and nthreshold = 2 × 1012 cm−3 (correspond to 1.3 × 105 cm−2), the Leff is 4.54 nm.

Extended Data Fig. 9 The TCAD simulation results of the 0.34 nm gate-length side-wall transistors to boost On-state performance.

The transfer curves by scaling down Lch from 500 nm to 4.54 nm shown in (a) log-scale and (b) linear-scale. The transfer curves under extreme Lch = 4.54 nm with different fixed Al bias shown in (c) log-scale and (d) linear-scale. The transfer curves under extreme Lch  = 4.54 nm by scaling down gate dielectric thickness from 14 nm to 5 nm shown in (e) log-scale and (f) linear-scale. Under 14 nm HfO2 as gate dielectric, VBS = 50 V, VAl = 0 V and VDS = 50 mV condition, the On-state current can be further improved ~2 orders of magnitude.

Extended Data Table 1 The detailed parameters for MoS2 channel with different layer numbers.
Extended Data Table 2 The detailed parameters for HfO2 and natural AlOx. Here, Tch is the channel thickness, Eg is the band gap, ε is the relative dielectric constant, χ is the electron affinity, me is the electron effective mass, μe is the electron mobility, the initial doping of MoS2 is 1016~1017 cm−3, and graphene is modeled as metal with work function set as 4.6 eV.

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Wu, F., Tian, H., Shen, Y. et al. Vertical MoS2 transistors with sub-1-nm gate lengths. Nature 603, 259–264 (2022).

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