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Ultralow contact resistance between semimetal and monolayer semiconductors


Advanced beyond-silicon electronic technology requires both channel materials and also ultralow-resistance contacts to be discovered1,2. Atomically thin two-dimensional semiconductors have great potential for realizing high-performance electronic devices1,3. However, owing to metal-induced gap states (MIGS)4,5,6,7, energy barriers at the metal–semiconductor interface—which fundamentally lead to high contact resistance and poor current-delivery capability—have constrained the improvement of two-dimensional semiconductor transistors so far2,8,9. Here we report ohmic contact between semimetallic bismuth and semiconducting monolayer transition metal dichalcogenides (TMDs) where the MIGS are sufficiently suppressed and degenerate states in the TMD are spontaneously formed in contact with bismuth. Through this approach, we achieve zero Schottky barrier height, a contact resistance of 123 ohm micrometres and an on-state current density of 1,135 microamps per micrometre on monolayer MoS2; these two values are, to the best of our knowledge, the lowest and highest yet recorded, respectively. We also demonstrate that excellent ohmic contacts can be formed on various monolayer semiconductors, including MoS2, WS2 and WSe2. Our reported contact resistances are a substantial improvement for two-dimensional semiconductors, and approach the quantum limit. This technology unveils the potential of high-performance monolayer transistors that are on par with state-of-the-art three-dimensional semiconductors, enabling further device downscaling and extending Moore’s law.

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Fig. 1: The concept of gap-state saturation at semimetal–semiconductor contact.
Fig. 2: Comparison of ohmic and Schottky contacts in monolayer MoS2 FETs.
Fig. 3: Crystal structure and mechanism of ohmic contact.
Fig. 4: Benchmark of Bi-contacted 2D semiconductor technology.

Data availability

All data needed to evaluate the conclusions herein are present in the Article.


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P.-C.S., J.B. and J.K. acknowledge financial support from the Center for Energy Efficient Electronics Science (NSF award no. 0939514), which provided funding for development of high-performance monolayer TMD transistors. P.-C.S., Y.L., J.-H.P., A.-Y.L., T.P. and J.K. acknowledge the US Army Research Office through the Institute for Soldier Nanotechnologies at MIT, under cooperative agreement no. W911NF-18-2-0048. C.S., J.-H.P., J.W. and J.K. acknowledge the support from the US Army Research Office (ARO) under grant no. W911NF-18-1-0431. C.S. is currently supported by the Kavli Energy NanoScience Institute/Heising–Simons Fellowship, Berkeley, California, USA. C.S. and A.Z. are supported by the Director, Office of Science, Office of Basic Energy Sciences, Materials Sciences and Engineering Division, of the US Department of Energy under contract no. DE-AC02-05-CH11231, within the sp2-Bonded Materials Program (KC2207), which provided for TEM characterizations. C.S. and A.Z. are further supported by the National Science Foundation under grant no. DMR-1807233, which provided funding for development of TEM image-processing methods. J.L. acknowledges support by the Office of Naval Research MURI through grant no. N00014-17-1-2661. Y.L. and J.B. acknowledge support by the Office of Naval Research MURI programme N00014-16-1-2921, and the NSF award RAISE TAQS under grant no. DMR-1839098. Y.L. and N.M. acknowledge support by the US Department of Energy (DOE), Office of Science, Basic Energy Sciences (BES) under award DE-SC0020042. A.-S.C. and C.-I.W. acknowledge support from the Ministry of Science and Technology of Taiwan (MOST 108-2622-8-002-016). J.W. and J.K. acknowledge support from the joint development project (JDP) from TSMC. V.T. and M.-H.C. are indebted to the support from the King Abdullah University of Science and Technology (KAUST) Office of Sponsored Research (OSR) under award no: OSR-2018-CARF/CCF-3079. H.-L.T. acknowledges partial support from the Ministry of Science and Technology of Taiwan (MOST-108-2917-I-564-036). We acknowledge H.-S.P. Wong for guidance. We thank Y. Guo, E. Shi and H. Wang for technical assistance with materials characterizations, and Y.-T. Shao for discussions on SAED pattern simulation.

Author information




J.K. and L.-J.L. supervised the project. P.-C.S. and J.K. proposed the project. P.-C.S., C.S., Y.L. and J.K. designed the experiments. P.-C.S. carried out the device fabrication. P.-C.S., H.-L.T. and Y.L. performed the electrical characterization supervised by T.P. C.S. carried out the TEM measurements and analysis and first-principles calculations supervised by A.Z. and J.L. P.-C.S., Y.L. and C.S. conducted the device modelling and data analysis. A.-S.C., C.-C.C. and G.P. carried out additional fabrication and characterization of the short-channel devices supervised by L.-J.L. The work of A.-S.C. is also co-supervised by C.-I.W. Y.L. and J.W. performed the SEM measurements. J.-H.P., P.-C.S., Z.C. and N.M. contributed to the growth, exfoliation and transfer of materials supervised by J.K. M.-H.C., A.-Y.L., M.M.T., and P.-C.S. carried out the materials characterizations. P.-C.S., C.S., Y.L. and J.K. wrote the manuscript. All authors discussed the results and provided constructive comments on the manuscript.

Corresponding authors

Correspondence to Pin-Chun Shen or Lain-Jong Li or Jing Kong.

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Competing interests

P.-C.S. and J.K. are co-inventors on a patent application (provisional filling number US 63/024,141) related to the research presented in this paper.

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Peer review information Nature thanks Hyeon-Jin Shin and the other, anonymous, reviewer(s) for their contribution to the peer review of this work. Peer reviewer reports are available.

Publisher’s note Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Extended data figures and tables

Extended Data Fig. 1 Temperature-dependent electrical characteristics.

ab, Typical IDSVDS curves at 150 K (a) and 77 K (b) for the Bi–MoS2 FET. The device exhibits linear output characteristics at all the temperatures measured. c, Schottky barrier height (ΦSB) extraction for the Bi–MoS2 FET, showing a negligible contact barrier. Inset, logarithmic plot of the IDSVDS curve at 77 K and n2D ≈ 4 × 1012 cm−2, demonstrating ohmic contact in the Bi–MoS2 FETs. de, Typical IDSVDS curves at room temperature (d) and 77 K (e) for the Ni–MoS2 FET. The nonlinear output characteristics at low temperatures suggest the existence of a Schottky barrier at the Ni–MoS2 junction. f, Schottky barrier (ΦSB) extracted by equation (3) as a function of the gate voltage for the Ni–MoS2 FET. ΦSB is around 100 meV at the flatband voltage (the elbow of the curve)2. g, Typical IDSVGS curves of the Ti–MoS2 FET. h, Typical IDSVDS curves at 77 K for the Ti–MoS2 FET. Similar to the Ni–MoS2 device, the Ti–MoS2 FET exhibits both drain–current suppression and obviously nonlinear output characteristics at low temperatures, owing to the presence of a Schottky barrier at the Ti–MoS2 interface. i, Extracted ΦSB for the Ti–MoS2 FET as a function of the gate voltage, which is around 150 meV at the flatband voltage.

Extended Data Fig. 2 Arrhenius plots and extraction of contact resistance.

ab, Arrhenius plots of Ni-contacted (a) and Bi-contacted (b) monolayer (1L) MoS2 FETs. The two transistors yield opposite slopes derived from equation (3), reflecting different metal–semiconductor junction configurations. The good agreement between the data extracted from the Ni–MoS2 FET and the thermionic emission model suggests that there is thermally activated electronic transport at an energy barrier, that is, a Schottky barrier at the Ni–MoS2 interface. By contrast, the deviation from the thermionic emission model and nearly saturated slopes at low temperatures observed in the Bi–MoS2 FET indicate the disappearance of an energy barrier for electron injection. The light blue curve represents the off state of the Bi–MoS2 FET biased at a negative gate voltage of −60 V. The device at this condition shows a negative slope in the Arrhenius plot and the effective barrier height is extracted to be ~130 meV. This barrier originates from the energy difference between the Fermi level of the degenerate MoS2 underneath Bi and the conduction band minimum of the depleted MoS2 channel. c, Transfer characteristics, IDSVGS, of Bi-contacted monolayer MoS2 FETs on 100-nm-thick SiNx with various channel lengths (LCH) at a VDS of 0.5 V for the TLM study. d, Plots of total device resistance RTOT (normalized by width) versus LCH for the Bi–MoS2 FETs at various carrier densities, from which the total contact resistance (2RC) can be extracted from the y-axis intercepts. Symbols are experimental data and lines are linear fits in a and d.

Extended Data Fig. 3 SAED patterns of the freestanding Au/Bi/monolayer–MoS2 and Au/Bi/amorphous carbon.

ae, Schematics of the Au/Bi layer deposited directly on the monolayer (1L) MoS2 (a) and amorphous carbon (a-carbon; e) in the TEM grid. bd, SAED patterns of Au/Bi/1L–MoS2 at three different locations. The [0001] zone axis of Bi is always observed in parallel to the electron beam throughout the whole sample. The diffraction spots of MoS2 at 3.6 nm−1 can be clearly identified. The in-plane rotations of MoS2 with respect to the Bi (0001) plane are 30° (b), 4° (to the nearest Bi diffraction spots; c), and 8° (d). For most of the areas, Bi demonstrates homogeneous orientation, as shown in b and d, but polycrystalline areas can also be found, as shown in c. The selected-area aperture is 1 μm. fh, The diffraction ring located at 3.0 nm−1 is identified to be from Bi2O3 polycrystal, as confirmed from the atomic structure of Bi2O3 viewing at zone axes [110] (g), and its simulated diffraction pattern (h), demonstrating the diffraction pattern at 3.0 nm−1.

Extended Data Fig. 4 DFT results for Sb–MoS2, Bi–MoS2 with sulfur vacancy and Bi–WS2.

a, PLDOS of MoS2 before (upper) and after (lower) contact with Sb. The valence band (VB) is shaded in light blue and conduction band (CB) in light red. The Fermi level (EF) is shifted from the valence band maximum inside the gap (before Bi contact) into the conduction band (after Bi contact). bc, LDOS of MoS2 with a sulfur vacancy (b) and WS2 (c) when in contact with Bi. The Fermi level is pinned at the sulfur vacancy defect state inside the bandgap. This implies that a high-quality TMD crystal with a low defect density is critical to form ohmic contact to Bi. The result of LDOS of WS2 in contact with Bi, predicting that ohmic contact can also be formed at the Bi–WS2 interface owing to gap-state saturation.

Extended Data Fig. 5 Characterization of transition metal dichalcogenide monolayers.

a, Raman characterization of MOCVD-grown monolayer MoS2 (blue) and mechanically exfoliated WS2 (green) and WSe2 (red) monolayers for device fabrication. b, Raman characterization of Ni–MoS2 and Au–MoS2 interfaces. Samples are prepared using the mechanically tape-assisted exfoliation. No substantial shifts in A1g are observed for Ni and Au contacts. The shift in E12g is prevalently observed in the metal–MoS2 system, probably originating from the strain induced at the metal–MoS2 boundary. c, Deconvolution of the XPS spectra of S 2p and Bi 4f for pristine monolayer MoS2 and Bi-contacted MoS2. The blueshifted core-level binding energies for the Bi-contacted MoS2 indicate the upward shift of its Fermi level induced by the Bi contact, which is in good agreement with the DFT calculation and the Raman spectroscopy analysis. Moreover, the absence of characteristic peaks for Bi2O3 suggest that the Bi contact is free of oxidation when in contact with MoS2, which is consistent with the TEM results (Fig. 3b and Extended Data Fig. 3).

Extended Data Fig. 6 Transfer characteristics of monolayer WS2 and WSe2 FETs with Bi contacts.

ab, Typical transfer characteristics of Bi–WS2 (a) and Bi–WSe2 (b) FETs on 100-nm SiNx at room temperature. Both transistors exhibit n-type conduction with a high ION/IOFF ratio of >107.

Extended Data Fig. 7 Monolayer MoS2 transistors with very high ION.

a, Transfer characteristics of a 35-nm LCH Bi–MoS2 FET. bc, Transfer and output characteristics of a 50-nm LCH Bi–MoS2 FET. d, Output characteristics of a 120-nm LCH Bi–MoS2 FET. The excellent current-delivery capacities represent, to our knowledge, new records for monolayer MoS2 at these device dimensions, outperform thicker TMD devices, and are comparable to three-dimensional semiconductor devices such as 90-nm node-strained Si and AlGaAs/InGaAs HEMT transistors with similar channel lengths39,40,46. Note that the required drain voltage for the ohmic Bi–monolayer MoS2 FET to achieve a high ION is relatively small compared to previously reported high-performance TMD transistors (that is, typically VDS > 2 V with a thicker channel thickness)18,22,30,31,32,33,34,42,43,44,45. Inset, optical microscopic image of the device. e, Semi-logarithmic plot of the transfer characteristic of a different Bi–MoS2 FET showing an excellent ION/IOFF ratio of 108. Insets, SEM image of a representative 150-nm LCH Bi-contacted monolayer MoS2 FET on 100-nm-thick SiNx and its channel region. f, Output characteristics of the same Bi–MoS2 transistor as in e. The drain current saturates at a VDS of ~1.5 V and scales linearly with the gate voltage, which suggests that the electrons travelling in the monolayer MoS2 channel reach its saturation velocity. The gate dielectrics of devices presented in this figure are 100-nm SiNx.

Extended Data Fig. 8 Effects of TMD quality on the output characteristics.

ab, Sample-quality-dependent contact performance for the case of monolayer MoS2. The room-temperature output characteristics of the Bi–MoS2 transistors fabricated with a CVD-grown defective MoS2 monolayer (a) and MOCVD-grown MoS2 monolayer (b). Inset to a, optical image of a typical low-quality MoS2 crystal with a non-clean surface and curved edges; scale bar, 5 μm. Inset to b, optical image of a typical high-quality MoS2 crystal with a clean surface; scale bar, 10 μm. cd, Output characteristics of Bi-contact transistors fabricated with fresh CVD-grown monolayer WS2 (c) and monolayer WSe2 (d) FETs, showing that the proposed gap-state-saturation-induced ohmic contact can also be formed on high-quality WS2 and WSe2 CVD samples. ef, Room-temperature output characteristics (e) and transfer curves (f) of the Bi–WSe2 transistors fabricated with an aged CVD-grown WSe2 monolayer (low quality). Scale bar, 10 μm. gh, Room-temperature output characteristics (g) and transfer curves (h) of the Bi–WSe2 transistors fabricated with a fresh CVD-grown WSe2 monolayer (medium quality). Scale bar, 10 μm. ij, Room-temperature output characteristics (i) and transfer curves (j) of the Bi–WSe2 transistors fabricated with a mechanically exfoliated WSe2 monolayer (high quality). Scale bar, 5 μm. The results show a clear evolution from p-type conduction to enhanced n-type conduction with the sample quality improvement. These variations could be attributed to the gap-state pinning effect induced by the chalcogen vacancies (Extended Data Fig. 4b). Insets to f, h and j are the optical images of a typical low-quality CVD WSe2 crystal with an obviously defective surface (f), a medium-quality CVD WSe2 with an irregular crystal shape (h), and a high-quality, freshly exfoliated WSe2 with a clean surface (j).

Extended Data Fig. 9 Performance projection of Bi–monolayer TMD technology.

a, Fraction of channel resistance (RCH, green line) and total contact resistance (2RC, blue line) with respect to the total device resistance (RTOT = RCH + 2RC) in Bi–MoS2 FETs as a function of the channel length (LCH) at room temperature based on the device and material parameters extracted from Fig. 2c. The dashed lines show the quantum limit, representing the minimum RC that can be achieved in a transistor. The quantum limit RC is πh/(4q2kF) ≈ 0.036(n2D)−0.5 kΩ μm, which is determined by the quantum resistance (h/2q2 ≈ 12.9 kΩ) and the number of conducting modes per channel width (kF/π), which is related to the 2D sheet carrier density (n2D, in units of 1013 cm–2)2. b, Projection of 2RC as a function of the contact length (LC) in monolayer TMD transistors based on the transmission line model with various metal contacts at room temperature. The vertical dashed line represents the current transfer length (LT) for each metal contact. The results are calculated based on the data extracted from previously reported TLM results13,47. As can be seen, RC increases as LC becomes comparable to LT, owing to the current-crowding effect (equation (4))18. Note that In, hexagonal boron nitride (hBN)/Co, Ni and high-vacuum Au contacts to monolayer MoS2 exhibit similar values of RC (~3–6 kΩ μm) and ρC (~10−6–10−5 Ω cm2)13,14,18,50. c, Required minimum VDS for Bi-contacted monolayer TMD transistors to work in the velocity saturation regime using our best RC of 123 Ω μm and a theoretical FC of 1.15 × 105 V cm−1. The VDD required by IRDS is also plotted. d, The required VDS to bias monolayer MoS2 transistors in the velocity-saturation regime for different contact technologies.

Extended Data Table 1 Key performance metrics of representative devices

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Shen, PC., Su, C., Lin, Y. et al. Ultralow contact resistance between semimetal and monolayer semiconductors. Nature 593, 211–217 (2021).

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