Thermal management is one of the main challenges for the future of electronics1,2,3,4,5. With the ever-increasing rate of data generation and communication, as well as the constant push to reduce the size and costs of industrial converter systems, the power density of electronics has risen6. Consequently, cooling, with its enormous energy and water consumption, has an increasingly large environmental impact7,8, and new technologies are needed to extract the heat in a more sustainable way—that is, requiring less water and energy9. Embedding liquid cooling directly inside the chip is a promising approach for more efficient thermal management5,10,11. However, even in state-of-the-art approaches, the electronics and cooling are treated separately, leaving the full energy-saving potential of embedded cooling untapped. Here we show that by co-designing microfluidics and electronics within the same semiconductor substrate we can produce a monolithically integrated manifold microchannel cooling structure with efficiency beyond what is currently available. Our results show that heat fluxes exceeding 1.7 kilowatts per square centimetre can be extracted using only 0.57 watts per square centimetre of pumping power. We observed an unprecedented coefficient of performance (exceeding 10,000) for single-phase water-cooling of heat fluxes exceeding 1 kilowatt per square centimetre, corresponding to a 50-fold increase compared to straight microchannels, as well as a very high average Nusselt number of 16. The proposed cooling technology should enable further miniaturization of electronics, potentially extending Moore’s law and greatly reducing the energy consumption in cooling of electronics. Furthermore, by removing the need for large external heat sinks, this approach should enable the realization of very compact power converters integrated on a single chip.
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All the data needed to evaluate the conclusions in the paper are present in the paper, in the Extended Data and in the Supplementary Information.
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We thank the staff at the Center of Micro and Nano Technology (CMi) for support and advice on the fabrication processes. We thank V. Navikas for his graphical assistance to the paper. This work was supported in part by the European Research Council (ERC Starting Grant) under the European Union’s H2020 program (ERC grant agreement number 679425), in part by the Swiss Office of Energy (grant number SI501568-01) and in part by the Swiss National Science Foundation (Assistant Professor Energy grant number PYAPP2_166901).
The authors declare no competing interests.
Peer review information Nature thanks Peter Moens, Tiwei Wei and the other, anonymous, reviewer(s) for their contribution to the peer review of this work.
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Extended data figures and tables
a, AlGaN/GaN epilayer on a silicon substrate. b, SiO2 hard-mask deposition. c, Hard mask patterning and opening. d, Epilayer etching until the substrate is reached. e, Anisotropic deep (to depth h) etching of the silicon substrate through the epilayer opening. f, Isotropic gas etching through the epilayer opening to widen the slits under the epilayer. An in situ optical etching tracking was put in place to control the width w of the channels. g, Hard-mask removal. h, Ohmic contact deposition and annealing, and seed layer deposition for electroplating and patterning the electroplating mask. i, Manifold channel etching from the back of the substrate. j, Cr/Cu seed layer deposition for electroplating. k, Lithography step to define electroplating openings. l, Electroplating to seal the epilayer openings. m, Photoresist removal. n, Wet etch to remove Cr/Cu seed layer. o, Finish device fabrication with optional dielectric deposition. p, Finish device fabrication with optional gate metal deposition.
a, Schematic overview of the measurement setup. An inlet reservoir of coolant is pressurized using a pressure controller, whereas the temperature is controlled using a thermostatic bath. Liquid flow through a flow meter into the test section, containing the chip (DUT). The temperature of the chip is monitored using an infrared (IR) camera, and coolant temperature is monitored using thermocouples (T) and transferred to the personal computer (PC) using a data acquisition box (DAQ). Pressure drop over the chip (dP) is measured at the inlet and outlet port of the chip. b, Picture of the experimental setup for characterizing the thermal performance. c, Close-up picture of the test section.
Extended Data Fig. 3 Example data reduction of thermal characterization experiments for the 10×-manifold chip.
a, Peak surface temperature rise above the inlet temperature, measured using infrared thermography at varying power dissipation. The slope of the linear fit through the data points gives the total thermal resistance (Rtotal). b, Water temperature rise, measured between the inlet and outlet of the chip. The slope of the linear fit through the data points gives the contribution of the total thermal resistance due to the temperature rise of the water (Rheat). c, Wall temperature rise. The slope through these data points gives the convective thermal resistance. d, Total, caloric, convective and conductive thermal resistance versus the inverse flow rate. e, Nusselt number and fin efficiency. f, Effective base-area averaged heat transfer coefficient (heff) and wall-area averaged heat transfer coefficient (hwall), taking the surface area of the microchannels as well as the fin efficiency into account.
a, Wall temperature for all devices. Each device shows a distinct slope in wall temperature rise versus power dissipation. b, Caloric thermal resistance for all evaluated flow rates, showing a clear (ρcpf)−1 relationship over all devices. c, Fin efficiency over a range flow rates. d, Nusselt number versus inverse flow rate. The dashed line indicates that Nu = 3.66 for fully developed internal flow.
Surface temperature rise dT, wall temperature rise, water temperature rise and thermal resistance R for: a, 100 µm-wide SPMC; b, 50 µm-wide SPMC straight microchannels; c, 25 µm-wide SPMC straight microchannels; and d, 4×- manifold.
Extended Data Fig. 6 Extensive benchmarking plot of micro-structured cooling approaches in the literature using water as a working fluid.
COP versus heat flux for a maximum surface temperature rise of 60 K. Solid markers indicate experimental results and open markers indicate numerical or analytical calculations. The results in this work are indicated by red stars. Dashed lines correspond to predictions based on a constant heat transfer. References 19,29,35,38,61,62,63,64,65,66,68,69,70,71 to all datasets used can be found in Extended Data Table 2, and all the data used are available in the Supplementary Table.
a, Current–voltage characteristics at hydrostatic pressure between 0 mbar and 1,590 mbar. b, Normalized change in electrical resistance versus pressure during a sweep in pressure up to 1,600 mbar and back. Each resistance value was extracted using a linear fit (R2 > 0.997) through a cyclic current–voltage measurement from 0 V to 0.5 V and back. Error bars indicate standard error of the fit over each set of 46 data points per condition.
a, Three PCBs that provide coolant delivery to the chip. b, Laser-cut adhesives used to bond the layers together. c, Converter after assembly, with electrical and fluidic connections. d, SEM image of the four-diode structure. The inset shows the polarity of each device and a close-up of the structure of the tri-anode Schottky barrier diode.
a, Input and output waveforms of 150 V/1.2 A peak-to-peak rectification at 100 kHz. b, Surface temperature rise versus power dissipation for varying flow-rates. c, Thermal resistance versus inverse flow rate of the full converter. Pressure drop and pumping power versus flow rate. d, Pressure drop and pumping power versus flow rate.
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van Erp, R., Soleimanzadeh, R., Nela, L. et al. Co-designing electronics with microfluidics for more sustainable cooling. Nature 585, 211–216 (2020). https://doi.org/10.1038/s41586-020-2666-1
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