Abstract
Classification is an important task at which both biological and artificial neural networks excel^{1,2}. In machine learning, nonlinear projection into a highdimensional feature space can make data linearly separable^{3,4}, simplifying the classification of complex features. Such nonlinear projections are computationally expensive in conventional computers. A promising approach is to exploit physical materials systems that perform this nonlinear projection intrinsically, because of their high computational density^{5}, inherent parallelism and energy efficiency^{6,7}. However, existing approaches either rely on the systems’ time dynamics, which requires sequential data processing and therefore hinders parallel computation^{5,6,8}, or employ large materials systems that are difficult to scale up^{7}. Here we use a parallel, nanoscale approach inspired by filters in the brain^{1} and artificial neural networks^{2} to perform nonlinear classification and feature extraction. We exploit the nonlinearity of hopping conduction^{9,10,11} through an electrically tunable network of boron dopant atoms in silicon, reconfiguring the network through artificial evolution to realize different computational functions. We first solve the canonical twoinput binary classification problem, realizing all Boolean logic gates^{12} up to room temperature, demonstrating nonlinear classification with the nanomaterial system. We then evolve our dopant network to realize feature filters^{2} that can perform fourinput binary classification on the Modified National Institute of Standards and Technology handwritten digit database. Implementation of our materialbased filters substantially improves the classification accuracy over that of a linear classifier directly applied to the original data^{13}. Our results establish a paradigm of siliconbased electronics for smallfootprint and energyefficient computation^{14}.
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Data availability
Data are available from the corresponding author upon reasonable request.
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Acknowledgements
We thank T. Bolhuis, M. H. Siekman and J. G. M. Sanderink for technical support. We thank C. P. Lawrence, B. J. Geurts, M. Nass, A. J. Annema, M. Dale and J. Dewhirst for discussions. We thank W. M. Elferink, R. Hori, J. Wildeboer and T. Dukker for help with measurements. We acknowledge financial support from the MESA+ Institute for Nanotechnology, and the Netherlands Organisation for Scientific Research (NWO): NWA Startimpuls grant number 68091114 and Natuurkunde Projectruimte grant number 40017607.
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Contributions
T.C. and W.G.v.d.W. designed the experiments. J.v.G., T.C., B.v.d.V. and S.V.A. fabricated the samples. T.C., J.v.G. and B.v.d.V. performed the measurements and simulations. T.C. analysed the data with input from all authors. H.B., H.C.R.E. and P.A.B. provided theoretical inputs. B.d.W. and H.C.R.E. contributed to measurement script. T.C. and W.G.v.d.W. wrote the manuscript and all the authors contributed to revisions. W.G.v.d.W. and F.A.Z. conceived the project. W.G.v.d.W. supervised the project. F.A.Z. cosupervised the sample fabrication.
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Peer review information Nature thanks Cyrus Hirjibehedin and the other, anonymous, reviewer(s) for their contribution to the peer review of this work.
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Extended data figures and tables
Extended Data Fig. 1 Fabrication steps and dopant concentration.
a, Thermal oxidation. b, Implantation window definition and growth of 35 nm oxide. c, Ion implantation. d, Photolithography and contact pads liftoff. e, Electronbeam lithography and nanoelectrodes liftoff. f, Reactive ion etching (RIE) of silicon. g, Height profile of the metal electrodes with respect to silicon before (black) and after (red) RIE etching. The etch depth of silicon is estimated by measuring the height change of the metal electrodes with respect to the silicon surface (indicated by the black line on the atomic force microscopy image in the inset, not to scale). Assuming that the metal is not etched by RIE, the etch depth of silicon is around 83 nm. h, Secondary ion mass spectroscopy of the boron dopant depth profile after implantation. On the basis of the etch depth, the boron concentration near the recessed silicon surface is of the order of 5 × 10^{17} cm^{−3}.
Extended Data Fig. 2 Nonlinear and tunable hopping conduction.
a, I–V characteristics at 4.2 K with different total etching time by RIE. As the total etching time increases, the nonlinearity becomes increasingly prominent, signalling the dominance of hopping conduction. b, Drain current versus control voltage for constant source–drain voltage V_{SD} = 1.2 V at 4.2 K. The source (S), drain (D) and control (C) electrodes are shown in the inset. The hysteresis for negative gate voltage is probably due to charging of the other five floating electrodes. c, Schematic plot of electrochemical potential µ versus position r, illustrating the tunability. The solid lines represent impurity states and the arrows represent hopping of carriers among states. See Supplementary Note 3 for detailed discussion. d, Fitting the temperaturedependent I–V curves with the model described by equation (2) in Supplementary Note 2. Black dashed lines represent the fitted curves. e, Conductance versus the reciprocal of the cube root of the source–drain voltage at different temperatures. The black circle groups data at temperatures below 140 K. See also Supplementary Note 2 for more discussion.
Extended Data Fig. 3 Evolved logic gates at 77 K.
a, Abundance plot of 14 nontrivial truth tables at 77 K. From a search with 10,000 sets of randomly generated control voltages, we found all 16 possible truth tables that can be realized for a twoinput–oneoutput configuration. b, Thermal stability of a NAND gate evolved at 77 K. Above 140 K, the output current clipped to compliance, and therefore the fitness was not extracted. The error bars represent the standard deviation of ten tests (see also Supplementary Note 4). c, Boolean logic gates evolved at 77 K in a device other than the one in Fig. 3c. Red circles are experimental output currents, and black lines represent the normalized desired output currents. The left six panels show the six major logic gates evolved with input voltage levels 0 V and 0.5 V. The right two panels show a NAND and a XNOR gate evolved with input voltage levels of −0.25 V and 0.25 V, showing the adaptability of the dopant network to different voltage levels (see also Supplementary Note 6).
Extended Data Fig. 4 Convergence of genetic algorithm in the configuration space.
a, Genetic algorithm convergence for the six major Boolean logic gates at 77 K. The best fitness of the 20 genomes is plotted against generation. b, Histograms of the control voltages that configure the dopant network to the XNOR gates with fitness F larger than 1.5. The first control voltage is prominently concentrated in a small range, but the others do not show a favourite range. The ranges of the five control voltages are (−600, 600), (−1,200, 1,200), (−1,200, 1,200), (−1,200, 1,200) and (−600, 600). c, Control voltages for the six major logic gates. d, Control voltages for the 16 filters, which are visualized in e. The filters ‘0110’ and ‘0010’ have the smallest separation. See Supplementary Notes 3 and 7 for more discussion.
Extended Data Fig. 5 Evolution of logic gates at two ends of hopping conduction.
a, Evolved logic gates at 4.2 K, at which the charge transport mechanism is still VRH (Methods). b, Evolved logic gates at 140 K. Red circles are experimental output currents and black lines represent the normalized desired output currents. See Supplementary Note 5 for a detailed discussion.
Extended Data Fig. 6 Measurement setup.
a, Schematics of the existing measurement setup. b, Equivalent circuit of the current measurement setup. I_{out} and R_{out} represent the output current and output resistance of the device. C_{L} is the parasitic capacitance of about 4 nF. R_{IV} and R_{F} are the input resistance and feedback resistance of the I/V converter, respectively. c, Schematic of an integrated highspeed current reading circuit. Here, R_{IV} is a resistor to convert current to voltage, C_{L} is the parasitic capacitance that can be reduced to below 1fF. R_{O} is a resistor that sets the amplification.
Extended Data Fig. 7 Bandwidth and energy efficiency scaling.
a, The scaling of allowed bandwidth with signal intensity in a log–log plot. The back, blue and red solid lines represent three different indicated cases. Larger required SNR (red) and smaller R_{IV} (blue) lower the bandwidth. The horizontal black dashed line represents the limit set by the hopping relaxation time at 77 K, which increases with temperature. b, The scaling of equivalent energy efficiency with signal intensity in a log–log plot. Larger SNR (red) and smaller R_{IV} (blue) lowers the energy efficiency. The horizontal black dashed line represents the limit at 77 K and fixed power consumption. If the dopant network power consumption is lowered, then the limit and all three scaling trends shift upwards. The three black dotted lines mark three representative computational technologies, the most energy efficient highperformance computer^{36}, the neural network (NN) accelerator^{29} and memristors^{37} (Supplementary Note 8). c, Current flow pattern of a NAND gate (NAND10 in d) with inputs 500 and 0 mV. There is a large parasitic current flowing from input 1 to control electrode 2 (black curved arrow). This parasitic current limits the energy efficiency. This can be solved by using electrostatically coupled electrodes (Supplementary Note 8). d, Measured power consumption of a NAND gate for the four input combinations. The standard deviations in the current are calculated from ten measurements. The differential resistances R_{diff} are measured around the voltages in the second column.
Extended Data Fig. 8 Backgateinduced nonlinearity and evolved logic gates at room temperature.
a, A positive voltage V_{Sub} with respect to the drain voltage is applied to the ntype substrate (Fig. 2b) to make the depletion region wider at the p–n junction, and to suppress the band conduction. b, Evolved gates at room temperature. Red circles are experimental outputs, and black lines represent the normalized desired outputs. The output current levels, and also the separation between these levels, are more than one order of magnitude larger than those of the logic gates evolved at 77 K, owing to the increased hopping conductance (Supplementary Note 3). The increased noise intensity is mainly due to the settings of the current measurement circuit (Methods).
Extended Data Fig. 9 Experimental response of the 16 filters.
Each of them is evolved to filter the feature given in blue. The output currents corresponding to features other than the desired one are not zero, but the output current of the targeted feature is clearly separated from the other currents. Error bars represent the standard deviation obtained from ten tests.
Extended Data Fig. 10 Enhancing robustness of the linear classifier against noise.
Besides optimizing the SNR, the linear classifier’s tolerance to noise can also be increased by taking noise into account during the training phase. The accuracy remains over 92% at 0.05 nA noise amplitude (see Supplementary Note 8 for a detailed discussion).
Supplementary information
Supplementary Information
Nine additional notes are included. The first three sections are related to the charge transport mechanism and the origin of the tunable nonlinearity. Aspects related to device characteristics such as stability and reproducibility are detailed from the fourth to the sixth sections. The last three sections consist of benchmarkingrelated topics including the speed, energy consumption, and classification accuracy.
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Chen, T., van Gelder, J., van de Ven, B. et al. Classification with a disordered dopantatom network in silicon. Nature 577, 341–345 (2020). https://doi.org/10.1038/s4158601919010
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