Integer factorization using stochastic magnetic tunnel junctions

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Abstract

Conventional computers operate deterministically using strings of zeros and ones called bits to represent information in binary code. Despite the evolution of conventional computers into sophisticated machines, there are many classes of problems that they cannot efficiently address, including inference, invertible logic, sampling and optimization, leading to considerable interest in alternative computing schemes. Quantum computing, which uses qubits to represent a superposition of 0 and 1, is expected to perform these tasks efficiently1,2,3. However, decoherence and the current requirement for cryogenic operation4, as well as the limited many-body interactions that can be implemented, pose considerable challenges. Probabilistic computing1,5,6,7 is another unconventional computation scheme that shares similar concepts with quantum computing but is not limited by the above challenges. The key role is played by a probabilistic bit (a p-bit)—a robust, classical entity fluctuating in time between 0 and 1, which interacts with other p-bits in the same system using principles inspired by neural networks8. Here we present a proof-of-concept experiment for probabilistic computing using spintronics technology, and demonstrate integer factorization, an illustrative example of the optimization class of problems addressed by adiabatic9 and gated2 quantum computing. Nanoscale magnetic tunnel junctions showing stochastic behaviour are developed by modifying market-ready magnetoresistive random-access memory technology10,11 and are used to implement three-terminal p-bits that operate at room temperature. The p-bits are electrically connected to form a functional asynchronous network, to which a modified adiabatic quantum computing algorithm that implements three- and four-body interactions is applied. Factorization of integers up to 945 is demonstrated with this rudimentary asynchronous probabilistic computer using eight correlated p-bits, and the results show good agreement with theoretical predictions, thus providing a potentially scalable hardware approach to the difficult problems of optimization and sampling.

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Fig. 1: Characteristics of stochastic magnetic tunnel junctions.
Fig. 2: Experimental demonstration of a p-bit.
Fig. 3: Experimental demonstration of integer factorization.

Data availability

The datasets generated and analysed during this study are available from the corresponding authors on reasonable request.

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Acknowledgements

We thank H. Sato, M. Bersweiler, T. Hirata, H. Iwanuma, K. Goto, C. Igarashi, I. Morita, R. Ono and M. Musya for technical support. We thank O. Hassan and S. Chowdhury for their help with the Methods sections comparing CMOS alternatives and quantum computing, respectively. A portion of this work was supported by ImPACT Program of CSTI, JSPS KAKENHI grant numbers 17H06093 and 19J12206, Cooperative Research Projects of RIEC, and ASCENT, one of six centres in JUMP, an SRC program sponsored by DARPA. W.A.B. acknowledges JST-OPERA.

Author information

S.F., K.Y.C., H.O. and S.D. planned the study. W.A.B. and S.F. prepared and characterized the MTJ devices. A.Z.P., K.Y.C. and S.D. developed the algorithm and experimental setup. A.Z.P. and K.Y.C. conducted factorization experiment and collected results. All authors contributed to the writing of the manuscript. All authors discussed the results.

Correspondence to Shunsuke Fukami or Kerem Y. Camsari.

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Competing interests

The authors declare no competing interests.

Additional information

Publisher’s note Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Peer review information Nature thanks Kyung-Jin Lee, Dmitri Nikonov and the other, anonymous, reviewer(s) for their contribution to the peer review of this work.

Extended data figures and tables

Extended Data Fig. 1 p-bit construction.

a, A diagram of the ideal response of a stochastic MTJ as used in this work and the parameters used to characterize the MTJ. b, The measured drain current IDS as a function of VIN of a 2N7000 NMOS transistor used in our p-bit demonstration.

Extended Data Fig. 2 Block diagram of an asynchronous p-circuit.

A microcontroller reads the outputs voltages VOUT of all p-bits and computes the synaptic weights, which are then converted to the analogue input voltages VIN for each p-bit, using a DAC that communicates with the microcontroller.

Extended Data Fig. 3 Experimentally observed time snapshots.

ac, Experimentally observed time snapshots of the four p-bits used to factorize 35 (a, b). These snapshots are combined to create x and y (c), which fluctuate between 7 × 5 and 5 × 7.

Extended Data Fig. 4 Calibrating the experimental system.

Calibrating a reference state using synaptic weights. a, The experimentally observed time-averaged output of six p-bits versus applied inputs (which are misaligned). b, The output is corrected using synaptic biases leading to the reference state shown. Each data point in a and b are taken as an average over a time window of 15 s with 2,000 or more sampling points.

Extended Data Fig. 5 Comparison between the MTJ- and CMOS-based energy per random bit and cell area.

a, An MTJ-based p-bit simulated with the stochastic LLG model (s-LLG, dotted box). b, A 32-bit LFSR. The look-up table (LUT) and the digital comparator of the CMOS p-bit are not included in the comparison. INV, inverter; DFF, D-type flip flop.

Extended Data Fig. 6 Computing with p-bits versus AQC.

a, A representation of how an array of six Ising spins in a qubit array can be replicated with an array of p-bits. b, A comparison of both approaches for factoring 161 = 23 × 7. For a system of six Ising spins, there are 64 states. At higher magnetic fields (ΓX = 0.5) both systems are ‘disordered’ and the correct peak is not pronounced. At lower magnetic field (ΓX = 0.1) the correct peaks emerge with a high probability. The states (yixi) have been converted to binary variables si from the bipolar variables mi by defining si = (mi + 1)/2 and the states [y2 y1 x4 x3 x2 x1] are expressed in decimal on the x axis.

Extended Data Fig. 7 Simulation versus experiment.

ad, We simulate the ideal experiment when all p-bits are perfectly aligned (a), using an idealized p-bit model which produces the results shown in c. Each data point is taken as an average over a time window of 15 s with 2,000 or more sampling points. The presence of device variations leads to a non-ideal system of misaligned p-bits (b), which is corrected using synaptic biases, allowing the experiment to approach the correct results (d). The time-averaged statistics in b are collected over a time window of 15 s with 2,000 or more sampling points.

Extended Data Fig. 8 Simulation of variations of τN.

The τ of six p-bits is varied from a minimum value of τΝ to a maximum value of 4τΝ. Variations between p-bits do not affect system operation providing that τinter = τN.

Extended Data Fig. 9 Simulations of variations of MTJ parameters.

ac, The variation of MTJ parameters results in the misalignment of the average responses of the p-bits (a), which results in a biased reference state (b). When such a system is used for factorizing 161 the observed results are incorrect (c). df, The shifts in the average responses are corrected using synaptic biases (d), which correct the reference state (e) and factorization results (f).

Extended Data Fig. 10 Invertible AND gate operation.

a, b, Time snapshot for the direct mode of operation when the inputs x2 and x1 have both been pinned to 1 (a); the statistics collected for 60 s (b). c, d, Time snapshot for the p-bits operating the AND gate in inverted mode when the output y1 is pinned to 0 (c); the statistics collected for 60 s (d). e, f, Time snapshot for the p-bits operating the AND gate in floating mode (e); the statistics collected for 60 s (f). All statistics shown are collected over a time window of 60 s with 2,000 or more sampling points.

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