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Integrating photonics with silicon nanoelectronics for the next generation of systems on a chip

A Publisher Correction to this article was published on 21 June 2018

This article has been updated

Abstract

Electronic and photonic technologies have transformed our lives—from computing and mobile devices, to information technology and the internet. Our future demands in these fields require innovation in each technology separately, but also depend on our ability to harness their complementary physics through integrated solutions1,2. This goal is hindered by the fact that most silicon nanotechnologies—which enable our processors, computer memory, communications chips and image sensors—rely on bulk silicon substrates, a cost-effective solution with an abundant supply chain, but with substantial limitations for the integration of photonic functions. Here we introduce photonics into bulk silicon complementary metal–oxide–semiconductor (CMOS) chips using a layer of polycrystalline silicon deposited on silicon oxide (glass) islands fabricated alongside transistors. We use this single deposited layer to realize optical waveguides and resonators, high-speed optical modulators and sensitive avalanche photodetectors. We integrated this photonic platform with a 65-nanometre-transistor bulk CMOS process technology inside a 300-millimetre-diameter-wafer microelectronics foundry. We then implemented integrated high-speed optical transceivers in this platform that operate at ten gigabits per second, composed of millions of transistors, and arrayed on a single optical bus for wavelength division multiplexing, to address the demand for high-bandwidth optical interconnects in data centres and high-performance computing3,4. By decoupling the formation of photonic devices from that of transistors, this integration approach can achieve many of the goals of multi-chip solutions5, but with the performance, complexity and scalability of ‘systems on a chip’1,6,7,8. As transistors smaller than ten nanometres across become commercially available9, and as new nanotechnologies emerge10,11, this approach could provide a way to integrate photonics with state-of-the-art nanoelectronics.

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Fig. 1: Photonic integration with nanoscale transistors.
Fig. 2: Monolithic electronic–photonic platform in 65-nm bulk CMOS.
Fig. 3: Photonics platform performance.
Fig. 4: Electro-optical testing of WDM transceiver chips.

Change history

  • 21 June 2018

    In this Letter, owing to an error during the production process, the author affiliations were listed incorrectly. Affiliation number 5 (Colleges of Nanoscale Science and Engineering, State University of New York (SUNY)) was repeated, and affiliation numbers 6–8 were incorrect. In addition, the phrase “two oxide thickness variants” should have been “two gate oxide thickness variants”. These errors have all been corrected online.

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Acknowledgements

We thank E. Timurdogan and M. Byrd for help with high-speed photonic measurements, and A. Nikiforov of the Boston University Photonics Center for assistance with sample imaging and analysis. This work was supported by DARPA POEM award HR0011-11-C-0100 and contract HR00111190009, led by J. Shah. We also acknowledge support from the Microsystems Technology Laboratories (MTL) at MIT, the Berkeley Wireless Research Center, the Center for Nanoscale Sciences and Engineering and the Packard Foundation. The views expressed are those of the authors and do not reflect the official policy or position of the DoD or the US Government.

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Authors and Affiliations

Authors

Contributions

A.H.A., S.M. and F.P. all contributed equally to this work. A.H.A. designed and tested avalanche photodetectors, tested photonic devices during process development and designed WDM receiver rows. S.M. designed the mixed-signal electronics for transceiver chiplets, tested optical transceivers and electronics, and performed top-level assembly of electronics and photonics on the chip. F.P. designed and tested optical modulators, designed WDM transmitter rows, and performed top-level assembly of photonics in the transceiver chips. A.H.A., S.M. and F.P. all contributed to the chip verification. H.G. tested optical modulators and loss test structures on full flow wafers. J.N. designed and tested the original version of grating couplers. L.A. developed the CAD infrastructure for the photonics layout and chip verification, and contributed to the layout of waveguide test structures. M.T.W. designed and contributed to the layout of optical passive devices. C.S. contributed to the design of WDM optical transceivers and thermal tuning circuits. S.A.K. ran process experiments for propagation loss improvement, performed CMOS and photonics fabrication compatibility optimization, fabricated full flow wafers, and performed inline electrical and optical testing. H.M. contributed to the design of avalanche photodetectors. K.A.K. tested grating couplers on full-flow wafers. I.W. performed device metrology and post processing of optical waveguide and resonator loss data. B.Z. performed grating coupler simulations and contributed to the new grating coupler designs. A.K. analysed device metrology and measurement data for studying and optimizing photonic performance. C.V.B. developed the 65-nm CMOS-compatible photonics design kit, designed methodology for the in-line electrical tests, metrology and optical photonics testing, worked with the mask house with building the photolithography masks and managed the overall process development and wafer fabrication. M.A.P., V.M.S. and R.J.R. supervised the project.

Corresponding author

Correspondence to Amir H. Atabaki.

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Competing interests

C.S., M.T.W., R.J.R., M.A.P. and V.M.S. are involved in developing silicon photonic technologies at Ayar Labs.

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Extended data figures and tables

Extended Data Fig. 1 Passive photonic performance at 1,300 nm and 1,550 nm.

a, Waveguide propagation loss at 1,300 nm. Waveguide loss drops with wavelength because of a combination of lower absorption and scattering by polysilicon. b, Q-factor of a 15-µm-diameter microring resonator. c, Waveguide propagation loss at 1,550 nm. d, One resonance of a 17-µm-diameter microring near 1,540 nm with a Q-factor of 38,000.

Extended Data Fig. 2 Polysilicon avalanche photodetector.

a, Current–voltage curve of the microring photodiode under dark and illumination for an input optical power of 20 µW. Dynamic range is about 60 dB and about 10 dB at 0 V and 16 V, respectively. b, One microring photodetector resonance (top) and the corresponding photo-current (bottom) as the wavelength is swept across the resonance. The loaded Q-factor (Qloaded) of the microring is about 10,000. The fit is obtained through least-squares optimization of a model that includes a Lorentzian resonance for the microring and accounts for the reflections from the end facets of the chip to model the Fabry–Perot resonances observed in the transmission curve. c, Noise equivalent power (NEP, blue curve) of the photodiode estimated from the dark-current shot noise, which dominates the detector noise. Avalanche gain is 13 at 16 V bias, with an noise equivalent power of 0.27 pW Hz−1/2. The simulated signal-to-noise ratio (SNR) (red curve) at the output of the optical receiver, assuming an optical signal of 1 µW, and a receiver circuit input-referred noise spectral density of 1 pA Hz−1/2. d, The responsivity of the photodetector versus input optical power, showing minimal power dependency. The error bar is estimated based on a ±5% error in estimating the optical power in the waveguide before coupling into the detector. This error comes from variations in fibre to chip coupling efficiency owing to fibre-grating coupler misalignment. e, f, Eye diagrams at 12.5 Gb s−1 at 0 V and 14.5 V reverse bias.

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Atabaki, A.H., Moazeni, S., Pavanello, F. et al. Integrating photonics with silicon nanoelectronics for the next generation of systems on a chip. Nature 556, 349–354 (2018). https://doi.org/10.1038/s41586-018-0028-z

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