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Electronics

Ferroelectric memory for back-end-of-line 3D integration

Nature Reviews Materials volume 8, page 421 (2023)Cite this article

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The memory wall is a common issue in computing referring to the fact that processors have limited capacity and bandwidth for memory transfer. The monolithic three-dimensional integration of non-volatile memories (NVMs) — which retain data without requiring a continuous power supply — and ‘conventional’ Si complementary metal–oxide–semiconductor (CMOS) logic could prove indispensable in tackling the memory wall. Naturally, this approach requires energy-efficient and scalable NVMs based, as one option, on ferroelectric field-effect transistor (FE-FET) arrays. However, the compatibility of FE-FETs with CMOS back-end-of-line (BEOL) processes and the scalability of these devices present multiple challenges. Now, writing in Nature Nanotechnology, Roy H. Olsson III, Deep Jariwala and colleagues propose a CMOS BEOL-compatible NVM technology based on 2D–3D heterogeneous FE-FETs.

To prepare the devices, the team drew on their extensive fabrication experience to deposit AlScN films of various thicknesses. The films could be deposited on four-inch wafers, illustrating that the method is easily applicable at larger scales. The deposition was then followed by the transfer of a large-area monolayer MoS2. Importantly, the processing was done at 350 °C, well within the BEOL thermal budget, which is a process that needs to be carried out at temperatures below 400 °C.

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  1. Associate Editor, Nature Reviews Electrical Engineering http://www.nature.com/natrevmats/

    Lishu Wu

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  1. Lishu Wu
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Correspondence to Lishu Wu.

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Wu, L. Ferroelectric memory for back-end-of-line 3D integration. Nat Rev Mater 8, 421 (2023). https://doi.org/10.1038/s41578-023-00578-6

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