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Constant-overhead fault-tolerant quantum computation with reconfigurable atom arrays


Quantum low-density parity-check (qLDPC) codes can achieve high encoding rates and good code distance scaling, potentially enabling low-overhead fault-tolerant quantum computing. However, implementing qLDPC codes involves nonlocal operations that require long-range connectivity between qubits. This makes their physical realization challenging in comparison to geometrically local codes, such as the surface code. Here we propose a hardware-efficient scheme for fault-tolerant quantum computation with high-rate qLDPC codes that is compatible with the recently demonstrated capabilities of reconfigurable atom arrays. Our approach utilizes the product structure inherent in many qLDPC codes to implement the nonlocal syndrome extraction circuit through atom rearrangement, resulting in an effectively constant overhead. We prove the fault tolerance of these protocols, and our simulations show that the qLDPC-based architecture starts to outperform the surface code with as few as several hundred physical qubits. We further find that quantum algorithms involving thousands of logical qubits can be performed using less than 105 physical qubits. Our work suggests that low-overhead quantum computing with qLDPC codes is within reach using current experimental technologies.

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Fig. 1: Architecture of a qLDPC-based fault-tolerant quantum computer using reconfigurable atom arrays.
Fig. 2: Efficient implementation of quantum LDPC codes with atom arrays.
Fig. 3: qLDPC memory performance.
Fig. 4: Fault-tolerant teleportation from surface to qLDPC code.

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Data availability

The data collected and analysed in this article are available at (ref. 65). Source data are provided with this paper.

Code availability

All codes used to generate the figures are available upon request.


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We acknowledge helpful discussions with D. Bandyopadhyay, N. Breuckmann, M. Cain, L. Cohen, C. Duckering, S. Ebadi, S. Evered, X. Gao, S. Geim, M. Kalinowski, S. Li, J. Liu, T. Manovitz, B. Matuz, N. Maskara, Q. Nguyen, H. P. Nautrup, D. Orsucci, N. Rengaswamy, M. Vasmer, P. Yu and H. Zheng, among others. We particularly thank A. Krishna for detailed feedback on our results and paper. We are grateful for the support from the University of Chicago Research Computing Center for assistance with numerical simulations. This work was supported by the Army Research Office (ARO; Grant No. W911NF-23-1-0077 to Q.X. and L.J.), ARO Multidisciplinary University Research Initiatives (MURI; Grant No. W911NF-21-1-0325 to Q.X. and L.J. and Grant No. W911NF-20-1-0082 to J.P.B.A., D.B., M.D.L. and H.Z.), Air Force Office of Scientific Research MURI (Grant Nos. FA9550-19-1-0399 and FA9550-21-1-0209 to Q.X. and L.J. and Grant No. FA9550-19-1-0360 to C.A.P.), the National Science Foundation (NSF; Grant Nos. OMA-1936118, ERC-1941583 and OMA-2137642 to Q.X. and L.J. and Grant Nos. CCF-2313084, CIF-1855879, CCF-2100013 and CIF-2106189 to N.R. and B.V.), NTT Research (L.J.), the Packard Foundation (Grant No. 2020-71479 to L.J.), the Quantum Systems Accelerator Center of the US Department of Energy (Grant Nos. 7568717 and DE-SC0021013 to J.P.B.A., D.B., M.D.L. and H.Z.), the Center for Ultracold Atoms (Grant No. NSF PHY-1734011 to J.P.B.A., D.B., M.D.L. and H.Z.), the NSF Institute for Quantum Information and Matter (C.A.P.), the Optimization with Noisy Intermediate-Scale Quantum Devices programme of the Defense Advanced Research Projects Agency (Grant No. W911NF2010021 to D.B., J.W., M.D.L. and H.Z.), the NSF Graduate Research Fellowship Program (Grant No. DGE1745303 to D.B.), the Fannie and John Hertz Foundation (D.B.), and the Ramsay Centre for Western Civilisation (J.P.B.A.).

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Authors and Affiliations



M.D.L. and L.J. conceived the project. Q.X., J.P.B.A. and C.A.P. performed the numerical simulations. Q.X., J.P.B.A., C.A.P. and H.Z. proved the fault tolerance of the schemes. H.Z. identified the correspondence between product codes and product optical tools, H.Z. and Q.X. devised efficient implementations of various codes, and D.B. verified the experimental feasibility of the proposal. J.W. and H.Z. devised the 1D log-depth rearrangement algorithm. N.R. constructed the LP codes used in the simulations. All authors contributed to the design of the methodology and data analysis. All authors contributed to the writing of the paper. All work was supervised by B.V., M.D.L., L.J. and H.Z.

Corresponding authors

Correspondence to Liang Jiang or Hengyun Zhou.

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M.D.L. is a co-founder and shareholder of QuEra Computing. J.W and H.Z. are employees of QuEra Computing. The other authors declare no competing interests.

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Extended data

Extended Data Fig. 1 Product structure of HGP codes and LP codes.

(a) The HGP code is constructed from two classical LDPC codes. The classical codes are illustrated on the left and top, where circles indicate classical bits and squares indicate classical checks. A data qubit is placed at each intersection of two classical bits (filled orange circles) and of two classical checks (filled blue circles). Z stabilizer generators are placed at the intersection of horizontal bits and vertical checks, while X stabilizer generators are placed at the intersection of horizontal checks and vertical bits. Each stabilizer is connected to data qubits along the same row or column, with the same connectivity as the classical codes, as illustrated for the top left Z stabilizer. We have omitted other connections for ease of visualization. (b) The LP code is constructed by taking a lift over the hypergraph product of two classical protographs. The protographs and their hypergraph product are indicated by the dashed nodes and the lift is illustrated by the multiple inner nodes within each dashed node. The inner connectivity between two dashed nodes is given by the circulant-matrix representation of the ring elements in Eq. (4). When flattening the inner nodes vertically (horizontally), the vertical (horizontal) connectivity between the qubits and the checks for each column (row) is the same as the left (top) lifted classical code.

Extended Data Fig. 2 Efficient non-intersecting rearrangement in log-depth.

By using a divide and conquer algorithm, we can perform an arbitrary 1D rearrangement in depth logarithmic in the number of qubits. Repeating this across the array yields an efficient implementation of the desired rearrangements, without requiring intersecting atom trajectories that may lead to additional loss and decoherence. Here, we illustrate the full set of movements required in a small example. Similar to the earlier figures, blue squares indicate classical checks and orange circles indicate classical bits. When a blue square and orange circle are moved to be neighboring at the end of the rearrangement, they execute an entangling gate. The top panel indicates the desired change of configuration, where the ordering of neighboring atoms in the top row needs to be modified to that in the bottom row via parallel rearrangement, as illustrated by the crossing gray lines. The bottom figure illustrates how we decompose the arbitrary rearrangement into a non-crossing rearrangement, where the gray lines no longer intersect.

Extended Data Fig. 3 Illustration of ordering of operations in pipelined syndrome extraction.

(a) Successive steps of entangling gates for the pipelined product coloration circuit described in Alg. 3, with d = 3 rounds of syndrome extraction. Numbers at the corners of the X and Z ancilla qubits denote the round of syndrome extraction they correspond to. (b) Illustration of a local circuit that data qubits and ancilla qubits see, with dashed lines indicating different circuit moments. As the X stabilizer interacts with both qubits before the Z stabilizer, the syndrome extraction order is valid. Similar analysis can be performed for the commutation relations with the next round of ancilla qubits.

Extended Data Fig. 4 Achievable logical failure rates of the HGP codes with different idling error strengths.

We characterize the idling error strengths as the relative ratio between the idling error rate pi(n) at n = 4 and the gate error rate pg. This idling error strength can potentially be reduced by, for example, increasing the coherence time and accelerating the atom shuttling.

Supplementary information

Supplementary Information

Supplementary Discussion and Figs. 1–10.

Supplementary Video 1

Video of one syndrome extraction cycle for the hypergraph product LDPC code. Black dots indicate atoms (qubits), green dots indicate static spatial light modulators traps, dashed lines indicate AODs used for atom moving and red flashes indicate parallel two-qubit gates.

Source data

Source Data for Fig. 1

Data files and Python notebook for plotting.

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Xu, Q., Bonilla Ataides, J.P., Pattison, C.A. et al. Constant-overhead fault-tolerant quantum computation with reconfigurable atom arrays. Nat. Phys. (2024).

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