Abstract
Researchers have been developing 2D materials (2DM) for electronics, which are widely considered a possible replacement for silicon in future technology. Two-dimensional transition metal dichalcogenides are the most promising among the different materials due to their electronic performance and relatively advanced development. Although field-effect transistors (FETs) based on 2D transition metal dichalcogenides have been found to outperform Si in ultrascaled devices, the comparison of 2DM-based and Si-based technologies at the circuit level is still missing. Here we compare 2DM- and Si FET-based static random-access memory (SRAM) circuits across various technology nodes from 16 nm to 1 nm and reveal that the 2DM-based SRAM exhibits superior performance in terms of stability, operating speed and energy efficiency when compared with Si SRAM. This study utilized technology computer-aided design to conduct device and circuit simulations, employing calibrated MoS2 nFETs and WSe2 pFETs. It incorporated layout design rules across various technology nodes to comprehensively analyse their SRAM functionality. The results show that, compared with three-dimensional structure Si transistors at 1 nm node, the planar 2DMFETs exhibited lower capacitance, leading to reduced cell read access time (−16%), reduced time to write (−72%) and lowered dynamic power (−60%). The study highlights the provisional benefits of using planar 2DM transistors to mitigate the performance degradation caused by reduced metal pitch and increased wire resistance in advanced nodes, potentially opening up exciting possibilities for high-performance and low-power circuit applications.
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Data availability
The data supporting the plots in this paper and other findings from this study are available from the corresponding authors upon reasonable request.
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Acknowledgements
This work was supported by the National Science and Technology Council (NSTC) in Taiwan under grants NSTC 112-2223-E-002-011-MY3, 112-2218-E-002-028, 111-2222-E-002-015, 111-2622-8-002-001 and 111-2636-E-002-023. L.-J.L. thanks the support from the Jockey Club Hong Kong to the JC STEM lab of 3DIC, the Research Grant of Council of Hong Kong (CRS_PolyU502/22) and National Key R&D Project of China (2022YFB4400100). J.-K.H. appreciates the support from the City University of Hong Kong.
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V.P.-H.H. and L.-J.L. conceived the idea of this project. Y.-C.L. conducted the simulations and analyses, while J.-K.H. contributed expertise on material parameters for simulations. K.-Y.C. offered valuable insights from end-user perspectives. Y.-C.L. and V.P.-H.H. conducted data analysis and jointly drafted the paper with input from all authors. All authors discussed the results and commented on the paper.
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Nature Nanotechnology thanks Tian-Ling Ren, Tom Schram and Han Wang for their contribution to the peer review of this work.
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Extended data
Extended Data Fig. 1 The evolution of device structures.
Schematic diagrams depicting the device structures of single-gate planar MOSFETs, FinFETs, and nanosheet (NS) gate-all-around (GAA) FETs.
Extended Data Fig. 2 8T SRAM cell and layouts.
a, Schematic of the 8T SRAM cell, featuring two pull-up transistors (M3 and M6), two pull-down transistors (M1 and M4), and two pass-gate transistors (M2 and M5). WBLB and WBL denote the write bitlines, and WWL represents the write wordline. RBL stands for the read bitline, and RWL is the read wordline. QB and Q denote the data storage nodes for the 8T SRAM. b, c, 8T SRAM layouts with Si NSFETs and 2DMFETs at the 1 nm node. d, e, 8T SRAM layouts with Si FinFETs and 2DMFETs at the 7 nm node. Both 2DM and Si SRAM cells maintain the same cell area at each node. The wire widths of WL and BL are adjusted at each technology node to minimize wire resistance. Buried power rail (BPR) is implemented at the 1 nm node.
Extended Data Fig. 3 Speed comparison between 2D material-based and Si 8T SRAM cells.
a, b, Comparison of read access time and time to write between 2DM-based and Si-based 8T SRAM cells. The right-hand side Y-axis indicates the improvement of 2DM 8T SRAM over Si 8T SRAM at different technology nodes.
Extended Data Fig. 5 Logic device parameters and design rules.
The parameters include metal pitch (Mx/M0/MD/M1), gate pitch, gate length (Lg), equivalent oxide thickness (EOT), and supply voltage (VDD) specified in IRDS27. CD stands for critical dimension. FinFET structure is used for Si-channel MOSFETs from 16 nm to 10 nm nodes. Two stacked nanosheets (NS) channels and a buried power rail (BPR) are used for Si-channel MOSFET at 1 nm node28. The vertical space between two stacked NS channels is 10 nm.
Extended Data Fig. 6 SRAM organization and interconnect model.
a, SRAM array with the select cell highlighted in red. The select cell signifies the worst-case scenario regarding WL and BL RC loading. b, The π3 model is used to consider the interconnect29.
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Supplementary Information
Supplementary Figs. 1–5 and discussion.
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Lu, YC., Huang, JK., Chao, KY. et al. Projected performance of Si- and 2D-material-based SRAM circuits ranging from 16 nm to 1 nm technology nodes. Nat. Nanotechnol. 19, 1066–1072 (2024). https://doi.org/10.1038/s41565-024-01693-3
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DOI: https://doi.org/10.1038/s41565-024-01693-3
