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An in-memory computing architecture based on a duplex two-dimensional material structure for in situ machine learning

Nature Nanotechnology volume 18, pages 493–500 (2023)Cite this article

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Abstract

The growing computational demand in artificial intelligence calls for hardware solutions that are capable of in situ machine learning, where both training and inference are performed by edge computation. This not only requires extremely energy-efficient architecture (such as in-memory computing) but also memory hardware with tunable properties to simultaneously meet the demand for training and inference. Here we report a duplex device structure based on a ferroelectric field-effect transistor and an atomically thin MoS2 channel, and realize a universal in-memory computing architecture for in situ learning. By exploiting the tunability of the ferroelectric energy landscape, the duplex building block demonstrates an overall excellent performance in endurance (>1013), retention (>10 years), speed (4.8 ns) and energy consumption (22.7 fJ bit–1 μm–2). We implemented a hardware neural network using arrays of two-transistors-one-duplex ferroelectric field-effect transistor cells and achieved 99.86% accuracy in a nonlinear localization task with in situ trained weights. Simulations show that the proposed device architecture could achieve the same level of performance as a graphics processing unit under notably improved energy efficiency. Our device core can be combined with silicon circuitry through three-dimensional heterogeneous integration to give a hardware solution towards general edge intelligence.

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Fig. 1: In situ machine learning with a TIIO cell.
Fig. 2: Duplex FeFET device performance.
Fig. 3: In situ machine learning with TIIO ANN.
Fig. 4: Simulation of large-scale TIIO ANN.

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Data availability

Source data are provided with this paper.

Code availability

The codes used to build interfaces 0–3 (Fig. 3) and used for the simulations (Extended Data Fig. 8) are available from the corresponding authors upon reasonable request.

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Acknowledgements

This work is supported by the National Key R&D Program of China (grant no. 2022YFB4400100 (X.W.), 2021YFA0715600 (H.Q.) and 2021YFA1202903 (W.L.)); the National Natural Science Foundation of China (grant no. T2221003 (X.W.), 61927808 (X.W.), 61734003 (X.W.), 61851401 (X.W.), 91964202 (Z.Y.), 62204124 (Z.Y.) and 51861145202 (X.W.)); the Leading-Edge Technology Program of Jiangsu Natural Science Foundation (grant no. BK20202005 (X.W.)); the Strategic Priority Research Program of the Chinese Academy of Sciences (grant no. XDB30000000 (X.W.)); the Research Grant Council of Hong Kong (no. 15205619 (Y.C.)); Key Laboratory of Advanced Photonic and Electronic Materials; Collaborative Innovation Center of Solid-State Lighting and Energy-Saving Electronics; and the Fundamental Research Funds for the Central Universities, China. In addition, we thank the NJU Micro-Fabrication and Integration Center for support during device fabrication and measurement, and thank the Beijing Advanced Innovation Center for Integrated Circuits for support on device modelling and simulations.

Author information

Author notes

  1. These authors contributed equally: Hongkai Ning, Zhihao Yu, Qingtian Zhang, Hengdi Wen, Bin Gao.

Authors and Affiliations

  1. National Laboratory of Solid State Microstructures, School of Electronic Science and Engineering and Collaborative Innovation Center of Advanced Microstructures, Nanjing University, Nanjing, China

    Hongkai Ning, Zhihao Yu, Hengdi Wen, Yun Mao, Lei Liu, Wenfeng Wang, Taotao Li, Yating Li, Wanqing Meng, Weisheng Li, Yun Li, Hao Qiu, Yi Shi & Xinran Wang

  2. School of Integrated Circuit Science and Engineering, Nanjing University of Posts and Telecommunications, Nanjing, China

    Zhihao Yu

  3. School of Integrated Circuits, Tsinghua University, Beijing, China

    Qingtian Zhang, Bin Gao, Yuankun Li, Ying Zhou & Huaqiang Wu

  4. Department of Applied Physics, The Hong Kong Polytechnic University, Hong Kong, China

    Yue Zhou, Jiewei Chen & Yang Chai

  5. School of Integrated Circuits, Nanjing University, Suzhou, China

    Xinran Wang

  6. Suzhou Laboratory, Suzhou, China

    Xinran Wang

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  1. Hongkai Ning
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Contributions

Z.Y. and X.W. conceived and supervised the project. H.N. fabricated the device and TIIO array with assistance from Z.Y., H. Wen., W.M., W.L., Yating Li and Yuankun Li. H.N. performed the electrical measurements with assistance from Z.Y. and H. Wen. Y.M. and H.Q. performed the projections and simulations of the 22-nm-node FeFET. L.L., W.W. and T.L. performed the MoS2 growth. Q.Z., Yuankun Li, Ying Zhou, Yue Zhou and J.C. contributed to the simulations of monocular depth estimation, with guidance from B.G., Y.C. and H. Wu. H.N., Z.Y. and X.W. co-wrote the manuscript with input from the other authors. All the authors contributed to discussions.

Corresponding authors

Correspondence to Zhihao Yu, Bin Gao, Huaqiang Wu or Xinran Wang.

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Nature Nanotechnology thanks Suraj Cheema and Rehan Kapadia for their contribution to the peer review of this work.

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Extended data

Extended Data Fig. 1

Three operational modes in TIIO cell by tuning the CFE/CDE ratio.

Extended Data Fig. 2 The AFE/ADE ratio dependence of performance for different channel lengths.

a, The dependence of memory window, endurance and retention on AFE/ADE for presented device with Lch=3μm in Fig. 2. b-d, Optical images (b), SEM images (c), and transfer characteristics (d) of the scaled device with channel length of 85nm. e, The extrapolated 10-year data retention at 85oC of I-type FeFET (AFE/ADE = 0.053) with three scaled channel lengths,480nm, 180nm, and 85nm, shows over 5 decades of on/off ratio @10-year. The off currents kept under the measure precision and did not show any potential of rise, thus we saw them as constant (~2pA) approximately. f, The endurance of T-type FeFET (AFE/ADE = 0.67) with three scaled channel lengths.

Source data

Extended Data Fig. 3 Endurance and high temperature retention characteristics of FeFET.

a, Schematic of measurement set-up for endurance. b-e, Endurance performance of FeFET with different AFE/ADE. The program and erase voltages are ±8 V (2.86 MV/cm), respectively, with 20 ns period. f. The extrapolated 10-year data retention of I-type FeFET (AFE/ADE = 0.053) at 85oC and 125oC, shows over 6 decades of on/off ratio @10-year. The off currents kept under the measure precision and did not show any potential of rise, thus we saw them as constant approximately. g, 128-level potentiation/depression curves for T-type device (AFE/ADE = 0.43) after 0 (pristine), 5E7, and 1E8 cycles, showing great uniformity. The α(P) and α(D) stand for the fitted nonlinearity factors for potentiation and depression, respectively. h, 16-level (chosen from 128 states) data retention of an I-type device (AFE/ADE = 0.053) after 1E5 endurance cycles under 85oC accelerated test.

Source data

Extended Data Fig. 4 Ultra-fast switching of the FeFETs.

a, Schematics of the T-type duplex FeFET’s test. b, Schematics of the I-type duplex FeFET’s test. c, The waveform of fastest output from PXI-5433 pulse generator, measured by oscilloscope. The amplitude is 10 V, and the pulse width is 4.8 ns. We applied a positive pulse and a negative pulse to the gate of FeFET, with pulse widths from 10 us to the fastest 4.8 ns. The waveforms of T-type FeFET are plotted in d and that of I-type are plotted in e. For the shortest 4.8 ns pulse, there are still 2~3 decades of on/off ratio. The on/off ratio increases to 7~8 decades when pulse width reaches 10 μs. f-j, The The Read-after-write characterization. f, Waveforms of gate voltage for read-after-write test. The amplitude of programming pulses is 9V. g-h, The pulsed memory window for T-type FeFET (AFE/ADE = 0.67, AFE = 64 μm2). g, Pulsed transfer characteristics of T-type device measured in a fast sweep time of 20 μs, with a wide range of read-after-write delay time from 1s to 20 ns (the minimum time resolution of instrument without read current). h, The memory window as a function of read-after-write delay time, extracted from (g). i-j, The pulsed memory window for I-type FeFET (AFE/ADE = 0.053, AFE = 8 μm2). i, Pulsed transfer characteristics of T-type device measured in a fast sweep time of 20 μs, with a wide range of read-after-write delay time from 1s to 20 ns. j, The memory window as a function of read-after-write delay time, extracted from (d). Note that the sweep time 20 μs, we used here, is nearly the minimum time resolution of the instrument for reading current. Additionally, to avoid any destructive read on the FeFET, the performed sweep voltages started from 0V, and stopped (at ±6V for T-type, and ±10V for I-type) when the FeFET was fully switched. Finally, the chosen ID currents for VTH extraction were plotted with horizontal lines in gray. Because of the precision reduction in 20 μs fast sweep, their ID currents for VTH extraction were set to 200nA and 500nA, respectively.

Source data

Extended Data Fig. 5 The switching energy of FeFET.

a, Transient gate voltage and current of a FeFET with AFE/ADE = 0.43. b, The gate charge by integration of gate current. An interval of one period is marked with a gray block. c, Benchmark of switching energy and speed with other memory technologies. SSD: solid-state drive; HDD: hard-disc drive. The switching energy is calculated as: \({{{\boldsymbol{E}}}}_{{{{\boldsymbol{switch}}}}} = \frac{{{{{\boldsymbol{Charge}}}} \times {{{\boldsymbol{Voltage}}}}}}{2} = \frac{{{{{\boldsymbol{Q}}}}_{{{{\boldsymbol{MAX}}}}} \cdot {{{\boldsymbol{V}}}}}}{2}\). The references for the data in c are summarized in Supplementary Table 5.

Source data

Extended Data Fig. 6 The multi-bit storage capability of T-type synapse.

a, Scheme of voltage sequence in the measurement of multi-bit capability. b, The 128-state (7-bit) output characteristics of the FeFET, shows good linear relationship. c, The symmetric and linear multi-state properties of the FeFET. The potentiation (red) and depression (blue) shows non-linearity factor of 0.876 (LTP) and 0.837 (LTD), respectively, and a symmetry factor of 0.039. (See fitting methods in Supplementary Note 1). d, All-analog computing. The ring datasets were normalized to two channels of voltages (Input-X and Input-Y) multiplied with different weights (conductance G1 and G2), and exported real-time current (Output-X and Output-Y) in an all-analog manner. e-g, The evolution of weights of layer 1 (e), layer 2 (f), and bias (g) during the training process.

Source data

Extended Data Fig. 7 The data flow of training and the experimental setup.

a, The data flow of training. The blocks in blue are accomplished in software, while the orange ones are realized in the Deplux FeFETs array. As for data flow, the processed data are plotted in green, weights of ANN are in yellow, and biases are in gray. All the data are vectorized as matrix, the size of which is marked with highlight. There are 4 interfaces for data transmission between the software and hardware. b, The gathered instruments for semi-automatic measurement of FeFETs array. c, d, Zoomed photo of modified components for array test in vacuum (c) and customized probe cards and a chip under test (d). More details were included in the Supplementary Note 4.

Extended Data Fig. 8 Simulation of non-linear localization task.

a, The evolution of weights for X of 1st layer. b, The evolution of weights for Y of 1st layer. c, The evolution of weights of 2nd layer. d,. The evolution of bias. e,. The cost and f, the accuracy curve of the entire training process. Classification accuracy firstly reached 100% at the 12th epoch. g, Original 300-point dataset for training process, 210 of them are divided to training, and the rest 90 were used for test. Red points are labeled as “inside”, while blue points are labeled as “outside”. h, The final classification result at the 16th epoch, drawn as a heatmap. The training data and test data are drawn with white and black border, respectively.

Source data

Extended Data Fig. 9 Statistics of 93 FeFETs in the array.

a, Transfer curves of 93 FeFETs (Yield=86%, 93 out of 108), VDS=0.1V. These FeFETs have a median current of 3.6 μA and variation coefficient of only 0.19 (standard deviation over median value), showing excellent uniformity. b, Cumulative plot of program and erase voltages, with symmetric median value of +3.9 V and −3.9 V and small variations. The memory window is strictly symmetric at 0 V.

Source data

Extended Data Fig. 10 Results of depth estimation on TIIO architecture.

a, Accuracy with 3 levels of threshold, b, Absolute Relative Error, c, Root Mean Square Error, d, Log Mean Absolute Error. e, Typical depth estimation of a subset of the KITTI dataset. The compared zones are marked with write blocks (for ground truth and TIIO results) and yellow blocks (for original scene). More details were included in the Methods.

Source data

Supplementary information

Supplementary Information

Supplementary Notes 1–6, Figs. 1–8, Tables 1–15 and references.

Training process for the 2D location task using a TIIO matrix. In every frame of this video, all of the important parameters and results of each epoch were plotted. The top row shows the weights for X of layer 1, weights for Y of layer 1, weights of layer 2 and bias. The bottom row shows the training and testing cost, training and testing accuracy, dataset, and the output heat map of the neural network. Once the weights and bias were calculated, the output heat map was subsequently determined, from which we could know how the network classifies a data point. A 100% accuracy case is that all the ‘outside’ points are coloured in blue, whereas the ‘inside’ points are in red (same as the labels in the original dataset). This case was realized in epoch 17.

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Ning, H., Yu, Z., Zhang, Q. et al. An in-memory computing architecture based on a duplex two-dimensional material structure for in situ machine learning. Nat. Nanotechnol. 18, 493–500 (2023). https://doi.org/10.1038/s41565-023-01343-0

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