Van der Waals moiré materials have emerged as a highly controllable platform to study electronic correlation phenomena1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17. Robust correlated insulating states have recently been discovered at both integer and fractional filling factors of semiconductor moiré systems10,11,12,13,14,15,16,17. In this study we explored the thermodynamic properties of these states by measuring the gate capacitance of MoSe2/WS2 moiré superlattices. We observed a series of incompressible states for filling factors 0–8 and anomalously large capacitance in the intervening compressible regions. The anomalously large capacitance, which was nearly 60% above the device’s geometrical capacitance, was most pronounced at small filling factors, below the melting temperature of the charge-ordered states, and for small sample–gate separation. It is a manifestation of the device-geometry-dependent Coulomb interaction between electrons and phase mixing of the charge-ordered states. Based on these results, we were able to extract the thermodynamic gap of the correlated insulating states and the device’s electronic entropy and specific heat capacity. Our findings establish capacitance as a powerful probe of the correlated states in semiconductor moiré systems and demonstrate control of these states via sample–gate coupling.
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Exciton-polarons in the presence of strongly correlated electronic states in a MoSe2/WSe2 moiré superlattice
npj 2D Materials and Applications Open Access 04 November 2022
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T.L. thanks Q. Shi and L. Ma for discussions on capacitance measurements. This work was supported by the US Department of Energy (DOE), Office of Science, Basic Energy Sciences (BES), under award number DE-SC0019481 (capacitance measurements), the National Science Foundation (Platform for the Accelerated Realization, Analysis, and Discovery of Interface Materials (PARADIM)) under cooperative agreement number DMR-1539918 (device fabrication) and the Air Force Office of Scientific Research Hybrid Materials MURI under award number FA9550-18-1-0480 (optical and device characterizations). This work was performed in part at Cornell NanoScale Facility, an NNCI member supported by NSF grant NNCI-1542081. Growth of the hBN crystals was supported by the Elemental Strategy Initiative of MEXT, Japan and CREST (JPMJCR15F3), JST. K.F.M. acknowledges support through a David and Lucille Packard Fellowship.
The authors declare no competing interests.
Peer review information Nature Nanotechnology thanks Raymond Ashoori and the other, anonymous, reviewer(s) for their contribution to the peer review of this work.
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Penetration capacitance (a) and top gate capacitance \(C/C_g\) (b) as a function of top gate voltage at 20 K (d/aM ≈ 0.6). We also show the top gate capacitance (obtained from a) in b for comparison. Good agreement between the penetration and top gate capacitance measurements is observed.
Top gate capacitance as a function of top gate voltage at 10 K (a) and at 20 K (b) under different excitation frequencies (10 mV modulation amplitude). A decrease in capacitance with increasing frequency is observed at 10 K, signifying the growing importance of the resistive component in the AC measurement. Meanwhile, no obvious frequency dependence is seen at 20 K, a temperature at which the sample/contact resistance becomes substantially smaller. The capacitance measurement is therefore in the low-frequency limit and reliable for most of the filling factors except ν = 1 and ν = 2.
a, Top gate (or filling) dependence of the capacitive channel output (top) and the resistive channel output (bottom) at different excitation frequencies (device 4 at 10 K). A constant background was subtracted from the capacitive channel for better comparison. The resistive signal gradually goes away with decreasing frequency for most of the filling factors except ν = 1 and ν = 2, where a small increase instead is observed. We conclude that the AC capacitance measurement at 10 K is reliable for most of the filling factors at the lowest frequency (137 Hz) for this device. However, for ν = 2 and ν = 1, the AC measurement is in the high-frequency limit so that the measured capacitance dips at ν = 2 and ν = 1 only reflect the large sample/contact resistance. b, Same as a measured at different temperatures (device 1 at 3137 Hz). As the resistive signal grows with decreasing temperature, the capacitive signal decreases accordingly at 10 K and above. The resistive signal is negligible compared to the capacitive signal. In addition, small resistive peaks at ν = 2 and ν = 1 grow with decreasing temperature. All of these observations show that the measurements are in the low-frequency limit for all filling factors in this device at 10 K and above.
The top gate capacitance shows incompressible states up to ν = 8.
a, Top gate capacitance as a function of filling factor at different temperatures. The charge-ordered states melt and the large capacitance enhancement disappears at high temperatures. b, Top gate capacitance at selected filling factors as a function of temperature. The capacitance in the incompressible region (v = 1/3 and 1/2) decreases rapidly below their transition temperatures, whereas the capacitance in the compressible regions (v = 0.42) increases. c, Filling factor versus top gate voltage at different temperatures obtained from integrating the data in a. The inset shows the temperature dependence of the top gate voltage at two constant filling factors. d, Filling factor dependence of (S−νkBln2), where S is the electronic entropy per moiré unit cell of the device extracted from two temperature windows, 15-40 (black) and 40-80 K (red).
Optical image of a typical device.
Lumped circuit model for the top gate capacitance measurement (a) and penetration capacitance measurement (b).
Calculated chemical potentials, μν, (in units of εa) at different filling factors ν and d/aM.
Source data for Fig. 1d,e with each panel as a different tab.
Source data for Fig. 2 with each panel given as a different tab.
Source data for Fig. 3 with each panel given as a different tab.
Source data for Extended Data Fig. 1 with each panel given as a different tab.
Source data for Extended Data Fig. 2 with each panel given as a different tab.
Source data for Extended Data Fig. 3 with each panel given as a different tab.
Source data for Extended Data Fig. 4 with each panel given as a different tab.
Source data for Extended Data Fig. 5 with each panel given as a different tab.
Source data for Extended Data Fig. 6 with each panel given as a different tab.
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Li, T., Zhu, J., Tang, Y. et al. Charge-order-enhanced capacitance in semiconductor moiré superlattices. Nat. Nanotechnol. 16, 1068–1072 (2021). https://doi.org/10.1038/s41565-021-00955-8