Room-temperature valleytronic transistor


Valleytronics, based on the valley degree of freedom rather than charge, is a promising candidate for next-generation information devices beyond complementary metal–oxide–semiconductor (CMOS) technology1,2,3,4. Although many intriguing valleytronic properties have been explored based on excitonic injection or the non-local response of transverse current schemes at low temperature4,5,6,7, demonstrations of valleytronic building blocks similar to transistors in electronics, especially at room temperature, remain elusive. Here, we report a solid-state device that enables a full sequence of generating, propagating, detecting and manipulating valley information at room temperature. Chiral nanocrescent plasmonic antennae8 are used to selectively generate valley-polarized carriers in MoS2 through hot-electron injection under linearly polarized infrared excitation. These long-lived valley-polarized free carriers can be detected in a valley Hall configuration9,10,11 even without charge current, and can propagate over 18 μm by means of drift. In addition, electrostatic gating allows us to modulate the magnitude of the valley Hall voltage. The electrical valley Hall output could drive the valley manipulation of a cascaded stage, rendering the device able to serve as a transistor free of charge current with pure valleytronic input/output. Our results demonstrate the possibility of encoding and processing information by valley degree of freedom, and provide a universal strategy to study the Berry curvature dipole in quantum materials.

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Fig. 1: Device configuration and experimental set-up for MoS2 valleytronic transistor.
Fig. 2: Generation of the valley-polarized electrons in the valleytronic transistor.
Fig. 3: Detection and transport of valley current in the valleytronic transistor.
Fig. 4: Manipulation of valley information by electrostatic gating.

Data availability

The data that support Figs. 14 can be found in the Source Data, and the data that support the other findings of this study are available from the corresponding author upon reasonable request. Source data are provided with this paper.


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This project was primarily supported by the National Key R&G Program of China (2018YFA0307300, 2018YFA0209100 and 2016YFA0200200), the National Natural Science Foundation of China (61934004, 61775092, 61674127 and 61874094), Zhejiang Natural Science Foundation (LZ17F040001), Program for High-Level Entrepreneurial and Innovative Talent Introduction of Jiangsu Province, Strategic Priority Research Program of the Chinese Academy of Sciences (grant no. XDB30000000), the Collaborative Innovation Center of Advanced Microstructures, the Fundamental Research Funds for the Central Universities and the Fundamental Research Funds for Zhejiang Provincial Colleges and Universities. L.S. acknowledges the financial support from the National Natural Science Foundation of China (NSAF, U1930402) and computational resources from the Beijing Computational Science Research Center. We also thank the supports from NJU micro-fabrication and integration centre, ZJU micro-nano fabrication centre and International Joint Innovation Centre, Zhejiang University, Haining campus.

Author information




X.W., L.L. and L.S. conceived the project. L.L., X.L., A.G., B.Z. and K.S. fabricated and measured the devices. L.S. modelled, prepared and characterized the plasmonic nanostructures. H.W. helped in the FDTD simulation. A.G., X.L. and F.M. helped prepare materials and perform electron beam lithography. G.H. and L.Y. helped perform scanning electron microscopy. B.Z. contributed to the data processing. X.W., L.L. and Y.X. analysed the data and wrote the manuscript. X.W., Y.X. and Y.S. supervised the research. All authors discussed the obtained results.

Corresponding authors

Correspondence to Yang Xu or Xiaomu Wang.

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Supplementary information

Supplementary Information

Supplementary Figs. 1–19, Notes 1–11 and refs. 1–14.

Source data

Source Data Fig. 1

Statistical source data.

Source Data Fig. 2

Statistical source data.

Source Data Fig. 3

Statistical source data.

Source Data Fig. 4

Statistical source data.

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Li, L., Shao, L., Liu, X. et al. Room-temperature valleytronic transistor. Nat. Nanotechnol. 15, 743–749 (2020).

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