# Thickness-controlled black phosphorus tunnel field-effect transistor for low-power switches

## Abstract

The continuous down-scaling of transistors has been the key to the successful development of current information technology. However, with Moore’s law reaching its limits, the development of alternative transistor architectures is urgently needed1. Transistors require a switching voltage of at least 60 mV for each tenfold increase in current, that is, a subthreshold swing (SS) of 60 mV per decade (dec). Alternative tunnel field-effect transistors (TFETs) are widely studied to achieve a sub-thermionic SS and high I60 (the current where SS becomes 60 mV dec–1)2. Heterojunction (HJ) TFETs show promise for delivering a high I60, but experimental results do not meet theoretical expectations due to interface problems in the HJs constructed from different materials. Here, we report a natural HJ-TFET with spatially varying layer thickness in black phosphorus without interface problems. We have achieved record-low average SS values over 4–5 dec of current (SSave_4dec ~22.9 mV dec–1 and SSave_5dec ~26.0 mV dec–1) with record-high I60 (I60 = 0.65–1 μA μm–1), paving the way for application in low-power switches.

## Main

Almost all aspects of life and society have changed in the past fifty years through dramatic improvements in our ability to process and communicate digital data, resulting from an integration and down-scaling of complementary metal–oxide–semiconductor (CMOS) transistors by Moore’s law. However, further down-scaling of transistors has stalled mainly due to power consumption1. Pop3 showed that formerly negligible standby power consumption had reached the level of switching power consumption. Reducing both switching and standby power consumption while further scaling transistors requires overcoming the thermionic limit of SS = 60 mV dec–1 in conventional metal–oxide–semiconductor field-effect transistors (MOSFETs; Supplementary Sections 1 and 2). The fundamental SS limit in MOSFETs originates from the thermal carrier injection mechanism, which prevents further reduction of a transistor supply voltage VDD needed to switch a transistor from the off to the on state. Furthermore, reduction of power consumption with SS < 60 mV dec–1 should be accompanied by a high enough on-current to drive the subsequent transistors at fast rates. The International Roadmap for Devices and Systems predicts that new device geometries with new materials beyond CMOS will be required to address transistor scaling challenges in the near future4. Nikonov and Young5 compared ultimate circuit performance for many CMOS device alternatives and identified tunnel transistors as a promising technology. In particular, TFETs have been suggested as a major alternative to MOSFETs, since the SS in TFETs can be substantially reduced below the thermionic limit (60 mV dec–1) due to the cold charge injection mechanism of band-to-band tunnelling (BTBT). Despite intensive research6, two critical, simultaneous requirements for TFETs to replace MOSFETs remain unfulfilled for low-power applications: (1) SSave_4–5dec (that is, the SSave over 4–5 dec of current) must be less than 60 mV dec–1 at room temperature and (2) the I60 must be high, equal to 1–10 μA μm–1, comparable to the level of the on-current at the threshold voltage in state-of-the-art MOSFETs. To date, only two n-type and no p-type TFETs have been reported to achieve SSave_4dec < 60 mV dec–1 (refs. 7,8) at T = 300 K, but with 2–5 orders of magnitude lower I60 than the preferred range. Increasing I60 is essential to operate a TFET-based logic gate at a faster rate since the on-current is inversely proportional to the switching delay.

The I60 value depends strongly on the BTBT transmission probability, which can be calculated by the Wentzel–Kramer–Brillouin (WKB) approximation9:

$$T_{{\mathrm{WKB}}} \approx \exp\left( { - \frac{{4\lambda \sqrt {2m^ \ast E_{\mathrm{g}}^3} }}{{3e\hbar (E_{\mathrm{g}} + \Delta \phi )}}} \right)$$
(1)

where Δϕ is the BTBT energy window, λ is the screening tunnelling length, m* is the carrier effective mass and Eg is the bandgap. To achieve a high I60, the transmission probability should be maximized by minimizing Eg, m* and λ. Computational models have shown that atomically thin 2D channel materials have an advantage in reducing λ by gate modulation over 3D materials10. Device simulations have shown that BTBT in HJs combining a small-bandgap source and large-bandgap channel material could significantly increase I60 and reduce SS while keeping Ioff low11,12,13. However, interface problems due to defects, oxides and lattice mismatches pose a major roadblock in developing high-performance HJ-TFETs. Sarkar et al.8 achieved SSave_4dec ~31 mV dec–1 in a MoS2/Ge vertical HJ-TFET. However, contrary to theoretical expectations, the HJ-TFET exhibited a very low I60 ~4.2 × 10–5 μA μm–1 with a low I60/Ioff ~7.0 × 103 due to the oxide tunnel barrier at the interface in the artificial HJ that formed by integrating MoS2 and Ge.

We use bulk and monolayer (ML) black phosphorus (BP) 2D materials as the source and channel of the HJ-TFETs, respectively (Fig. 1a), to take advantage of unique BP band properties to solve the two main problems of performance degradation for HJ-TFETs. (1) The direct bandgap changes with layer thickness from Eg ~2.0 eV in ML BP to Eg ~0.3 eV in bulk BP14 (Supplementary Fig. 3). This thickness-dependent band property allows us to solve one major issue for HJ-TFETs. HJs can be created by varying BP thickness rather than integrating different materials, avoiding many interface problems that degrade TFET performance. (2) We achieve effective carrier masses of 0.15me and 0.17me for holes and electrons, respectively, along the armchair direction (Supplementary Fig. 4), which is much lighter than other 2D materials with a nonzero bandgap, including transition metal dichalcogenides (MoS2, 0.55–0.56me; MoSe2, 0.49–0.61me; and WSe2, 0.44–0.48me)15,16, allowing a high I60 value in BP TFETs (see equation (1)) as well as high carrier mobility17,18. These unique BP band properties enabled us to achieve the lowest SSave_5dec ~26 mV dec–1 and the highest I60 ~1.0 μA μm–1, with I60/Ioff ~3.6 × 105, among all TFETs reported thus far, in our natural HJ-TFETs (NHJ-TFETs) with a single BP flake of varying thickness.

The single BP flake used in the NHJ-TFET consists of three distinct regions (Fig. 1a and Supplementary Fig. 8): (i) bulk BP (the source), (ii) ML BP only (the channel) and (iii) ML BP covered by ultrathin hexagonal boron nitride (hBN) and graphite (the drain). Since the bulk BP band (region (i)) does not shift with gate voltage due to the large thickness (60–100 nm; Supplementary Fig. 9), both the top-gate voltage, VTG, and the back-gate voltage, VBG, affect only the ML BP band. While VTG shifts the ML BP band in region (ii), VBG shifts the ML BP band in both regions (ii) and (iii). The use of ultrathin hBN (2–3 layers) between the graphite and ML BP in region (iii) has advantages over direct graphite contact on the ML BP (Supplementary Fig. 8). (1) Ultrathin hBN placed between graphite and ML BP protects the ML BP region (iii) band structure, since the strong chemical interaction between ML BP and metal atoms can destroy ML BP band structures and cause metallization19. (2) Fermi-level pinning does not occur in ML BP region (iii) since the ultrathin hBN increases the distance between the BP and the graphite layer. Fermi-level pinning is expected to occur due to chemical bonding between P and metal atoms regardless of the metal work function19. Therefore, the ML BP region (iii) chemical potential can be tuned by the drain bias voltage applied to graphite, VD, with an ultrathin hBN placed between the graphite and ML BP (Supplementary Section 8). In addition, we fabricated devices such that carrier transport occurs with a smaller m* in the armchair direction than in the zigzag direction to enhance the on-current.

Figure 1b,c shows representative transfer curves of two BP NHJ-TFET devices at |VD| ≤ 0.7 V. Device 1 has a bottom-gate dielectric of 285-nm SiO2 and top-gate dielectric of 10-nm hBN while device 2 has a bottom-gate dielectric of 3-nm hBN and top-gate dielectric of 5-nm hBN. The channel length (L) and width (W) are L ~0.7 μm and W ~1 μm in device 1, and L ~0.5 μm and W ~1 μm in device 2. Here, we demonstrate p-type TFET operation in device 1 with SSave_4dec < 60 mV dec–1. Furthermore, the p-type operation of device 1 at VD = –0.6 V outperforms all previous TFETs (including n-type TFETs) for both SSave_4dec and I60, with I60 close to the preferred range (1–10 μA μm–1)2,11. The measured drain current, ID, versus VTG (Fig. 1b; gate dielectric, 10-nm hBN) shows SSave_4dec ~23.7 mV dec–1 and I60 ~0.65 μA μm–1. The n-type operation in device 2 at VD = +0.7 V (Fig. 1c) shows an ultralow SSave_4dec as well as the highest I60 among all previous TFETs with a sub-thermionic SSave_4dec. The measured ID versus VBG (gate dielectric, 3-nm hBN) shows SSave_4dec ~24.0 mV dec–1 and I60 ~0.054 μA μm–1. Note that the on/off switching requires much lower voltages, ΔVTG = 0.15 V and ΔVBG = 0.2 V for devices 1 and 2, respectively, than the ΔVG = 0.7 V needed in state-of-the-art MOSFETs, implying much reduced power consumption in our BP NHJ-TFETs.

Device optimization for both n- and p-type TFETs is essential to develop low-power complementary TFET technology for beyond-CMOS devices. As described above, positive (negative) VD shifts the region (iii) band downwards (upwards; see the band diagrams in Fig. 1b,c). This control of the region (iii) ML band edges by VD enables our BP devices to operate as complementary n- and p-type TFETs depending on the sign of VD. Note that, if VD did not shift the band of ML BP region (iii), our devices could not operate as complementary TFETs regardless of the sign of VD (Supplementary Section 8). In the on state, the region (ii) and (iii) ML BP bands are adjusted with gate voltages such that a tunnelling energy window, Δϕ > 0, opens between the bulk and ML BP, and hence the BTBT transmission probability (equation (1)) becomes significant. If the energy window is blocked, the TFET enters the off state. For an n-type TFET with VD > 0, Δϕ = (bulk BP valence band maximum) – (ML BP conduction band minimum), whereas for a p-type TFET with VD < 0, Δϕ = (ML BP valence band maximum) – (bulk BP conduction band minimum).

We observed two on/off mechanisms in our heterostructured BP devices depending on VBG and VD: thermal injection and BTBT as shown in Fig. 2a,b. Thermal injection occurred when barrier height was reduced inside the ML BP between regions (ii) and (iii) by VBG such that carriers having higher energy than the barrier height according to the Boltzmann distribution could move over the barrier. On the other hand, BTBT occurred when the source (bulk BP, region (i)) and the channel (ML BP, region (ii)) became oppositely doped and the tunnel window Δϕ > 0 opened (Supplementary Fig. 12). From the temperature-dependent transfer curves, we extracted SSave_4dec and SSave_2dec, respectively, in the BTBT and thermal injection regimes. The insets of Fig. 2a,b show that both p- and n-type operations with SSave_4dec < 60 mV dec–1 at T = 300 K retain a constant SSave_4dec across 8–300 K, confirming that the carrier injection mechanism is BTBT. When BTBT dominates, thermally activated sections of the source Fermi distributions below the conduction band minimum and above the valence band maximum of the source and channel are effectively blocked, and hence the tunnelling probability (equation (1)) is temperature independent. Therefore, the electronic system is effectively cooled; that is, it maintains a low temperature. On the other hand, the SS shows a linear dependence on T in the thermal injection limit due to the exponential increase in the transport of thermally activated carriers over the potential barrier with T. Note that the temperature-dependent transfer curves show an additional feature in BTBT transitions: the BTBT threshold voltage shifts with temperature (Fig. 2 and Supplementary Fig. 13). We consider a few possibilities to explain the BTBT threshold voltage shifts. Most previous experimental and theoretical studies have shown that threshold voltage shifts of TFETs with temperature originate from trap-assisted tunnelling (TAT), Shockley–Read–Hall (SRH) recombination or the Urbach tail (exponentially decaying evanescent states near the band edges). However, TAT, SRH recombination and the Urbach tail were the major roadblocks to improving TFETs, since they increase both the SS and Ioff with temperature20, inconsistent with our observation of constant SS and Ioff. Another possibility is that the ML BP bandgap reduction with temperature could induce a threshold voltage shift (Supplementary Fig. 14). In this case, the BTBT on-current also increases with temperature since the BTBT energy window increases between the bulk and ML BP due to the decrease in the ML BP bandgap. While only thermal injection contributes to the electron-side IV curves in Fig. 2a, both thermal injection and BTBT inside the ML BP contribute to the hole-side IV curves in Fig. 2b. Because thermal injection, that is, the mechanism of carrier transport in a conventional CMOS transistor, dominates the transport in the electron transport in Fig. 2a, the on-current should decrease with temperature due to phonon scattering and mobility degradation. Because both thermal injection and BTBT inside the ML BP contribute to the hole-side IV curves in Fig. 2b, and the BTBT on-current significantly depends on the BTBT energy window, which increases with temperature due to the decrease in the ML BP bandgap, the on-current increases with temperature in the hole transport at positive VD in Fig. 2b, opposite to the electron transport at negative VD in Fig. 2a. The on/off transition of electron transport dominated by thermal injection in Fig. 2a occurs at the same VBG with changing temperature, implying that the conduction band edge of the drain ML BP does not change with temperature, which might be related to the Schottky barrier formed between the graphite contact and the ML BP21. A decrease in the bandgap of ML 2D van der Waals layers with temperature has been observed in transition metal dichalcogenides such as ML MoS2 (ref. 22). To our best knowledge, there have been neither experimental nor theoretical reports on the temperature dependence of the ML BP bandgap. Another possible explanation for the temperature-dependent threshold voltage shift is a work function change of the back and top gates with temperature. According to simulation studies23,24,25, a work function change of the gates in our devices can induce a threshold voltage shift with constant SS and Ioff. Accurately determining the mechanism of the temperature-dependent threshold voltage shift in our BP NHJ-TFETs will require further systematic studies.

Figure 3 shows a comparison of BP NHJ-TFETs with the only two previously reported n-type TFETs to achieve SSave_4dec < 60 mV dec–1 and the state-of-the-art Intel 14-nm Si MOSFET26. We extracted ID versus SS and I60 versus SSave_4dec from the transfer curves shown in Supplementary Fig. 20. The comparison data clearly indicate that (1) BP NHJ-TFETs outperform all previous TFETs and (2) more importantly, BP NHJ-TFETs fullfill the two critical requirements (sub-thermionic SSave_4dec and high I60) simultaneously in both p- and n-type operations. To date, only two n-type and no p-type TFETs have been reported to achieve a sub-thermionic SSave_4dec < 60 mV dec–1, but they achieved this value with an I60 value that was 2–5 orders of magnitude lower than the required range of 1–10 μA μm–1. Figure 3a shows that the BP NHJ-TFETs exhibit an Ioff that is 3–4 orders of magnitude lower than that of the Intel 14-nm Si MOSFET (Supplementary Fig. 20), indicating that standby power consumption is reduced by 103–104. Furthermore, the achieved I60 of up to ~1 μA μm–1, comparable to the on-current near the threshold voltage in MOSFETs suggest that NHJ-TFETs would be a competitive replacement for low-power switches, operating at fast enough rates. Figure 3b clearly shows that BP NHJ-TFET performance is the closest to the preferred region, with the best values of the two major figures of merit, that is, low SSave_4dec and high I60, among all the TFETs. In addition, Supplementary Table 1 compares other previous TFETs and includes values for SSave_5dec and I60/Ioff.

Although the lowest drain voltage we used was VD = –0.6 V for p-type and VD = +0.7 V for n-type operation, VD is expected to be further reduced with enhanced performance if we use high-κ dielectric materials between graphite and ML BP or control the chemical doping of the drain region. This could also improve the on-current of the BP NHJ-TFETs to close to that of a MOSFET (100–1,000 μA μm–1) at low bias (≤0.5 V) owing to the absence of interface problems in the natural BP HJ27.

## Methods

### Device fabrication and measurement

We first prepared graphite, hBN and BP flakes on a 90-nm SiO2 wafer by mechanical exfoliation from bulk crystals in an argon-filled glove box (<0.1 ppm of H2O and O2) to maintain clean surfaces and prevent contamination from air exposure. Subsequently, by using a polydimethylsiloxane (PDMS) stamp covered with a polycarbonate (PC) film28, each flake was picked up from the substrate at 80 °C and eventually released on a 285-nm SiO2 substrate on top of highly doped Si at an elevated temperature. The PC film was washed out by chloroform followed by acetone and isopropyl alcohol. Then, we used standard e-beam lithography and CF4 plasma etching followed by e-beam evaporation to prepare electrical contacts to the van der Waals layers. Finally, additional metal deposition was performed to form the top gate. After the device fabrication was complete, we performed DC measurement to obtain transfer curves at temperatures from 300 K to 8 K in a home-built cryostat. We used a Keithley 2400 or Yokogawa 7651 to bias DC voltages to the drain (or gate) electrodes. To measure the ID values, we used a DDPCA-300 preamplifier to amplify the ID signal by 106 and convert it to a voltage and we measured the amplified voltage signal using a Keithley 2182a nanovoltmeter. To increase accuracy and reduce noise level, we averaged each data point taken at every 5-mV gate step 30 times for both upwards and downwards gate sweeps. Each transfer curve (ID vs VG) plots the absolute values of ID on a log scale as a function of VG.

### ML BP characterization

We identified ML BP by combining three different characterization methods: atomic force microscopy, Raman spectroscopy and photoluminescence (Supplementary Section 5). In addition, we performed polarized Raman spectroscopy to determine the crystal orientation of the BP flakes. We determined the armchair direction along which the Ag1 and Ag2 modes show maximum peak intensities while the B2g mode shows a minimum peak intensity29,30 (Supplementary Section 4).

## Data availability

The data that support the findings of this study are available from the corresponding authors on reasonable request.

## References

1. 1.

Mack, C. A. Fifty years of Moore’s law. IEEE Trans. Semicond. Manuf. 24, 202–207 (2011).

2. 2.

Vandenberghe, W. G. et al. Figure of merit for and identification of sub-60 mV/decade devices. Appl. Phys. Lett. 102, 013510 (2013).

3. 3.

Pop, E. Energy dissipation and transport in nanoscale devices. Nano Res. 3, 147–169 (2010).

4. 4.

5. 5.

Nikonov, D. E. & Young, I. A. Overview of beyond-CMOS devices and a uniform methodology for their benchmarking. Proc. IEEE 101, 2498–2533 (2013).

6. 6.

Seabaugh, A. et. al., Steep slope transistors: tunnel FETs and beyond.proc. IEEE European Solid-State Device Research Conference (ESSDERC) 349–351 (IEEE, 2016).

7. 7.

Tomioka, K., Yoshimura, M. & Fukui, T., Steep-slope tunnel field-effect transistors using III–V nanowire/Si heterojunction. In 2012 Symposium on VLSI Technology 47–48 (IEEE, 2012).

8. 8.

Sarkar, D. et al. A subthermionic tunnel field-effect transistor with an atomically thin channel. Nature 526, 91–95 (2015).

9. 9.

Knoch, J., Mantl, S. & Appenzeller, J. Impact of the dimensionality on the performance of tunneling FETs: bulk versus one-dimensional devices. Solid State Electron. 51, 572–578 (2007).

10. 10.

Fiori, G. et al. Electronics based on two-dimensional materials. Nat. Nanotechnol. 9, 768–779 (2014).

11. 11.

Ionescu, A. M. & Riel, H. Tunnel field-effect transistors as energy-efficient electronic switches. Nature 479, 329–337 (2011).

12. 12.

Verhulst, A. S., Vandenberghe, W. G., Maex, K. & Groeseneken, G. Boosting the on-current of a n-channel nanowire tunnel field-effect transistor by source material optimization. J. Appl. Phys. 104, 064514 (2008).

13. 13.

Nayfeh, O. M. et al. Design of tunneling field-effect transistors using strained-silicon/strained-germanium type-II staggered heterojunctions. IEEE Electron Device Lett. 29, 1074–1077 (2008).

14. 14.

Tran, V., Soklaski, R., Liang, Y. & Yang, L. Layer-controlled band gap and anisotropic excitons in few-layer black phosphorus. Phys. Rev. B 89, 235319 (2014).

15. 15.

Rasmussen, F. A. & Thygesen, K. S. Computational 2D materials database: electronic structure of transition-metal dichalcogenides and oxides. J. Phys. Chem. C 119, 13169–13183 (2015).

16. 16.

Qiao, J., Kong, X., Hu, Z. X., Yang, F. & Ji, W. High-mobility transport anisotropy and linear dichroism in few-layer black phosphorus. Nat. Commun. 5, 4475 (2014).

17. 17.

Li, L. et al. Black phosphorus field-effect transistors. Nat. Nanotechnol. 9, 372–377 (2014).

18. 18.

Li, L. et al. Quantum Hall effect in black phosphorus two-dimensional electron system. Nat. Nanotechnol. 11, 593–597 (2016).

19. 19.

Pan, Y. et al. Monolayer phosphorene−metal contacts. Chem. Mater. 28, 2100–2109 (2016).

20. 20.

Sajjad, R. N., Chern, W., Hoyt, J. L. & Antoniadis, D. A. Trap assisted tunneling and its effect on subthreshold swing of tunnel FETs. IEEE Trans. Electron Devices 63, 4380–4387 (2016).

21. 21.

Kang, J., Liu, W., Sarkar, D., Jena, D. & Banerjee, K. Computational study of metal contacts to monolayer transition-metal dichalcogenide semiconductors. Phys. Rev. X 4, 031005 (2014).

22. 22.

Tang, W., Rassay, S. S. & Ravindra, N. M. Electronic & optical properties of transition-metal dichalcogenides. Madridge J. Nanotechnol. Nanosci. 2, 58–64 (2017).

23. 23.

Rahi, S. B., Ghosh, B. & Bishnoi, B. Temperature effect on hetero structure junctionless tunnel FET. J. Semicond. 36, 034002 (2015).

24. 24.

Rahi, S. B., Asthana, P. & Gupta, S. Heterogate junctionless tunnel field-effect transistor: future of low-power devices. J. Comput. Electron. 16, 30–38 (2017).

25. 25.

Abedini, M., Ziabari, S. A. S. & Eskandarin, A. A high-performance p-type based heterostructure electrically doped NTFET and representation of a neural network model. Appl. Phys. A 125, 318 (2019).

26. 26.

Natarajan, S. et. al., A 14nm logic technology featuring 2nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm2 SRAM cell size. In 2014 IEEE International Electron Devices Meeting 3.7.1–3.7.3 (IEEE, 2014).

27. 27.

Chen, F. W., Ilatikhameneh, H., Ameen, T. A., Klimeck, G. & Rahman, R. Thickness engineered tunnel field-effect transistors based on phosphorene. IEEE Electron Device Lett. 38, 130–133 (2017).

28. 28.

Zomer, P. J., Guimaraes, M. H. D., Brant, J. C., Tombros, N. & van Wees, B. J. Fast pick up technique for high quality heterostructures of bilayer graphene and hexagonal boron nitride. Appl. Phys. Lett. 105, 013101 (2014).

29. 29.

Kim, J. et al. Anomalous polarization dependence of Raman scattering and crystallographic orientation of black phosphorus. Nanoscale 7, 18708–18715 (2015).

30. 30.

Ling, X. et al. Anisotropic electron-photon and electron-phonon interactions in black phosphorus. Nano Lett. 16, 2260–2267 (2016).

## Acknowledgements

We thank P. Kim, A. Seabaugh, R. Sajjad, E. Yablonovitch, F. Liu, G. Klimeck, H. J. Choi and E. H. Hwang for helpful discussions. We also thank C. Lee for help with the dry-transfer technique. S. Cho acknowledges support from the Korea NRF (Grant no. 2019M3F3A1A03079760 and Grant no. 2016R1A5A1008184) and the KI 2019 Transdisciplinary Research Program. K.W. and T.T. acknowledge support from the Elemental Strategy Initiative conducted by MEXT, Japan, A3 Foresight by JSPS and CREST (JPMJCR15F3), JST.

## Author information

Authors

### Contributions

S. Cho conceived and supervised the project. S.K. fabricated devices and performed measurements. G.M. and W.S. assisted with fabrication of devices. G.M. and S. Chang assisted with the Raman and photoluminescence measurement of the BP flakes. K.W. and T.T. grew high-quality hBN single crystals. G.M., W.S., H.L., B.K. and T.J. assisted with the low-temperature transport measurements. S. Cho and S.K. analysed the data and wrote the manuscript. All the authors contributed to editing the manuscript.

### Corresponding author

Correspondence to Sungjae Cho.

## Ethics declarations

### Competing interests

The authors declare no competing interests.

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## Supplementary information

### Supplementary Information

Supplementary Figs. 1–20, Table 1 and refs. 1–41.

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Kim, S., Myeong, G., Shin, W. et al. Thickness-controlled black phosphorus tunnel field-effect transistor for low-power switches. Nat. Nanotechnol. 15, 203–206 (2020). https://doi.org/10.1038/s41565-019-0623-7