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Small footprint transistor architecture for photoswitching logic and in situ memory


The need for continuous size downscaling of silicon transistors is driving the industrial development of strategies to enable further footprint reduction1,2. The atomic thickness of two-dimensional materials allows the potential realization of high-area-efficiency transistor architectures. However, until now, the design of devices composed of two-dimensional materials has mimicked the basic architecture of silicon circuits3,4,5,6. Here, we report a transistor based on a two-dimensional material that can realize photoswitching logic (OR, AND) computing in a single cell. Unlike the conventional transistor working mechanism, the two-dimensional material logic transistor has two surface channels. Furthermore, the material thickness can change the logic behaviour—the architecture can be flexibly expanded to achieve in situ memory such as logic computing and data storage convergence in the same device. These devices are potentially promising candidates for the construction of new chips that can perform computing and storage with high area-efficiency and unique functions.

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Fig. 1: Logic gates based on 2D transistors.
Fig. 2: The OR logic gate via a single transitor and the unique two-surface-channel device mechanism.
Fig. 3: Demonstration of a single 2D transistor (monolayer) for photoswitching logic and the channel material thickness dependence.
Fig. 4: Logic behaviour of the 2D floating-gate transistor with and without charges in the floating gate.
Fig. 5: Demonstration of in situ memory in a single 2D floating-gate transistor.

Data availability

The data that support the plots in this paper and other findings of this study are available from the corresponding authors on reasonable request.


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This work was supported by the National Key Research and Development Program (2017YFB0405600), National Natural Science Foundation of China (61622401, 61851402 and 61734003), Shanghai Education Development Foundation and Shanghai Municipal Education Commission Shuguang Program (18SG01). P.Z. acknowledges support from Shanghai Municipal Science and Technology Commission (18JC1410300). P.Z. thanks D. Sandubashao’s group for encouragement and help, and H. Zhou from Giantec Semiconductor for assistance during device fabrication and for discussions.

Author information




P.Z. conceived the idea and supervised the experiments. C.L. performed the device fabrication and carried out the electrical characteristics measurements. H.C., X.H., H.Z., J.H., Y.-G.J. and X.Z. provided valuable input to the overall experiments. D.W.Z. provided input regarding the experiment conditions. C.L. and P.Z. wrote the paper, with help from all authors.

Corresponding authors

Correspondence to David Wei Zhang or Peng Zhou.

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The authors declare no competing interests.

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Journal peer review information: Nature Nanotechnology thanks Wei Chen and other anonymous reviewer(s) for their contribution to the peer review of this work.

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Supplementary information

Supplementary Information

Supplementary Sections 1–8, Supplementary Figs. 1–8, Supplementary references 1–7

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Liu, C., Chen, H., Hou, X. et al. Small footprint transistor architecture for photoswitching logic and in situ memory. Nat. Nanotechnol. 14, 662–667 (2019).

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