Skip to main content

Thank you for visiting nature.com. You are using a browser version with limited support for CSS. To obtain the best experience, we recommend you use a more up to date browser (or turn off compatibility mode in Internet Explorer). In the meantime, to ensure continued support, we are displaying the site without styles and JavaScript.

  • Letter
  • Published:

Small footprint transistor architecture for photoswitching logic and in situ memory

Nature Nanotechnology volume 14, pages 662–667 (2019)Cite this article

Subjects

Abstract

The need for continuous size downscaling of silicon transistors is driving the industrial development of strategies to enable further footprint reduction1,2. The atomic thickness of two-dimensional materials allows the potential realization of high-area-efficiency transistor architectures. However, until now, the design of devices composed of two-dimensional materials has mimicked the basic architecture of silicon circuits3,4,5,6. Here, we report a transistor based on a two-dimensional material that can realize photoswitching logic (OR, AND) computing in a single cell. Unlike the conventional transistor working mechanism, the two-dimensional material logic transistor has two surface channels. Furthermore, the material thickness can change the logic behaviour—the architecture can be flexibly expanded to achieve in situ memory such as logic computing and data storage convergence in the same device. These devices are potentially promising candidates for the construction of new chips that can perform computing and storage with high area-efficiency and unique functions.

This is a preview of subscription content, access via your institution

Access options

Buy this article

  • Purchase on Springer Link
  • Instant access to full article PDF
Buy now

Prices may be subject to local taxes which are calculated during checkout

Fig. 1: Logic gates based on 2D transistors.
Fig. 2: The OR logic gate via a single transitor and the unique two-surface-channel device mechanism.
Fig. 3: Demonstration of a single 2D transistor (monolayer) for photoswitching logic and the channel material thickness dependence.
Fig. 4: Logic behaviour of the 2D floating-gate transistor with and without charges in the floating gate.
Fig. 5: Demonstration of in situ memory in a single 2D floating-gate transistor.

Similar content being viewed by others

Data availability

The data that support the plots in this paper and other findings of this study are available from the corresponding authors on reasonable request.

References

  1. Seabaugh, A. C. & Zhang, Q. Low-voltage tunnel transistors for beyond CMOS logic. Proc. IEEE 98, 2095–2110 (2010).

    Article  CAS  Google Scholar 

  2. Ionescu, A. M. & Riel, H. Tunnel field-effect transistors as energy-efficient electronic switches. Nature 479, 329–337 (2011).

    Article  CAS  Google Scholar 

  3. Radisavljevic, B., Radenovic, A., Brivio, J., Giacometti, V. & Kis, A. Single-layer MoS2 transistors. Nat. Nanotechnol. 6, 147–150 (2011).

    Article  CAS  Google Scholar 

  4. Fang, H. et al. High-performance single layered WSe2 p-FETs with chemically doped contacts. Nano Lett. 12, 3788–3792 (2012).

    Article  CAS  Google Scholar 

  5. Desai, S. B. et al. MoS2 transistors with 1-nanometer gate lengths. Science 354, 99–102 (2016).

    Article  CAS  Google Scholar 

  6. Si, M. et al. Steep-slope hysteresis-free negative capacitance MoS2 transistors. Nat. Nanotechnol. 13, 24–28 (2018).

    Article  CAS  Google Scholar 

  7. Li, L. et al. Black phosphorus field-effect transistors. Nat. Nanotechnol. 9, 372–377 (2014).

    Article  CAS  Google Scholar 

  8. Liu, C. et al. A semi-floating gate memory based on van der Waals heterostructures for quasi-non-volatile applications. Nat. Nanotechnol. 13, 404–410 (2018).

    Article  CAS  Google Scholar 

  9. Liu, C. et al. Eliminating overerase behavior by designing energy band in high-speed charge-trap memory based on WSe2. Small 13, 1604128 (2017).

    Article  Google Scholar 

  10. Vu, Q. A. et al. Two-terminal floating-gate memory with van der Waals heterostructures for ultrahigh on/off ratio. Nat. Commun. 7, 12725 (2016).

    Article  CAS  Google Scholar 

  11. Huang, M. et al. Multifunctional high-performance van der Waals heterostructures. Nat. Nanotechnol. 12, 1148–1154 (2017).

    Article  CAS  Google Scholar 

  12. Shim, J. et al. Phosphorene/rhenium disulfide heterojunction-based negative differential resistance device for multi-valued logic. Nat. Commun. 7, 13413 (2016).

    Article  CAS  Google Scholar 

  13. Wachter, S., Polyushkin, D. K., Bethge, O. & Mueller, T. A microprocessor based on a two-dimensional semiconductor. Nat. Commun. 8, 14948 (2017).

    Article  CAS  Google Scholar 

  14. Britnell, L. et al. Electron tunneling through ultrathin boron nitride crystalline barriers. Nano Lett. 12, 1707–1710 (2012).

    Article  CAS  Google Scholar 

  15. Mak, K. F., Lee, C., Hone, J., Shan, J. & Heinz, T. F. Atomically thin MoS2: a new direct-gap semiconductor. Phys. Rev. Lett. 105, 474–479 (2010).

    Article  Google Scholar 

  16. Zhao, W. et al. Evolution of electronic structure in atomically thin sheets of WS2 and WSe2. ACS Nano 7, 791–797 (2012).

    Article  Google Scholar 

  17. Yu, L. et al. Design, modeling and fabrication of CVD grown MoS2 circuits with E-Mode FETs for large-area electronics. Nano Lett. 16, 6349–6356 (2016).

    Article  CAS  Google Scholar 

  18. Lopezsanchez, O., Lembke, D., Kayci, M., Radenovic, A. & Kis, A. Ultrasensitive photodetectors based on monolayer MoS2. Nat. Nanotechnol. 8, 497–501 (2013).

    Article  CAS  Google Scholar 

  19. Ohta, T. et al. Interlayer interaction and electronic screening in multilayer graphene investigated with angle-resolved photoemission spectroscopy. Phys. Rev. Lett. 98, 206802 (2007).

    Article  Google Scholar 

  20. Borghetti, J. et al. ‘Memristive’ switches enable ‘stateful’ logic operations via material implication. Nature 464, 873–876 (2010).

    Article  CAS  Google Scholar 

  21. Shulaker, M. M. et al. Three-dimensional integration of nanotechnologies for computing and data storage on a single chip. Nature 547, 74–78 (2017).

    Article  CAS  Google Scholar 

Download references

Acknowledgements

This work was supported by the National Key Research and Development Program (2017YFB0405600), National Natural Science Foundation of China (61622401, 61851402 and 61734003), Shanghai Education Development Foundation and Shanghai Municipal Education Commission Shuguang Program (18SG01). P.Z. acknowledges support from Shanghai Municipal Science and Technology Commission (18JC1410300). P.Z. thanks D. Sandubashao’s group for encouragement and help, and H. Zhou from Giantec Semiconductor for assistance during device fabrication and for discussions.

Author information

Author notes

  1. These authors contributed equally: Chunsen Liu, Peng Zhou.

Authors and Affiliations

  1. State Key Laboratory of ASIC and System, School of Microelectronics, Fudan University, Shanghai, China

    Chunsen Liu, Huawei Chen, Xiang Hou, Heng Zhang, Jun Han, Yu-Gang Jiang, Xiaoyang Zeng, David Wei Zhang & Peng Zhou

Authors
  1. Chunsen Liu
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Huawei Chen
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Xiang Hou
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Heng Zhang
    View author publications

    You can also search for this author in PubMed Google Scholar

  5. Jun Han
    View author publications

    You can also search for this author in PubMed Google Scholar

  6. Yu-Gang Jiang
    View author publications

    You can also search for this author in PubMed Google Scholar

  7. Xiaoyang Zeng
    View author publications

    You can also search for this author in PubMed Google Scholar

  8. David Wei Zhang
    View author publications

    You can also search for this author in PubMed Google Scholar

  9. Peng Zhou
    View author publications

    You can also search for this author in PubMed Google Scholar

Contributions

P.Z. conceived the idea and supervised the experiments. C.L. performed the device fabrication and carried out the electrical characteristics measurements. H.C., X.H., H.Z., J.H., Y.-G.J. and X.Z. provided valuable input to the overall experiments. D.W.Z. provided input regarding the experiment conditions. C.L. and P.Z. wrote the paper, with help from all authors.

Corresponding authors

Correspondence to David Wei Zhang or Peng Zhou.

Ethics declarations

Competing interests

The authors declare no competing interests.

Additional information

Journal peer review information: Nature Nanotechnology thanks Wei Chen and other anonymous reviewer(s) for their contribution to the peer review of this work.

Publisher’s note: Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Supplementary information

Supplementary Information

Supplementary Sections 1–8, Supplementary Figs. 1–8, Supplementary references 1–7

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Liu, C., Chen, H., Hou, X. et al. Small footprint transistor architecture for photoswitching logic and in situ memory. Nat. Nanotechnol. 14, 662–667 (2019). https://doi.org/10.1038/s41565-019-0462-6

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1038/s41565-019-0462-6

This article is cited by

Search

Advanced search

Quick links

Nature Briefing

Sign up for the Nature Briefing newsletter — what matters in science, free to your inbox daily.

Get the most important science stories of the day, free in your inbox. Sign up for Nature Briefing