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Steep-slope hysteresis-free negative capacitance MoS2 transistors

Nature Nanotechnology volume 13, pages 24–28 (2018)Cite this article

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Abstract

The so-called Boltzmann tyranny defines the fundamental thermionic limit of the subthreshold slope of a metal–oxide–semiconductor field-effect transistor (MOSFET) at 60 mV dec−1 at room temperature and therefore precludes lowering of the supply voltage and overall power consumption1,2. Adding a ferroelectric negative capacitor to the gate stack of a MOSFET may offer a promising solution to bypassing this fundamental barrier3. Meanwhile, two-dimensional semiconductors such as atomically thin transition-metal dichalcogenides, due to their low dielectric constant and ease of integration into a junctionless transistor topology, offer enhanced electrostatic control of the channel4,5,6,7,8,9,10,11,12. Here, we combine these two advantages and demonstrate a molybdenum disulfide (MoS2) two-dimensional steep-slope transistor with a ferroelectric hafnium zirconium oxide layer in the gate dielectric stack. This device exhibits excellent performance in both on and off states, with a maximum drain current of 510 μA μm−1 and a sub-thermionic subthreshold slope, and is essentially hysteresis-free. Negative differential resistance was observed at room temperature in the MoS2 negative-capacitance FETs as the result of negative capacitance due to the negative drain-induced barrier lowering. A high on-current-induced self-heating effect was also observed and studied.

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Fig. 1: Schematic and fabrication of MoS2 NC-FETs.
Fig. 2: Off-state switching characteristics of MoS2 NC-FETs.
Fig. 3: NDR and negative DIBL in MoS2 NC-FETs.
Fig. 4: On-state characteristics and self-heating of MoS2 NC-FETs.

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Acknowledgements

This material is based upon work partly supported by the Air Force Office of Scientific Research (AFOSR)/National Science Foundation (NSF) Two-Dimensional Atomic-layer Research and Engineering (2DARE) programme, Army Research Office (ARO) and Semiconductor Research Corporation (SRC).

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Authors and Affiliations

  1. School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, 47907, USA

    Mengwei Si, Chunsheng Jiang, Nathan J. Conrad, Hong Zhou, Kerry D. Maize, Gang Qiu, Ali Shakouri, Muhammad A. Alam & Peide D. Ye

  2. Birck Nanotechnology Center, Purdue University, West Lafayette, IN, 47907, USA

    Mengwei Si, Nathan J. Conrad, Hong Zhou, Kerry D. Maize, Gang Qiu, Ali Shakouri & Peide D. Ye

  3. National Nano Device Laboratories, Hsinchu, 300, Taiwan

    Chun-Jung Su & Chien-Ting Wu

  4. Tsinghua National Laboratory for Information Science and Technology, Institute of Microelectronics, Tsinghua University, Beijing, 100084, China

    Chunsheng Jiang

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  1. Mengwei Si
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Contributions

P.D.Y. conceived the idea and supervised the experiments. C.J.S. performed the ALD of HZO and Al2O3 and dielectric physical analysis. M.S. performed the device fabrication, d.c. and C–V measurements, and data analysis. M.S. and N.J.C. carried out the fast I–V measurement. M.S. and G.Q. performed the AFM measurement. H.Z., K.D.M. and A.S. did the thermo-reflectance imaging. G.Q. performed the Raman and photoluminescence experiment. C.T.W. conducted TEM and EDS analyses. C.J. and A.M.A. conducted the theoretical calculations and analysis. M.S., A.M.A. and P.D.Y. summarized the manuscript and all authors commented on it.

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Correspondence to Peide D. Ye.

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Steep Slope Hysteresis-free Negative Capacitance MoS2 Transistors.

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Si, M., Su, CJ., Jiang, C. et al. Steep-slope hysteresis-free negative capacitance MoS2 transistors. Nature Nanotech 13, 24–28 (2018). https://doi.org/10.1038/s41565-017-0010-1

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