Letter | Published:

Steep-slope hysteresis-free negative capacitance MoS2 transistors

Nature Nanotechnologyvolume 13pages2428 (2018) | Download Citation


The so-called Boltzmann tyranny defines the fundamental thermionic limit of the subthreshold slope of a metal–oxide–semiconductor field-effect transistor (MOSFET) at 60 mV dec−1 at room temperature and therefore precludes lowering of the supply voltage and overall power consumption1,2. Adding a ferroelectric negative capacitor to the gate stack of a MOSFET may offer a promising solution to bypassing this fundamental barrier3. Meanwhile, two-dimensional semiconductors such as atomically thin transition-metal dichalcogenides, due to their low dielectric constant and ease of integration into a junctionless transistor topology, offer enhanced electrostatic control of the channel4,5,6,7,8,9,10,11,12. Here, we combine these two advantages and demonstrate a molybdenum disulfide (MoS2) two-dimensional steep-slope transistor with a ferroelectric hafnium zirconium oxide layer in the gate dielectric stack. This device exhibits excellent performance in both on and off states, with a maximum drain current of 510 μA μm−1 and a sub-thermionic subthreshold slope, and is essentially hysteresis-free. Negative differential resistance was observed at room temperature in the MoS2 negative-capacitance FETs as the result of negative capacitance due to the negative drain-induced barrier lowering. A high on-current-induced self-heating effect was also observed and studied.

Access optionsAccess options

Rent or Buy article

Get time limited or full article access on ReadCube.


All prices are NET prices.

Additional information

Publisher’s note: Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.


  1. 1.

    Ionescu, A. M. & Riel, H. Tunnel field-effect transistors as energy-efficient electronic switches. Nature 479, 329–337 (2011).

  2. 2.

    Sze, S. M. & Ng, K. Physics of Semiconductor Devices 3rd edn (Wiley, Hoboken, New Jersey, 2008).

  3. 3.

    Salahuddin, S. & Datta, S. Use of negative capacitance to provide voltage amplification for low power nanoscale devices. Nano Lett. 8, 405–410 (2008).

  4. 4.

    Radisavljevic, B., Radenovic, A., Brivio, J., Giacometti, V. & Kis, A. Single-layer MoS2 transistors. Nature Nanotech. 6, 147–150 (2011).

  5. 5.

    Liu, H., Neal, A. T. & Ye, P. D. Channel length scaling of MoS2 MOSFETs. ACS Nano 6, 8563–8569 (2012).

  6. 6.

    Das, S., Chen, H.-Y., Penumatcha, A. V. & Appenzeller, J. High performance multilayer MoS2 transistors with scandium contacts. Nano Lett. 13, 100–105 (2013).

  7. 7.

    Wang, H. et al. Integrated circuits based on bilayer MoS2 transistors. Nano Lett. 12, 4674–4680 (2012).

  8. 8.

    Desai, S. B. et al. MoS2 transistors with 1-nanometer gate lengths. Science 354, 99–102 (2016).

  9. 9.

    English, C. D., Shine, G., Dorgan, V. E., Saraswat, K. C. & Pop, E. Improved contacts to MoS2 transistors by ultra-high vacuum metal deposition. Nano Lett. 16, 3824–3830 (2016).

  10. 10.

    Liu, Y. et al. Pushing the performance limit of sub-100 nm molybdenum disulfide transistors. Nano Lett. 16, 6337–6342 (2016).

  11. 11.

    Yang, L. et al. Chloride molecular doping technique on 2D materials: WS2 and MoS2. Nano Lett. 14, 6275–6280 (2014).

  12. 12.

    Liu, L., Lu, Y. & Guo, J. On monolayer MoS2 field-effect transistors at the scaling limit. IEEE Trans. Electron. Dev. 60, 4133–4139 (2013).

  13. 13.

    Gopalakrishnan, K., Griffin, P. B. & Plummer, J. D. I-MOS: a novel semiconductor device with a subthreshold slope lower than kT/q. Proc. IEEE Int. Electron. Dev. Meet. 289–292 (2002).

  14. 14.

    Appenzeller, J., Lin, Y.-M., Knoch, J. & Avouris, P. Band-to-band tunneling in carbon nanotube field-effect transistors. Phys. Rev. Lett. 93, 196805 (2004).

  15. 15.

    Sarkar, D. et al. A subthermionic tunnel field-effect transistor with an atomically thin channel. Nature 526, 91–95 (2015).

  16. 16.

    Abele, N. et al. Suspended-gate MOSFET: bringing new MEMS functionality into solid-state MOS transistor. Proc. IEEE Int. Electron. Dev. Meet. 479–481 (2005).

  17. 17.

    Dubourdieu, C. et al. Switching of ferroelectric polarization in epitaxial BaTiO3 films on silicon without a conducting bottom electrode. Nature Nanotech. 8, 748–754 (2013).

  18. 18.

    Jain, A. & Alam, M. A. Stability constraints define the minimum subthreshold swing of a negative capacitance field-effect transistor. IEEE Trans. Electron. Dev. 61, 2235–2242 (2014).

  19. 19.

    Khan, A. I. et al. Negative capacitance in a ferroelectric capacitor. Nat. Mater. 14, 182–186 (2015).

  20. 20.

    Zubko, P. et al. Negative capacitance in multidomain ferroelectric superlattices. Nature 534, 524–528 (2016).

  21. 21.

    McGuire, F. A., Cheng, Z., Price, K. & Franklin, A. D. Sub-60 mV/decade switching in 2D negative capacitance field-effect transistors with integrated ferroelectric polymer. Appl. Phys. Lett. 109, 093101 (2016).

  22. 22.

    Wang, X. et al. Ultrasensitive and broadband MoS2 photodetector driven by ferroelectrics. Adv. Mater. 27, 6575–6581 (2015).

  23. 23.

    Salvatore, G. A., Bouvet, D. & Ionescu, A. M. Demonstration of subthreshold swing smaller than 60 mV/decade in Fe-FET with P(VDF-TrFE)/SiO2 gate stack. Proc. IEEE Int. Electron. Dev. Meet. 167–170 (2008).

  24. 24.

    Muller, J. et al. Ferroelectricity in simple binary ZrO2 and HfO2. Nano Lett. 12, 4318–4323 (2012).

  25. 25.

    Cheng, C. H. & Chin, A. Low-voltage steep turn-on pMOSFET using ferroelectric high-κ gate dielectric. IEEE Electron. Dev. Lett. 35, 274–276 (2014).

  26. 26.

    Lee, M. H. et al. Prospects for ferroelectric HfZrO x FETs with experimentally CET = 0.98 nm, SSfor = 42 mV/dec, SSrev = 28 mV/dec, switch-off <0.2V, and hysteresis-free strategies. Proc. IEEE Int. Electron. Dev. Meet. 616–619 (2015).

  27. 27.

    Zhou, J. et al. Ferroelectric HfZrO x Ge and GeSn PMOSFETs with sub-60 mV/decade subthreshold swing, negligible hysteresis, and improved IDS. Proc. IEEE Int. Electron. Dev. Meet. 310–313 (2016).

  28. 28.

    Li, K. S. et al. Sub-60mV-swing negative-capacitance FinFET without hysteresis. Proc. IEEE Int. Electron. Dev. Meet. 620–623 (2015).

  29. 29.

    Ota, H. et al. Fully coupled 3-D device simulation of negative capacitance FinFETs for sub 10 nm integration. Proc. IEEE Int. Electron. Dev. Meet. 318–321 (2016).

  30. 30

    McGuire, F. A. et al. Sustained sub-60 mV/decade switching via the negative capacitance effect in MoS transistors. Nano Lett. 17, 4801–4806 (2017).

Download references


This material is based upon work partly supported by the Air Force Office of Scientific Research (AFOSR)/National Science Foundation (NSF) Two-Dimensional Atomic-layer Research and Engineering (2DARE) programme, Army Research Office (ARO) and Semiconductor Research Corporation (SRC).

Author information


  1. School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, 47907, USA

    • Mengwei Si
    • , Chunsheng Jiang
    • , Nathan J. Conrad
    • , Hong Zhou
    • , Kerry D. Maize
    • , Gang Qiu
    • , Ali Shakouri
    • , Muhammad A. Alam
    •  & Peide D. Ye
  2. Birck Nanotechnology Center, Purdue University, West Lafayette, IN, 47907, USA

    • Mengwei Si
    • , Nathan J. Conrad
    • , Hong Zhou
    • , Kerry D. Maize
    • , Gang Qiu
    • , Ali Shakouri
    •  & Peide D. Ye
  3. National Nano Device Laboratories, Hsinchu, 300, Taiwan

    • Chun-Jung Su
    •  & Chien-Ting Wu
  4. Tsinghua National Laboratory for Information Science and Technology, Institute of Microelectronics, Tsinghua University, Beijing, 100084, China

    • Chunsheng Jiang


  1. Search for Mengwei Si in:

  2. Search for Chun-Jung Su in:

  3. Search for Chunsheng Jiang in:

  4. Search for Nathan J. Conrad in:

  5. Search for Hong Zhou in:

  6. Search for Kerry D. Maize in:

  7. Search for Gang Qiu in:

  8. Search for Chien-Ting Wu in:

  9. Search for Ali Shakouri in:

  10. Search for Muhammad A. Alam in:

  11. Search for Peide D. Ye in:


P.D.Y. conceived the idea and supervised the experiments. C.J.S. performed the ALD of HZO and Al2O3 and dielectric physical analysis. M.S. performed the device fabrication, d.c. and C–V measurements, and data analysis. M.S. and N.J.C. carried out the fast IV measurement. M.S. and G.Q. performed the AFM measurement. H.Z., K.D.M. and A.S. did the thermo-reflectance imaging. G.Q. performed the Raman and photoluminescence experiment. C.T.W. conducted TEM and EDS analyses. C.J. and A.M.A. conducted the theoretical calculations and analysis. M.S., A.M.A. and P.D.Y. summarized the manuscript and all authors commented on it.

Competing financial interests

The authors declare no competing financial interests.

Corresponding author

Correspondence to Peide D. Ye.

Supplementary information

  1. Supplementary Information

    Steep Slope Hysteresis-free Negative Capacitance MoS2 Transistors.

About this article

Publication history




Issue Date



Further reading