The semiconductor–electrolyte interface dominates the behaviours of semiconductor electrocatalysis, which has been modelled as a Schottky-analogue junction according to classical electron transfer theories. However, this model cannot be used to explain the extremely high carrier accumulations in ultrathin semiconductor catalysis observed in our work. Inspired by the recently developed ion-controlled electronics, we revisit the semiconductor–electrolyte interface and unravel a universal self-gating phenomenon through microcell-based in situ electronic/electrochemical measurements to clarify the electronic-conduction modulation of semiconductors during the electrocatalytic reaction. We then demonstrate that the type of semiconductor catalyst strongly correlates with their electrocatalysis; that is, n-type semiconductor catalysts favour cathodic reactions such as the hydrogen evolution reaction, p-type ones prefer anodic reactions such as the oxygen evolution reaction and bipolar ones tend to perform both anodic and cathodic reactions. Our study provides new insight into the electronic origin of the semiconductor–electrolyte interface during electrocatalysis, paving the way for designing high-performance semiconductor catalysts.
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The data that support the findings of this study are available from the corresponding author on reasonable request.
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This work was supported by MOE under AcRF Tier 1 (M4011782.070 RG4/17 and M4011993.070 RG7/18), AcRF Tier 2 (2015-T2-2-007, 2016-T2-1-131, 2016-T2-2-153 and 2017-T2-2-136) and AcRF Tier 3 (2018-T3-1-002), and the A*Star QTE programme. This work was also supported by MOE under AcRF Tier 1 (2016-T1-002-051, 2017-T1-001-150 and 2017-T1-002-119) and AcRF Tier 2 (2015-T2-2-057, 2016-T2-2-103 and 2017-T2-1-162), and by NTU under Start-Up Grant M4081296.070.500000 in Singapore. H.Z. acknowledges support from ITC via the Hong Kong Branch of National Precious Metals Material Engineering Research Center and a Start-Up Grant from City University of Hong Kong. The authors acknowledge the Facility for Analysis, Characterization, Testing and Simulation, Nanyang Technological University, Singapore for use of their electron microscopy facilities. Q.J.W. acknowledges the support of the Ministry of Education Singapore Grant (MOE2016-T2-1-128) and National Research Foundation–Competitive Research Program (NRF-CRP18-2017-02). Z.Z. acknowledges the support from NSFC (11772153). Z.W.S. acknowledges support from the Institute of Materials Research and Engineering, A*STAR (IMRE/17-1R1211). Work at Rice was supported by the US ARO Grant W911NF-16-1-0255. The authors thank Z.J. Xu for discussions about surface conductance and L. Han, J.R. Galan-Mascaros (Institute of Chemical Research of Catalonia) and P. Tang (Catalonia Institute for Energy Research) for discussions about EIS. The authors also thank Y. Liu (Hunan University) for discussions about the semiconductor electronic device and S. Teddy for XPS measurements and data analysis.
The authors declare no competing interests.
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Supplementary methods, Supplementary Figs. 1–25, Supplementary notes 1–6, Supplementary Tables 1–4, Supplementary references 1–152