Pipeline quantum processor architecture for silicon spin qubits

Noisy intermediate-scale quantum (NISQ) devices seek to achieve quantum advantage over classical systems without the use of full quantum error correction. We propose a NISQ processor architecture using a qubit `pipeline' in which all run-time control is applied globally, reducing the required number and complexity of control and interconnect resources. This is achieved by progressing qubit states through a layered physical array of structures which realise single and two-qubit gates. Such an approach lends itself to NISQ applications such as variational quantum eigensolvers which require numerous repetitions of the same calculation, or small variations thereof. In exchange for simplifying run-time control, a larger number of physical structures is required for shuttling the qubits as the circuit depth now corresponds to an array of physical structures. However, qubit states can be `pipelined' densely through the arrays for repeated runs to make more efficient use of physical resources. We describe how the qubit pipeline can be implemented in a silicon spin-qubit platform, to which it is well suited to due to the high qubit density and scalability. In this implementation, we describe the physical realisation of single and two qubit gates which represent a universal gate set that can achieve fidelities of $\mathcal{F} \geq 0.9999$, even under typical qubit frequency variations.


I. INTRODUCTION
Fault-tolerant quantum computers offer profound computational speed-ups across diverse applications, but are challenging to build.However, even in the near term without full error correction, quantum computers have the potential to offer improvements over classical computing approaches in run time scaling [1] and energy consumption for certain tasks [2].There is a rich and diverse array of schemes for realising quantum computation, each formally equivalent in computational power [3][4][5], with important differences with regards to practical realisations.In the gate-based approach, a quantum algorithm is expressed as a quantum circuit consisting of a series of quantum logic gates.Typically, such gates are applied to a stationary array of qubits (for example through electromagnetic waves or optical pulses), relying on the delivery of a complex series of accurate, quasi-simultaneous control pulses to each qubit.This can lead to practical challenges ranging from cross-talk in the control pulses between nearby qubits [6,7] to increased demands on digital-to-analogue converters (DACs) particularly when fully integrating control systems with a cryogenic quantum chip.
To mitigate the practical challenges associated with high-density control electronics, global qubit control schemes have been explored [8][9][10].However, these approaches require a precision in the position and homogeneity of qubit structures, as well as the control pulses, to a degree that is technically challenging with available technology.Alternatively, local addressing can be used to bring qubits into resonance with globally applied control fields to create an effective local control [11,12].However, this approach still requires fast run-time control for the addressing [13].A second strategy is to accept the cost of a much lower effective qubit density in exchange for mitigating effects such as cross-talk -in such a distributed model of quantum computing [14] qubits, or small qubit registers, are well-separated and interfaced by a common entangling (typically photonic) mode.While such hybrid matter/photon systems have been successfully realised in several platforms [15][16][17], high gate speeds compatible with the demands of NISQ algorithms [18] may be difficult to achieve.
A further consideration when designing NISQ hardware architectures is that NISQ algorithms based on (e.g.) variational approaches [18,19] require multiple repetitions of the same quantum circuit -or simple variations thereof -to be performed.In turn this requires identical, or similar, sequences of local control fields to be repetitively applied to the qubits, presenting an opportunity for more efficient hardware implementations.In this Article, we propose a quantum computing architecture for implementing quantum circuits in which all runtime control is applied globally, and local quantum operations such as 1-qubit (1Q) and 2-qubit (2Q) gates are 'programmed' into the array in advance.This is achieved by shuttling qubit states through a grid of gated structures which have been electronically configured to realise specific gates.
In such an approach, each layer of gates in the original quantum circuit corresponds to a one-dimensional array of structures, such that the scheme is more demanding in terms of physical resources on a chip for confining qubits.However, when applying multiple repetitions of the same circuit by pipelining -i.e.running distinct, staggered layers of qubits through the array simultaneously -the physical resource efficiency becomes broadly equivalent arXiv:2306.07673v1[quant-ph] 13 Jun 2023 to more conventional approaches, combined with potential practical benefits.
Below, we introduce the concept of a qubit pipeline in more detail in Sec.II, before focusing on a potential implementation for the silicon metal-oxide-semiconductor (SiMOS) electron spin qubit platform in Sec III.We then estimate the expected improvement in run time for an example algorithm in Sec.IV.In particular, in Sec.III A, we outline a scheme for synchronous shuttling, and in Sec.III B, we discuss initialisation, readout, and parallelised pre-configuration, mostly outlining established methods.In Sections III C-III E, we show how to realise an universal gate set for the pipeline in the silicon electron spin platform including: single-qubit Zrotations using local, voltage-controllable g-factor Stark shifts, globally-applied √ X operations enabled by B 1drive frequency binning and 2Q SWAP-rotation gates using the native interaction of nearest neighbour exchange.Each of the above gate implementations is designed to accommodate natural variations, such as random g-factor differences, across the QDs while enabling synchronized operation and thus fixed gate times.

II. QUBIT PIPELINE
For solid-state quantum processors the qubit array may consist of a two-dimensional lattice with nearestneighbour couplings (see Fig. 1(a)).The qubit pipeline approach replaces the two-dimensional lattice of stationary qubits with an N ×D grid (see Fig. 1(b)), such that N qubits are arranged in a one-dimensional array and propagate through the grid to perform a quantum circuit of depth D. Each column therefore represents a single 'time step' of quantum logic gates in the corresponding quantum circuit while each row of structures forms a 'pipe' of computational length D along which a qubit travels.Multiple qubits can simultaneously travel through each pipe, at different stages, in order to more efficiently use the physical resource.
Run-time operation begins by initializing a onedimensional array of N qubit states on the input edge.This initialised array is synchronously pushed through D structures that have been preconfigured to perform the single-and two-qubit gates in the desired quantum circuit.Qubit states are read out on the opposite output edge.Between initialization and readout, operations on the qubit array alternate between synchronous one-and two-qubit gate steps and shuttling steps.Figures 1 (c)-(f ) illustrate the equivalence between an example quantum circuit (Fig. 1 (c)) and time-evolution on the qubit pipeline (Figs. 1 (d)-(f )).In this way, local qubit control of the typical qubit grid is replaced by a combination of global control (at least, with widely shared control lines) to push the qubit states from start to finish, combined with quasi-statically tuneable elements within the larger number of physical structures used to define the quantum circuit prior to running it.
We assume that while the parameters of the quantum logic gates can be tuned in-situ (e.g.electrically), the type of gate performed in each cell of the array is defined when fabricating the quantum processor.Indeed, though more generally reconfigurable implementations may be possible (see e.g.Supplementary Sec. S 1) and offer potential efficiencies, a suitably chosen pattern of gates is sufficient for universal quantum computation, subject only to the constraints of the qubit number and circuit depth.Assuming the quantum processor is restricted to a twodimensional topology, the pipeline approach presented here is limited to a linear qubit array.Many quantum algorithms can be mapped onto such a linear array without significant loss of efficiency, such as the variational quantum eigensolver for the Fermi-Hubbard model, a promising task that could be implemented on NISQ hardware [18][19][20][21].
Conventional approaches to operate an N qubit processor with tuneable nearest neighbour couplings demand at least O(N ) fast signal generators for single-qubit control, for qubit-qubit couplings, and for state readout.In contrast, the pipeline scheme presented here may require a constant (even just one) number of fast pulse generators, utilized for shuttling the qubit states through the grid in a manner analogous to a charge-coupled device.For example, three waveforms biasing columns d mod 3 = 0, d mod 3 = 1, and d mod 3 = 2, create a local potential minimum for a qubit which can then be driven forward through the array [22].Implementing such a shuttling scheme, synchronicity is achieved if gate steps take an equal amount of time for all qubits.For example, for logic gates expressed as exp(−iωτ σ) for some single-or two-qubit operator σ, we fix a common τ but select ω to control the amount of rotation and thus distinguish the logic operations.The gate speed ω is varied using parameters such as dc gate voltages and magnetic field amplitudes at the preconfiguration stage.In principle, different columns of gates (e.g.all single-qubit gates, or all two-qubit gates) could have different durations, at the cost of a more complex shuttling pulse sequence.The three-column approach to shuttling represents the maximum density with which different sets of qubits can be pipelined through the circuit.
Due to the statistical nature of measurement in quantum mechanics, several types of quantum algorithms, such as those that yield an expectation value following some quantum circuit [23,24], must be run a large number of times to obtain a meaningful result.Such algorithms are well-suited to the pipeline approach as multiple, independent qubit arrays can be pushed through the pipeline simultaneously, enabling multiple circuit runs in parallel.The maximum density of independent logical instances of a quantum circuit which can be pipelined through the structure is determined by the physical constraints of ensuring forward shuttling and avoiding unwanted interactions between qubits.Furthermore, if the duration of either the initialisation or readout stage is greater than that of the 1Q/2Q gates, this density must

Lattice Pipeline
Processor size

Runtime scaling
DNr D + Nr Table I.Comparison between the quantum lattice and the pipeline processors.Here, N is the number of qubits, D is the maximum circuit depth, and Nr is the number of repetitions.
be further reduced.Exploiting such pipelining, the algorithm runtime is proportional to (D + N r )τ instead of DN r τ , providing a significant speedup for circuits with large number of repetitions N r , or large depths.Here, τ is the timescale of the longest operation: a qubit gate, readout, or initialization.Table I summarises these main differences between a qubit lattice and the qubit pipeline.

III. IMPLEMENTATION WITH SILICON QUANTUM DOTS
We now analyse a hardware implementation wellsuited to the qubit pipeline paradigm, i.e. qubits based on single electron spins trapped in silicon-based QDs.Silicon spin qubits can achieve high density due to their small footprint of O(50 × 50 nm 2 ), and can leverage the state-of-the-art nanoscale complementary metal-oxidesemiconductor (CMOS) manufacturing technology used in microprocessors [7,[25][26][27].Quasi-CMOS-compatible electron spin qubits can be patterned as gated planar MOS devices [28][29][30], confining electrons at the Si-SiO 2 interface below the gates, or using Si/SiGe heterostructures [30,31].Typical values for single-and two-qubit gate fidelities measured so far in such systems include 99.96% and 99.48% in SiMOS [32,33] and 99.9% and 99.5% in Si/SiGe [31,34,35].Coherent spin shuttling has been demonstrated at a transfer fidelity of 99.97% for spin eigenstates, and 98% for spinsuperposition states [36,37], while SWAP gates have also be shown to transport arbitrary qubit states with fidelity up to 84% [38].In addition, silicon on insulator (SOI) nanowire and fin field-effect transistors (nwFET and fin-FET) devices [39][40][41] have been used to confine spin qubits within etched silicon structures, and have been proposed for sparsely-connected two-dimensional qubit architectures [42].These devices typically show a large electrostatic gate control of the QDs (larger so-called lever arms α) which is advantageous for reflectometry readout techniques, or spin-photon coupling [43,44].
To realise the qubit pipeline, we propose a sparse twodimensional quantum dot(QD) array, which we refer to as a nanogrid (see Fig. 2 (a)).The nanogrid is a weaved grid of silicon 'channels' in which QDs can be formed (e.g.etched silicon in the case of nwFET and finFET approaches, or through confining depletion gates in the case of planar MOS).Metal gates (green and orange shapes) for forming QDs are placed along and over the exposed Si to form locally one-dimensional QD arrays,  which make 90-degree angles at T-junctions to join neighbouring pipes.Such weaving is required for entangling all the qubits from different pipes.Extra control from a second gate layer aids tuning all QDs to nominally identical setpoints despite variability in e.g.charging energies [45,46].The metal gates are routed with vias.The overall architecture can be realised in a variety of silicon QD platforms, including planar MOS, SOI, and finFETs, with cross-sections illustrated in Figures 2 (b)-(d).In addition, a similar layout can be used in a Si/SiGe architecture or indeed other types of electron or hole semiconductor spin qubits.

A. Shuttling
In the qubit pipeline, we shuttle electrons between different columns d where logical 1Q and 2Q gate operations are performed.Electrons can be shuttled from one QD to another by inverting the biasing between gates, i.e. by pulsing over the inter-dot charge transition with DQD charge occupancies (1, 0) → (0, 1) [47][48][49].This scheme is also referred to as bucket-brigade shuttling.
The shuttling time τ s is determined by the inter-site tunnel coupling frequency t ij /h (typically 1 − 20 GHz in two-layer QD arrays using barrier gates [48]) and the electron temperature, which affects charge relaxation rates.Charge shuttling errors are expected to be minimized when the pulsing rate is slow compared to the inter-dot tunnel coupling [36,50], where non-adiabatic Landau-Zener (LZ) transitions are minimal.At tunnel coupling t ij /h = 20 GHz, the ramp can be performed adiabatically (P LZ < 10 −4 ) with shuttling times of 9.1 ns or more (see Supplementary Sec. S 2 a).Electron charges and spins have been demonstrated to shuttle reliably over these timescales [36,50], so we take 10 ns as the range of target shuttling times τ s .The exact shuttling time should be determined to avoid LZ transitions to excited states, such as valley-orbit states.The systematic Z-phases arising from g-factor differences between sites can be accounted for as part of single-qubit control, as discussed in Sec.III C.
The pulse sequence depicted in Fig. 2 (e) can realise the shuttling and logic gate dynamics modulation.To this end, each gate is routed to an ac + dc voltage combining circuit.The ac nodes from gates from a single column, and mod 5 steps, are combined at interconnect level with a power splitter, whereas each gate receives an individual dc bias.Bias tees at gate nodes enable applying dc biases from individual dc sources.See Supplementary Sec. S 2 b for footprint estimates.As there are signals with three different periods, we could employ e.g.phase modulation or partially digital signal processing to generate the five shuttling biases, and hence shuttling biases for the entire pipeline with only three voltage pulse generators.We can fill the pipeline up to every fifth physical gate column of QDs single electrons, which we refer to as maximal filling.

B. Initialization, readout and pre-configuration
Initialisation and readout is analogous to a shift register for single-electron spins, where electrons are moved through a pipe and electron reservoirs are located at the input and output ends of the array.Preconfiguration of the unit cells can be done locally, utilizing initialization and readout nodes like the one depicted in Fig. 2 (f ).Logical ground states |↓ q ⟩ are initialised using spindependent reservoir-to-dot tunneling [51].The fidelity is typically determined by the relative magnitude of the spin Zeeman energy splitting and k B T where T is the temperature of the electron reservoirs and k B is Boltz-mann's constant.For example, at B 0 = 1 T, F 0.9999 at T ≲ 73 mK.The initialization time is determined by the reservoir-to-dot tunnelling time 1/Γ ψR , which can be controlled with a barrier gate, and can reach tens of GHz [52].At higher electron reservoir temperatures, required fidelities could be obtained using real-time monitoring of the qubit through a negative-result measurement at the expense of longer initialization times [53].
For readout, we employ the so-called Elzerman readout, where we detect spin states using the reverse of the spin-dependent tunneling described above, detected by a capacitively-coupled charge sensor, such as a singleelectron box [54,55], at site ϕ (see Fig. 2 (f )).This method is estimated to yield a spin readout fidelity F 0.993 in 4 µs [52], while advances in resonant readout techniques could help increase F 0.9999 in 50 ns [56].We utilize Elzerman readout over Pauli spin blockade or parity readout, which are based on projections in the singlet-triplet basis, since we prefer to operate at relatively high B 0 fields, B 0 ≈ 1 T.

C. Z -rotation gates with Stark-shifted g-factors
The electron spin g-factor g * , which defines the Larmor frequency ω 0 = g * µ B B 0 /ℏ (where µ B is the Bohr magneton and B 0 the applied dc magnetic field) can be shifted using electric fields from gate voltages.In SiMOS heterostructures the dominant Stark shift is understood to arise from wavefunction displacement with respect to the Si/SiO 2 interface [57].Linear or quasi-linear shifts δg q (V ) with ∂g/∂E z (V ) = ±(1-5) × 10 −3 (MV/m) −1 have been reported for QDs in planar MOS devices [29,58,59] with an in-plane magnetic field and E z applied perpendicular to the interface.The sign of the shift depends on the valley state of the electron [57,58].The roughness of the Si/SiO 2 interface also introduces some random contribution G q to the effective g-factor, which can be larger than the tuneability, G q = ±O(10 −3 ...10 −2 ) [59].Hence, the g-factor of a spin at some site q can be considered as a combination of these shifts on some intrinsic value, g Si , such that g * q = g Si + G q + δg q (V ).In the following, we assume g Si = 2.0.
We use the gate-voltage controllable g-factor Stark shift to perform relative single-qubit Z(ϕ q ) = e −iϕqσz/2 gates by synchronously shuttling the qubit onto a QD structure (see columns d + 1 and d + 3 in Fig. 2 (a)) with predetermined dc gate voltages.Spins encoding the qubit state remain at the same site for a fixed time τ 1Q to acquire some phase (relative to a spin with g = g Si ) before synchronously shuttling forward.The gate Z(ϕ q ) is achieved by selecting a suitable g-factor shift (1) Here, r q ∈ [0, 1) is selected from G q µ B B 0 τ 1Q ℏ −1 := 2π(n q + r q ), for n q ∈ Z. Since we only require phase matching up to 2π, the site-to-site randomness G q only contributes via 2πr q , which remains in the same order of magnitude for any G q .As a result, the randomness does not affect the required tuneability to attain a rotation angle over a target gate time.Similarly, systematic phase shifts arising from the other QDs involved in shuttling can be accounted for as an effective contribution to G q and corrected in the same way.The order of magnitude of δg q (V ) required to generate a π phase shift at varying τ 1Q and B 0 is plotted in Fig. 3 (a), where we take G q = 0 for simplicity.Tunabilities of at least δg ≈ ±3.6 × 10 −5 and δg ≈ ±3.6 × 10 −4 are required at B 0 = 1 T for τ 1Q = 1 µs and τ 1Q = 0.1 µs, respectively.
To realise such Stark shifts, we propose to employ the plunger gate as the g-factor tuning gate, and a neighbouring gate as a µ-compensating gate (gate labelled with µ in Fig. 3 (b)).This additional compensating gate is required to ensure the electrochemical potentials (see Supplementary Sec. S 3, Eqs.S1-S2), and hence QD electron occupancies remain correct under the applied electric field for g-factor tuning, as illustrated in the triple QD stability diagrams shown in Figs. 3 (c)-(d).In planar MOS, the plunger gate contributes dominantly to E z , while the µcompensating gate E-field mostly to E x , at site q, having negligible effect on the g-factor.In etched silicon devices, due to two facets of Si/SiO 2 interface (Fig. 2 (f )), we expect both split gates to contribute to the Stark shift, but as long as the effects of the two gates to the g-factor Stark shift and the electrochemical potential shift are asymmetric, the pair of gates allows to compensate for the shift in the electrochemical potential.
Analytical estimates for the E-field derivatives ∂E z /∂V j and ∂E x /∂V j due to the plunger and µcompensating voltages V q and V µ , as a function of longitudinal position x, close to the MOS interface, are plotted in Fig. 3 (e), with simulation details given in Supplementary Sec. S 3. The estimated values of the E z -gradient at site q, together with a conservative figure of ∂g/∂E z = ±1 × 10 −3 (MV/m) −1 suggest a required voltage shift dV q = 615 V × δg q .For example, a target Stark shift δg π = ±3.6 × 10 −5 , would require the dc bias on the gate to be shifted dV q = ±22 mV.The corresponding change in µ q can be compensated with the µ-compensating gate, by setting the voltage dV µ ≈ −α qq /α qµ dV q , where α ij is the lever arm between QD at site i and gate j (see Supplementary Sec. S 3).
We evaluate the sensitivity of this Z(ϕ q ) gate to noise using the so-called process fidelity [60] between an ideal and a noisy unitary gate, for the case of τ 1Q = 1.0 µs and B 0 = 1.0 T. We sample a value for G q from a normal distribution with width σ G set to 10 −3 g Si , and use it to find δg q (Eq.( 1)) to hit ϕ q = π for an ideal gate.For the noisy gate, we consider shuttling time errors of magnitude δτ that lead to gate time errors, and fluctuations in the gate voltage, δV q , which lead to impacts in the g-factor according to δg q = δV q /615 V.These noise contributions δτ and δV q are also sampled from normal distributions with varying widths of σ τ and σ V , respectively.
In Fig. 3 (f ), we plot the resulting Z(π) fidelities, μ q (a) (b) Gate layout realisation of the g-factor tuning scheme with shuttling through quantum dots under gates q − 1, to q, and to q + 1.The voltage Vq is used to tune the g-factor at site q, while the voltage Vµ is used to compensate for the change in the electrochemical potential due to the g-factor tuning.(c)-(d) Overlaid stability diagrams of the (q − 1, q, q + 1) triple quantum dot at the start and end (blue lines), and at the middle (red lines) of the shuttling sequence, illustrate the requirement for electrochemical potential compensation.Using a waveform as shown in Fig. 2 ( averaged over 1000 samples at each pair of noise levels.We find that the noise sources for the gate time and g-tuning errors add up independently.Noise levels of σ τ ≲ 0.08 ns, i.e. ∼ 10 −2 τ s for the target shuttling time of τ s = 10 ns, and σ V ≲ 100 µV are required to achieve F Z(ϕ q ) 0.9999.Charge noise acts equivalently to gate voltage fluctuations.Based on state-of-the art charge noise spectral densities in industrial SiMOS devices [41,61,62], we would expect voltage fluctuations of σ V ≈ 30...90 µV over a bandwidth of 1 Hz − 1 GHz, which is sufficient for our fidelity requirements, whereas there is less experimental data available on timing errors in shuttling.

D. Two-qubit gate family with gate-voltage-tuneable exchange strength
To perform two-qubit operations, qubits are shuttled to neighbouring sites that connect adjacent pipes, in order to introduce an exchange interaction whose strength, J ij , can be estimated by ( Here, ϵ(t) is the detuning of the single-particle level spacings proportional to chemical potentials and ∆K is the difference between the on-site and inter-site charging energies.J ij can thus be in-situ modulated by the detuning using the plunger gates, or the tunnel coupling using the barrier gates.Both knobs can modulate the exchange strength over several order of magnitude.We choose to use module the tunnel coupling to allow us to operate in the centre of the (1, 1) charge configuration, where charge noise is minimised [63,64].
In the logic basis , the interaction between two exchange-coupled spins with a Zeeman energy difference ∆E Z (see Supplementary Sec. S 4 a, Eq. (S8)) generates time-evolution which is analogous to the single-qubit semiclassical Rabi dynamics in the m z = 0 subspace, while the decoupled m z = ±1 subspaces merely acquire phases according to their Larmor frequencies (see Supplementary Sec. S 4 b, Eq. (S14)).In this analogy, within the m z = 0 subspace, ∆ ij := ∆E Z + (J i − J j )/2 ≈ ∆E Z (also see Supplementary Sec. S 4 a) corresponds to the qubit-drive detuning, J ij to the transversal coupling strength, and to the Rabi frequency.This time evolution is our native two-qubit operation.Figure 4 (a)-(d) illustrates some circuit identities obtained from it.To classify these operations, we may rep- resent the unitary operation with two angle variables, as Here, the angle ϕ = τ 2Q /Ω ij is set by the gate time τ 2Q and the frequency Ω ij .The angle χ = arctan(x) is set by the ratio x = ∆ ij /J ij .This ratio is related to the singlequbit analogue of the B 1 polar angle arccos(∆ ij /Ω ij ) via arccos(∆ ij /Ω ij ) = arccot(x).We also have ϕ Z = (E Z +∆E Z )ϕ/Ω ij , and α(ϕ, χ) = ϕ cos(χ).When x → 0, coinciding with negligible Zeeman energy differences, the native operation (3) reduces to the SWAP-rotation with the rotation angle given by ϕ (viewed from the frame from which E Z = 0).But even in the presence of ∆E Z , the native operation (3) can be used to realise several familiar two-qubit operations.One way to engineer desired gates starts by considering interaction times that correspond to particular numbers of completed rotations with respect to the single-qubit analogue of the Rabi frequency.In doing so, are left to fix χ to define the operation.Since we largely do not control the Zeeman energy difference, we choose the polar angle analogue with J ij .By choosing ϕ = π + 2πn, we realise the diagonal two-qubit phase gates [65], as where we have defined ϕ 11 = −ϕ Z − α(ϕ, χ), and The circuits are visualised in Fig. 4 (a)-(b).See Supplementary Sec. S 5 for their matrix representations.These gates are maximally entangling (for certain rotation angles), but e.g. the SWAP gate, or any non-diagonal gate using just phase gates and single-qubit Z-rotations is not possible.In general, a larger set of gates allows more efficient decompositions for algorithms.For example, the variational eigensolvers for the Fermi-Hubbard model natively decompose into SWAP-rotations and single-qubit Z-rotations, so we show how to construct the SWAProtation from the native operation.By instead choosing ϕ = π/2 + 2πn, we obtain a gate close to the so-called Givens rotation (see Supplementary Sec. S 5, Eq. (S24)), as The circuit identity is illustrated in Fig. 4 (c).The angle of the Givens rotation is controllable with the polar angle analogue, although not all rotation angles are attainable equally easily.In particular, rotation angles of 0 and π/2 would require negligible Zeeman energy difference or exchange strength, respectively.However, these cases are not interesting, since in the absence of Zeeman energy differences, we may employ a SWAP-rotation gate, and in the absence of an interaction the operation is nonentangling.
The rotation angle χ = ±π/4 corresponds to the case where the (absolute value of the) Zeeman energy difference is equal to the exchange strength.Here, the m z = 0 matrix elements simplify to |U Nat (ϵ, π/2, π/4 The native operation U Nat (ϵ, π/2, π/4) thus acts as a controlled Hadamard operation for the m z = 0 subspace.The operation can be used to convert single-qubit Z(θ)rotations into SWAP-rotations, as The circuit is illustrated in Fig. 4 (d).We have written the circuit identity using the Ising gate for clarity, but in realising it using Eq. ( 5), we may absorb the Z-rotations into the final step, reducing physical gates from 6 to 5.
It provides an exact method to perform SWAP-rotation operations, including the non-entangling SWAP gate, in the presence of Zeeman energy differences.The fidelity of this operation does not depend on the magnitude of ∆E Z (as long as an equally large exchange strength is attainable), which means that the gate decomposition can be used with e.g.micromagnets, with which ∆E Z = O(1 − 10 GHz) [38].
The strategy for choosing parameters for the ϕ = π/2 + 2πn operation is as follows (also see Supplementary Sec. S 6 for further details).Knowing ∆E Z , we set J ij = |∆E Z |.We are required to set the gate time, as τ = (π/2 + 2πn)/( √ 2J ij ).The gate time is limited by a minimum set by ∆E Z , and a resolution 2πn/( √ 2J ij ), but we may use g-factor tuneability at QD j for fine-tuning τ (after which J ij is recalculated).Smaller g-factor tuneability then requires a longer gate time to minimise gate time errors.For example, setting the target gate time and rotation angle, as τ = 1 µs, and χ = π/4, respectively, and assuming ∆K = 1 meV, σ G = 10 −3 g Si , B 0 = 1 T yields the desired Givens-like gate with x = ±1, and with average exchange strength, number of rotations, and average timing errors of J ij ≈ 32 MHz, n ≈ 45, and δτ 2Q ≈ 0.1 ns.For the phase gates, the protocol is similar, but x is solved from the desired rotation angle.We note that typically, the two-qubit gates impose an independent restriction to the g-factor tuneability to ensure that fidelities are not limited by gate timing errors, which we find to be higher than the requirements for single-qubit gates.For example, in the above, we require approximately δg ±1 × 10 −4 (corresponding to dV q ±61 mV).
The process fidelities of the native Ising(α + π), Givens(χ)SWAP, and composite SWAP(θ) operations are shown in Fig. 4 (e)-(g), as a function of rotation angle and relative variance in tunnel coupling noise, σ tij /t ij .They are evaluated using the exact perturbative Hamiltonian (Supplementary Sec.S 4, Eq. ( S8)), at ϵ = 0. We average over N = 1000 random g-factor pairs.For the Givens-like gate, we determine the sign of χ from the sign of the g-factor difference.All gates enable fidelities F 0.9999 for sufficiently low noise in the tunnel coupling.For example, charge noise in the barrier gate voltage propagates to noise in the tunnel coupling.The dependence of both rotation angles on tunnel coupling is reflected in the fidelities: angles that require higher t ij are more sensitive to tunnel coupling noise.However, since the rotation angles of the SWAP-rotation gate (7) arise from single-qubit Z-rotations, it's fidelity is approximately independent of rotation angles, and expected to be limited by the fidelity of the Givens(χ)SWAP operation.

E. Transversal rotation gates
A gate set enabling universal quantum computing requires another single-qubit gate besides the Z(ϕ q ) gate and a maximally entangling two-qubit gate [66].To this end, we propose to realise a globally applied The gate composes into a single-qubit rotation gate e.g.via the identity Y (ϕ q ) := √ XZ(ϕ q ) √ X † .
In the nanogrid, a √ X gate can be applied globally by providing a small B 1 perpendicular to B 0 from large resonant structures, such as a dielectric 3D cavity resonator [67], or a superconducting resonator based on a coplanar waveguide patterned e.g. over the metal gate layers [68], with a resonance frequency coinciding with the average qubit frequency f Si ≈ 28 GHz, and a quality factor Q ≈ 100 to cover a bandwidth of 280 MHz corresponding to G q ±10 −2 (> 5σ G , assuming σ G = 10 −3 g Si ).Global control allows avoiding issues related to crosstalk and impedance matching, which would be a challenge with partially or fully local broadband structures [69].
The global X-control together with pipelining provides an extra limitation for the circuit compilation and density of pipelining.Since all qubits on the pipeline undergo the √ X pulses, the algorithms must be compiled with periodic X-control.A simple example code block for the pipelined, global-X-controlled compilation is given by [Z(θ 1 ), X(π/2), Z(θ 2 ), Z(θ 3 ), X(π/2), Native(θ 4 )] × D/6, (8) where Native(θ 4 ) is a native two-qubit gate of the system, as discussed in Sec.III D. This code block allows pipelining at a filling density of one in every three (logical) columns.The code block (8) maps to an equal density of single-qubit Z-rotation gates, Y -rotation gates, and native two-qubit interactions.Due to the variations in g-factor discussed above, driving all spins with a single drive tone is challenging.We instead opt for multitone driving and frequency binning [70], which is discussed in Supplementary Sec. S 8. We show that reaching F 0.9999 requires σ B1 < 0.1 µT and σ τ < 0.2 ns.

IV. APPLICATION AS BESPOKE HARDWARE FOR A NISQ EIGENSOLVER
We summarise the proposed qubit control protocols for operating the silicon spin qubit pipeline from Sec. III in Table II.The requirements of synchronous shuttling, lack of local runtime control, and qubit frequency variability leads to protocols where we fix gate times and adjust qubit frequencies with dc voltage tuneable parameters, namely the g-factor (qubit frequency) and the exchange strength.Each of these protocols are feasible up to fidelities F 0.9999 in the presence of noise, in the realistic scenario where qubit frequency variabilities are larger than the frequency tuneability.
We now exemplify how these elements propagate into solving a quantum computing problem in the NISQ era.Here, we focus on the variational eigensolver for the Fermi-Hubbard model, where the resources required to run the algorithm on a set of physical qubits have been estimated in [18], and where the task is to estimate the ground state of a 5 × 5 Fermi-Hubbard Hamiltonian.See supplementary Sec.S 9 for details of this algorithm.At the low level, the algorithm breaks down into SWAP-, and single-qubit Z-rotation gates for the so-called (simulated) state initialisation and (simulated) state evolution stages, while the bit-string (physical qubit) initialisation and readout stages also require qubit-selective qubit-flip X(π) and basis-change X(π/2) operations.We assume that we are not limited by initialisation or readout times.The single-qubit gate times, and the two-qubit gate time errors are upper limited by the qubit frequency tuneability.While the tuneability has not been studied on a large number of devices, based on the literature, we expect the processor clockspeeds no slower than 1 MHz (at B 0 = 1 T).This means that to run an algorithm of depth 10000, for example, we require qubit T * 2 10 ms.We summarise the estimated pipelined run-time, and contributions to the run-time, of the Fermi-Hubbard variational eigensolver in Table III, using the resource esti-mates from [18].There are several layers at the high level.The algorithm requires a number of iterations.Each iteration consists of a number of runs, which is equal to the number of circuit configurations multiplied by runs per configuration.The number of circuit configurations, in turn, is determined by the number of parameters, number of measured observables, and the number of noise levels, which is part of an error mitigation protocol [71].The number of runs per configuration is determined by the number of runs for one parameter, to measure one set of commuting observables, and the extra sampling cost for error mitigation.For each parameter-observable-setspecific run, we may then evaluate the circuit run time.
Two types of classical parallelisation are possible.As discussed in Sec.II, pipelining allows to perform N r number of repetitions for a circuit of depth D in time (D + N r )τ .For example, at maximal filling, this runtime scaling is (D + 2N r )τ .For single-qubit and twoqubit gate depths of D 1Q and D 2Q , the run-time for N r repetitions on the nanogrid pipeline (Fig. 2 (a)) with three physical shuttling steps between gates is then (D 1Q + 2N r )(τ 1Q + 3τ s ) + (D 2Q + 2N r )(τ 2S + 3τ s ).For D 1Q = 1174 and D 2Q = 2196 [18], and the gate time estimates for Z-rotation and SWAP-rotation gates from Table II, we find that pipelining reduces the run-time per circuit configuration from 25.5 minutes (assuming τ 1Q = 1 µs) to 1.74 seconds, i.e. by roughly a factor of 880.
We may also run e.g.different circuit configurations on different physical pipeline processors in parallel.To estimate the footprint of the pipeline processor, we expect the width of a single pipe to be approximately 340 nm, with a same-layer gate pitch of 100 nm.Likewise, we expect the length of a single-qubit or two-qubit gate step to be approximately 190 nm.Then, for N = 25 qubits, and a circuit depth of D = D 1 + D 2 = 1174 + 2196 = 3370 quantum logic gates, we estimate the footprint of a single pipeline qubit processor to be 8.5 µm ×640.3 µm.

V. CONCLUSIONS AND DISCUSSION
We have analysed a qubit pipeline architecture for realizing gate based quantum computation in the NISQ era.The architecture minimizes run-time local control resources, utilizing instead global run-time, and local preconfiguration control.This is made possible by a combination of an increased qubit grid layout size, and by synchronized operation, where steps of qubit state shuttling and quantum logic gates alternate.
Having described the architectural paradigm, we focused on a physical implementation case-study in the SiMOS electron spin qubit platform.Here, we laid out qubit control protocols under the pipeline-and platformspecific restrictions, demonstrating each theoretically with NISQ-high fidelities while remaining robust against qubit frequency variabilities characteristic for the platform.Our main focus has been to address this frequency Table III.NISQ Fermi-Hubbard eigensolver run-time on the pipeline.The times in parentheses assume τ1Q = τ2Q = 0.1 µs, whereas otherwise we assume, that τ1Q = τ2Q = 1 µs.
variability, while we may improve robustness against noise with bespoke control methods in the future.Most of the elements are possible to implement with presentday technology without further advances, but we expect more microwave engineering efforts to designing and testing switchable, dense transmission lines or resonators, and their ability to support a finite frequency bin.We then assessed the performance of this architecture for a NISQ variational eigensolver task.In the future, it may be possible to decrease the number of required gates per run by more directly utilising the native two-qubit gate family that arises from nearest neighbour exchange in the presence of Zeeman energy differences.The silicon spin qubit platform is well-suited to the pipeline approach, but the concept may also be implemented in other architectures, such as with trapped ions, or with superconducting qubits by replacing shuttling with SWAPs.
Indeed it would be an interesting topic of further work to explore an implementation based on SWAPs.There, the qubit grid remains fully occupied and stationary, and useful quantum information is transferred forward through the array (while states carrying no quantum information propagate in reverse).As before, the horizontal density of quantum information in the array can be ad-justed as required (e.g. to accommodate initialisation and measurement times) by introducing buffer states which do not participate in the calculation.Back-propagating states or buffer states do not interfere with the calculation due to the non-entangling nature of the SWAP gate.As discussed in the main text, non-adiabatic time evolution can create shuttling errors via so-called Landau-Zener transitions.Thus, high-fidelity shuttling should be * ucapsmp@ucl.ac.uk performed adiabatically with respect to inter-dot charge transition tunnel rates, and using ramp rates which are not resonant with valley-orbit transitions.
For a simple ballpark figure of adiabaticity, we may estimate probability for charge state error by evaluating the first-order, or single-passage, Lanzau-Zener transition probability, which is given by P LZ = exp −2πδ , where δ = t 2 ij /(4ν), and furthermore ν = Aℏω is the approximate drive velocity for a ramp with amplitude A (in units of energy) and angular frequency ω [3].Over a typical voltage range across an inter-dot-charge transition, A = eα × 25 mV, where α = 0.1 is a typical lever arm.At tunnel coupling t ij /h = 20 GHz, the ramp can be performed adiabatically (P LZ < 10 −4 ) with shuttling times of 9.1 ns or more (corresponding to ω/(2π) ≲ 110 MHz).

b. Control line footprints
A bias tee where current is not expected to flow can be realised using a resistor and a capacitor.Assuming a sheet resistance of ρ = 100 Ω/square [4], the footprint of a single R tee = 10 kΩ resistor would be 50 nm×5 µm.Like-arXiv:2306.07673v1[quant-ph] 13 Jun 2023 wise, assuming a capacitance per area of 1 pF/µm 2 [5], a C = 159 pF capacitor, to hit an RC-constant cutoff frequency of f cutoff = 100 kHz, would take around 159 µm 2 ≈ 12.6 µm × 12.6 µm.For a single column of 50 qubits, bias tees could be fitted into an area of approximately 630 µm ×12.7 µm.The 1-to-N power splitter can be realised as e.g. a common-source N -parallel-MOSFET.

Electric field dependence on applied gate voltages
For the g-factor Stark shift where E i are the electric field components and V j the associated gate voltages, we have a corresponding change in electrochemical potential of where α qj is the lever arm from dot q to gate j.The change in µ q would be detrimental to the shuttling scheme when uncompensated, which can be illustrated with the triple QD stability diagrams, shown in main text Figs.
3 (e)-(g).Stability diagrams show the boundaries of regions of constant charge as a function of two (or more, in higher-dimensional graphs) gate voltages.
In a successful shuttling sequence, the shuttling waveform takes the electron from the charge configuration (n q+1 n q n q−1 ) = (001), to (010), and to (100), as illustrated in Fig. 3 (e).Uncompensated g-factor modulation using V q can lead to a change in the proximal ground state charge configurations, which under globally applied shuttling sequence would lead to an error in the charge state as illustrated in Fig. 3 (f ).
To estimate the relative contributions of the plunger gate and the µ-compensating gate, we solve for the derivatives ∂E i /∂V as follows.We model a metal gate as a rectangular infinitely thin charge sheet centered at origin.The sheet has width a, length b, and a uniform charge density σ.The electric field components can be expressed as the double integrals of Eqs.(S3)-(S5), where k e = 1/(4πϵ 0 ϵ r ).These can be computed with Mathematica [6], or by hand using substitutions, which for the second integral of (S5) would read: x ′′ = x − x ′ , where dx ′′ = dx ′ , followed by the trigonometric substitution x ′′ /z = tan(θ), with dx ′′ = dθ cos(θ) −2 .The substitution allows to simplify the integrand in a form which is integrable using trigonometric identities.The resulting functions can be expressed in terms of elementary functions.
Once we fix a heterostructure of planar dielectrics with large surface areas, we obtain a relationship between applied gate voltage V and the effective charge density σ, as where the sum is taken over the interfaces between different materials from the charge sheet to the ground plane.For example, there is a single layer of dielectric and substrate between the gate and the ground plane in a planar MOS structure such that z 0 = 0, z 1 = d ox , and z 2 = d ox + d Sisub , where d ox and d Sisub are widths of the dielectric and the Si substrate, respectively.For a path perpendicular to the interfaces dl where a σ is a constant with respect to the coordinates, and is a function of the geometry.The relation (S7) allows us to express E(σ) = E(σ(V )), which allows us to evaluate the derivatives ∂E i /∂V analytically.Since E ∝ σ ∝ V , ∂E i /∂V ∝ E, and ∂E i /∂V is independent of V .Table I summarises the parameters used in this simulation.
For planar MOS or mostly ± z-valley-lying wavefunctions, the effect of E z due to V q dominates.This is because ∂E x /∂V q ≈ 0.010 ∂E z /∂V q , ∂E x /∂V µ ≈ 0.062 ∂E z /∂V q , and ∂E z /∂V µ ≈ 0.0037 ∂E z /∂V q at site q (see Fig. 3 (g)).We also expect ∂g/∂E z ≫ ∂g/∂E x .More generally, when both gates Stark shift the g-factor, compensation is possible, as long as the effects of the gates to g-tuning and µ q are asymmetric.Then Eq. (S1) simplifies to δg q (V ) ≈ ∂g/∂E z ∂E z /∂V q dV q .
As discussed in the main text, tuneability of δ gπ = ±3.6 × 10 −5 may require plunger gate voltage shifts of dV q = ±0.022V, which can be compensated with dV µ ≈ −α qq /α qµ dV q .In addition, perfect compensation requires α qq /α q±1 q = α qµ /α q±1 µ , where α q±1 q and α q±1 µ are the lever arms to of the subsequent and prior QDs to the plunger gate of q and the µ-compensating gate, respectively.The stability diagrams in Fig. 3 (e) are in fact simulated using the µ-compensation scheme described above.The results are identical to those in the absence of g-factor tuning.The stability diagram is sim-

Two-qubit gates
We define a few well-known two-qubit gates for reference [9].From the family of SWAP-rotation gates, The so-called Givens rotation gate has a similar form to the SWAP-rotation gate in the m z = 0 subspace: We define the phase gates )

Engineering the native operation
Here, we show an example protocol for choosing the exchange strength such, that the resulting unitary time evolution corresponds to the desired two-qubit gate.
In preconfiguration, the gate time τ 2Q , operation (CPhase, Ising, or Givens-like), and rotation angle (either α or χ) are set.In addition, the site-dependent gfactors G qi and G qj are known, as well as the detuning ϵ, and external dc magnetic field B 0 .
As discussed in the main text, the operation determines ϕ such, that for the phase gates we take ϕ = π + 2πn for some n, and for the Givens-like gate we take ϕ = π/2 + 2πn.Initially, we assume, that n = 0. We then solve for the desired x based on the gate rotation angle, i.e. either α or χ.For the phase gates For the CPhase gate, we take For the Ising gate, we take For the Givens-like gate, |x| = tan(χ) and n = 0.The sign of x is determined based on ∆E Z (J ij 0).These solutions are not unique.We also note that care must be taken if the desired rotation angle α = 0 or α = 2π for the CPhase gate, when α = π for the Ising gate.
The solved x translates to exchange strength J ij (and ∆ ij ) via t ij , and furthermore to Ω ij .Since Ω ij and ϕ are fixed, in general, the gate time τ = ϕ/Ω ij is shorter compared to the target τ 2Q .We use the above solutions for |x| at increasing n until τ τ 2Q , to find the n for which τ is closest to τ 2Q .For a high-fidelity operation, we require higher accuracy in τ than what choosing n can provide.To this end, we may fine-tune τ using g-factor tuning with either of the qubits, to minimize the gate time error At the best value of δg, we re-evaluate the required t ij to hit the desired J ij , and hence x and Ω ij .

Semiclassical Rabi model
The dynamics of a qubit with Larmor frequency ω 0 , coupling to a transversal magnetic field mode of frequency ν and amplitude B 1 , leading to coupling strength g * µ B B 1 /ℏ = ω 1 , is described by the semiclassical Rabi model, which we display for convenience.The Hamiltonian reads where ϕ = φ + φ α .
In a frame rotating by H R = e −iω R t the semiclassical Rabi Hamiltonian (S29) retains its form, but the frequencies get replaced, as The time evolution generated by this Hamiltonian reads where Ω = ∆ 2 + ω 2 1 is the Rabi frequency, and ∆ = ω 0 − ν is the qubit-field detuning.At resonance ν = ω 0 , ∆ = 0 and Ω = ω 1 .We may also write the operator in terms of Pauli matrices, as At resonance ν = ω 0 , ∆ = 0 and Ω = ω 1 .Then, In the frame ν = 0, the resonant unitary operator In the nanogrid, we apply transversal single-qubit control (represented as red vertical arrows) chip-globally using e.g.dielectric or superconducting resonators.(b) Qubits with a Larmor frequency distribution, represented as a gray histogram, can be driven with evenly spaced B1 tones, or bins (red vertical arrows).Using bin spacing determined by g-factor tuneability, g bin = 2δgπ, all qubits can be tuned to their closest bins.

Multitone driving with frequency binning
In the main text we discuss global transversal control (see Fig. S3 (a) for illustration).The difficulty with single-tone driving is illustrated by the Bloch-sphere polar angle arccos(∆ qν /Ω q (t)), where ∆ qν = ω 0q − ν is the qubit-drive frequency detuning, and Ω q (t) = ∆ 2 qν + ω 2 1q (t)/h is the time-dependent Rabi frequency.At small detuning ∆ qν ≪ ω 1q (t), arccos(∆ qν /Ω q ) ≈ π/2 and the effective magnetic field axis is on the transversal plane for all qubits, whereas for ∆ qν ω 1q (t) the effective field axis is significantly qubit-dependent.The small-detuning limit holds when G q /g Si ≪ B 1 (t)/B 0 .At B 0 = 1 T, to reach e.g.G q /g Si = 0.05B 1 /B 0 with G q 10 −2 , we would require B 1 = 100 mT, which is technologically out of reach.The minimum amplitude required to bring a qubit with G q = 10 −2 from the Bloch sphere north or south pole onto the transversal plane requires B 1 = 5 mT (coinciding with ∆ qν = ω 1q (t)).Even this is technologically challenging.
While insensitivity to qubit frequencies can be increased with pulse shaping close to the small-detuning limit [10], far from the small-detuning limit, we propose instead to achieve global control using frequency binning [11], which is illustrated in Fig. S3 (b).That is, we employ a control pulse of length τ 1Q consisting of 2N 1 drive tones, at where i = 0 ± 1, 2, 3, ..., N 1 is the bin, and the bin width is determined by the g-factor tuneability according to g bin = 2δg π , i.e. a bin width of ν i+1 − ν i = 2 MHz.The drive is akin to a finite-component frequency comb.Then, using the g-factor tuning described above, the frequency of each qubit may be tuned into resonance with the closest bin.We expect this bin width to be significantly larger than intrinsic ESR linewidths of O(1 kHz) [12].For example, choosing N 1 = 140 covers a g-factor distribution with G q ±10 −2 .There is also less power dissipation with frequency binning compared to single-tone driving due to the much smaller required amplitudes.At The effect of a single classical drive tone on a qubit is described by the unitary time evolution generated by the semiclassical Rabi model (see Supplementary Sec. S 7) U 1Q (t, ∆ qν , ν).While frequency binning allows one to drive all qubits resonantly (ω 0q = ν i for all q for some i), viewing the dynamics from a global frame, the laboratory frame is not resonant with any of the drive tones.In the laboratory frame, qubit dynamics is described by U 1Q t = π/(2ω 1 ); ∆ = 0; ν i = Z(ϕ i )X(π/2) (S36) for some ϕ i which increases with i.This can be shown, as Z(θ)U 1Q (∆ = 0, ν = 0) = cos(ω 1 t/2) cos(θ)I − i cos(ω 1 t/2) sin(θ)σ z − i sin(ω 1 t/2) cos(ϕ + θ)σ x + sin(ϕ + θ)σ y .(S37) Then, Z(θ)U 1Q (t, ∆ = 0, ν = 0) = U 1Q (t, ∆ = 0, ν) with θ = νt.This Z-rotation can be absorbed into Z(ϕ q ).In Fig. S4, we visualise gate operations using the decomposition to a rotation direction (n x , n y , n z ) (n k ∈ [−1, 1]), which is a vector on the Bloch sphere, and the rotation angle θ ∈ [−π, π].The decomposition allows us to study the conformity of U 1Q to the Z(ϕ i )X(π/2) operation.The ideal gate X(π/2) has a decomposition with θ = π/2, n x = −1, n y = n z = 0.In comparison, Z(ϕ i )X(π/2) has a linearly decreasing n y and n z for linearly increasing ϕ i , and thus a small quadratic deviation from θ = π/2 and n x = −1 with increasing bin number.
We study the gate fidelity of the analytical semiclassical Rabi unitary U 1Q as the conformity to Z(ϕ i )X(π/2) under noise.Unless otherwise stated, we use the same parameters as in the simulations described in main text.In particular, we take B 1i ≈ 35.7 µT (linearly decreasing with increasing bin number), g bin = 2δg π .The fidelities are essentially bin-independent, since the dominating errors come from the frequency at f Si .For a fixed bin  X and Z(ϕi)X(π/2) for linearly increasing ϕi, respectively.Solid green line shows the decomposition of the analytical semiclassical Rabi unitary operator with drive tone νi, and numerically integrated time evolution under the semiclassical Rabi Hamiltonian, U1Q, with a single drive tone at νi, corresponding to the resonant bin.Orange datapoints show the decomposition differences δ θ , δx, δy, and δz between U1Q with a single drive tone, and five drive tones from νi−2 to νi+2 and a smaller ω1.The Hamiltonian natively coincides with X(π/2) (viewed from the frame rotating with the average g-factor Larmor frequency fSi) at resonance ω0 = ν, for qubit Larmor frequency ω0, and drive tone ν, in the reference frame ν = 0 (see the overlap point between the light gray and the blue traces).At reference frames with ν ̸ = 0, resonantly driven qubit dynamics coincide with Z(ϕi)X(π/2) instead (see the overlap between the dark gray and the green traces).Effects of cross-talk can be compensated with a globally reduced B1 amplitude and thus ω1, while retaining a fixed τ1Q (overlapping solid lines).drive tones νi, and νi−1, νi, and νi+1 for each bin (agreement is better than 1 − 10 −4 for all bins).i = 10, we plot the Z(ϕ i )X(π/2) fidelity as a function of gate time error σ τ , and noise in the magnetic field component σ B1 , in Fig. S5.Fidelity behaves similarly to the Z-rotation gate fidelity, with noise sources contributing individually.

Figure 1 .
Figure 1.The qubit pipeline.(a) In a typical N -qubit solid state quantum processor, qubits reside at fixed spatial locations (e.g. on a √ N × √ N grid) with nearest-neighbour connectivity.(b) The qubit pipeline is a weaved grid in which N qubits are shuttled through D locations where fixed single-(1Q) or two-qubit (2Q) logic gates are implemented.Vertical lines indicate 2Q couplers, while horizontal lines indicate shuttling couplers.At runtime, qubits are initialized at one end, synchronously shuttled through the pipeline, and read out on the opposite end.(c) An example quantum circuit diagram, where an algorithm is decomposed into alternating steps of 1Q and 2Q gates.(d)-(f)The qubit pipeline contains physical locations which have been configured to implement 1Q (circles) and 2Q (connected circles) gates.Different qubit arrays (first (χ0, χ1, ...), then (ψ0, ψ1, ...), (ϕ0, ϕ1, ...)) can be piped sequentially through the structures, each representing one execution of the configured quantum circuit.

Figure 3 .
Figure 3. Z -rotation gate using Stark shifts.(a) Order of magnitude of Stark shift δgq, with respect to the bulk value gSi ≈ 2.0, as a function of external magnetic field B0 and single-qubit gate time τ1Q, required for the π-rotation gate Z(π).(b)Gate layout realisation of the g-factor tuning scheme with shuttling through quantum dots under gates q − 1, to q, and to q + 1.The voltage Vq is used to tune the g-factor at site q, while the voltage Vµ is used to compensate for the change in the electrochemical potential due to the g-factor tuning.(c)-(d) Overlaid stability diagrams of the (q − 1, q, q + 1) triple quantum dot at the start and end (blue lines), and at the middle (red lines) of the shuttling sequence, illustrate the requirement for electrochemical potential compensation.Using a waveform as shown in Fig.2 (e), shuttling proceeds from the charge configuration (nq+1 nq nq−1) = (001) (blue circle marker) to (010) (red star marker), and to (100) (blue triangle marker).(c) In the perfectly compensated case with g-factor tuning, the (010) region opens up during the shuttling sequence.(d) In the non-compensated case, adjusting Vq to tune the g-factor at q causes the (010) region to shift away from the ground state charge configurations.(e) Electric field gradients evaluated along the cut shown as a gray dotted line in panel (d).Electric field gradients due to Vq are denoted as blue, and those due to Vµ as orange traces.(f ) Estimated fidelity of Z(π) as a function of variance in actual gate duration and voltage noise affecting δg, with fixed σG = 10 −3 gSi, B0 = 1 T, and τ1Q = 1 µs.(see main text).
Figure 3. Z -rotation gate using Stark shifts.(a) Order of magnitude of Stark shift δgq, with respect to the bulk value gSi ≈ 2.0, as a function of external magnetic field B0 and single-qubit gate time τ1Q, required for the π-rotation gate Z(π).(b)Gate layout realisation of the g-factor tuning scheme with shuttling through quantum dots under gates q − 1, to q, and to q + 1.The voltage Vq is used to tune the g-factor at site q, while the voltage Vµ is used to compensate for the change in the electrochemical potential due to the g-factor tuning.(c)-(d) Overlaid stability diagrams of the (q − 1, q, q + 1) triple quantum dot at the start and end (blue lines), and at the middle (red lines) of the shuttling sequence, illustrate the requirement for electrochemical potential compensation.Using a waveform as shown in Fig.2 (e), shuttling proceeds from the charge configuration (nq+1 nq nq−1) = (001) (blue circle marker) to (010) (red star marker), and to (100) (blue triangle marker).(c) In the perfectly compensated case with g-factor tuning, the (010) region opens up during the shuttling sequence.(d) In the non-compensated case, adjusting Vq to tune the g-factor at q causes the (010) region to shift away from the ground state charge configurations.(e) Electric field gradients evaluated along the cut shown as a gray dotted line in panel (d).Electric field gradients due to Vq are denoted as blue, and those due to Vµ as orange traces.(f ) Estimated fidelity of Z(π) as a function of variance in actual gate duration and voltage noise affecting δg, with fixed σG = 10 −3 gSi, B0 = 1 T, and τ1Q = 1 µs.(see main text).

Figure 4 .
Figure 4. Two-qubit gate family from nearest-neighbour exchange.(a)-(d) Circuit identities for the unitary time evolution UNNE(ϵ, ϕ, χ) Eq. (3), describing nearest-neighbour exchange in the presence of Zeeman energy differences.Multiples of 2πn are left out of the rotation angles for simplicity.(a)-(b) Choice of rotation angle ϕ = π + 2πn realises the phase gates (a) CPhase and (b) Ising ZZ-rotation gate.(c) Choice of ϕ = π/2 + 2πn realises a gate close to the Givens rotation, where the rotation angle χ depends on the ratio ∆EZ /Jij.(d) The SWAP-rotation gate can be constructed from the native unitary gate with ϕ = π/2 + 2πn and χ = π/4, as two such native operations separated by single-qubit Z-rotation gates.The phases of the mz = ±1 components are fixed by subsequent application of another phase gate and single-qubit Z-rotations.(e)-(g) Fidelities for the native gates with (e) φ = π + 2πn, realising the Ising ZZ-rotation gate, and (f ) φ = π/2 + 2πn, realising the Givens(χ) SWAP operation, which, for χ = π/4 is used in the composition of SWAP(θ) (see panel (d)), and (g) the composite SWAP(θ) rotation gate as a function of rotation angles and tunnel coupling variance σt ij /tij.

Balint
Koczor is acknowledged for a useful discussion regarding gate fidelities.SMP acknowledges the Engineering and Physical Sciences Research Council (EP-SRC) through the Centre for Doctoral Training in Delivering Quantum Technologies (EP/L015242/1).MFGZ acknowledges support from UKRI Future Leaders Fellowship [grant number MR/V023284/1].

Figure S1 .
Figure S1.Programmable pixelgrid.A dense quantum dot array provides a reconfigurable implementation of the pipeline.Squares, or pixels, represent quantum dot defining metal gates.The decomposition of the algorithm to single-, and two-qubit gates determines which gates acts as plungers (green) and which as barriers (orange).(a)-(b) Shuttling forward along the pixelgrid is implemented with three-stage shuttling.(c)-(e) Two-qubit interactions between pipes are implemented with diagonal shuttling.

x
Figure S2.Attainable rotation angles.Illustration of the required ratio x = ∆ij/Jij corresponding to the sine (orange trace) and cosine (blue trace) of particular rotation angles χ.

Figure S4 .
Figure S4.Bin-dependence of the column-global single-qubit operation.Gate decomposition coefficients θ, nx, ny, and nz as a function of even bin numbers.Light gray and dark gray dotted lines show the decomposition of ideal X(π/2) = e iπ/4 √ X and Z(ϕi)X(π/2) for linearly increasing ϕi, respectively.Solid green line shows the decomposition of the analytical semiclassical Rabi unitary operator with drive tone νi, and numerically integrated time evolution under the semiclassical Rabi Hamiltonian, U1Q, with a single drive tone at νi, corresponding to the resonant bin.Orange datapoints show the decomposition differences δ θ , δx, δy, and δz between U1Q with a single drive tone, and five drive tones from νi−2 to νi+2 and a smaller ω1.The Hamiltonian natively coincides with X(π/2) (viewed from the frame rotating with the average g-factor Larmor frequency fSi) at resonance ω0 = ν, for qubit Larmor frequency ω0, and drive tone ν, in the reference frame ν = 0 (see the overlap point between the light gray and the blue traces).At reference frames with ν ̸ = 0, resonantly driven qubit dynamics coincide with Z(ϕi)X(π/2) instead (see the overlap between the dark gray and the green traces).Effects of cross-talk can be compensated with a globally reduced B1 amplitude and thus ω1, while retaining a fixed τ1Q (overlapping solid lines).drive tones νi, and νi−1, νi, and νi+1 for each bin (agreement is better than 1 − 10 −4 for all bins).

Figure S5.
Figure S5.Global √ X gate fidelity.Process fidelity of Z(ϕi)X(π/2) with Z(ϕi) determined by the bin (here, i = 10), as a function of variance in gate time στ , and in the magnetic field component σB 1 .

Table II .
Qubit control protocols on the pipeline.Summary of the protocols introduced in Section III.We have marked the gate times assuming τ1Q = τ2Q = 0.1 µs in parenthesis.Numbers that are not in parentheses assume τ1Q = τ2Q = 1 µs.Faster gate times require higher attainable g-factor tuning to prevent gate time errors from dominating the infidelities.