Surface loss calculations and design of a superconducting transmon qubit with tapered wiring

Analytical formulas are presented for simplified but useful qubit geometries that predict surface dielectric loss when its thickness is much less than the metal thickness, the limiting case needed for real devices. These formulas can thus be used to precisely predict loss and optimize the qubit layout. Surprisingly, a significant fraction of surface loss comes from the small wire that connects the Josephson junction to the qubit capacitor. Tapering this wire is shown to significantly lower its loss. Also predicted are the size and density of the two-level state (TLS) spectrum from individual surface dissipation sites.


INTRODUCTION
Quantum computers are made from quantum bits, which have natural sources of noise and dissipation that produce errors in quantum gates. Decreasing these errors increases the size and complexity of quantum algorithms that can be run on a quantum computer. When errors are reduced to about 0.1% per gate operation, then quantum error correction may be used on a large array of qubits in order to lower logical errors and execute vastly more complex quantum algorithms 1 . Qubit errors are often limited by the rate of energy decay from loss mechanisms.
Superconducting qubits can be thought of as an inductorcapacitor resonator, with the superconducting Josephson junction giving a non-linear inductance that allows the two lowest energy levels to behave as a qubit. The Josephson junction and the capacitance are designed to be separate physical entities, as illustrated in Fig. 1, and thus can be separately optimized. The size of the Josephson junction is about 100 nm. Its natural capacitance is negligible and junction defects are statistically unlikely because of its small size; the junction can thus typically be modeled as bringing no energy loss. The capacitance is made from superconducting pads with a relatively large millimeter size and about 100 μm spacing, producing a capacitance of about 100 fF for the transmon qubit 2 . When the capacitor is designed properly with control lines weakly coupled to an external circuit, dielectric surface loss from the superconductor and substrate is the dominant mechanism of energy loss. As for any surface loss mechanism, it has been found experimentally that increasing the size of this capacitor lowers the net effect of the surface loss on the qubit device 3 .
Calculating the surface loss is difficult because of the divergence of the electric fields at the metal edges, which has pushed researchers to solve the problem numerically with finiteelement models [3][4][5][6][7] . More recently, an analytical result was obtained using solutions of conformal mapping, which describes the electric fields of ribbon and coplanar geometries 8 . Unfortunately, this result is only approximate since it assumed the dielectric is thicker than the metal, opposite of the real design. Here, a more practical solution is presented that is valid for a few nanometer lossy dielectric surrounding a much thicker metal layer about 0.1 μm. Changes to the conformal predictions are calculated using the scaling of corner fields and numerical simulation, and are simple to use and understand.
For planar transmons, ribbon capacitors are typically embedded in a ground plane, and thus the analytical results are not valid. Numerical simulations and fit functions give capacitance and surface loss for this important practical case.
New surface loss predictions are also given for the wires that connect the Josephson junction to the capacitor pads. They typically have a width approximately the size of the junction, about 0.1 μm, and extend in length from the junction to the pads, about 50 μm. They are typically narrow compared to their length and thus have large electric fields at their edges. Conformal and numerical solutions are used to give analytic predictions of surface loss. Their long length produces significant surface loss, which can be reduced by tapering the wires, as illustrated in Fig. 1. I argue that tapering is better than previous stepped designs.
For numerical solutions, meshing is always a concern given the range of size scales, from nanometer thick oxides to millimetersized capacitor pads. Meshing is particularly important for 2-D and 3-D numerical solvers where the large grid makes it more difficult to calculate edge fields accurately. In this paper, the assumption of flat substrates (no trenching) allows solutions based on surface charges that are effectively 1-D, so that adaptive meshing at corners to the nanometer scale enables accurate checking of formulas. These formulas are thus a useful standard reference for verifying numerical methods. This is especially needed for experiments where surface loss parameters want to be accurately extracted 9,10 .
Expressing loss with formulas is also useful since the designer can separate out all the loss mechanisms, instead of modeling the entire device at once using numerical solvers. Optimization is more transparent, for example, trading off the surface loss of the qubit capacitance pads and the junction wires. In order to give useful design formulas for various geometries of the qubit capacitor, the surface loss is analyzed for 3 cases: a parallel plate, a ribbon capacitor where electric fields are between the two electrodes, and a coplanar capacitor where the fields connect through a ground plane. A typical design should be able to be modeled as a combination of these geometries, thus enabling surface loss predictions from formulas derived here.
The initial section introduces the surface loss calculation and shows that the participation ratios have significant contributions from dielectric factors. This theory is then applied to the simple case of a parallel plate capacitor, where the surface fields can be calculated readily. The next section considers the case of a coaxial and flat coaxial geometry because the fields can be expressed in simple formulas, thus allowing surface energy to be calculated. Here, important corrections are introduced due to finite thickness of the film. The next three sections give results for the important cases of a ribbon, coplanar and ribbon with ground capacitors. The surface loss from the junction wires are then calculated for both a straight and tapered design, the later showing lower loss. A final section discusses how the splitting spectrum from the twolevel-states of the surface loss can be estimated knowing the surface electric fields. The methods section describes how numerical calculations were performed here.
RESULTS AND DISCUSSION Qubit model and participation ratios Figure 2 shows an example design of a full differential qubit, include the qubit electrodes and an shielding ground plane (gray). The full design can be broken up into the junction and tapered wires (red), a ribbon capacitor (blue) and a coplanar capacitor (green). The capacitances and losses from the combination of the structures would then be used to optimize the design.
We are interested here in calculating the loss from dielectrics, since the loss from the metallic structures are typically negligible for superconductors. For a crystalline substrate such as silicon or sapphire, the loss is dominated by the thin surface layers of the films 4 : the metal-air (MA), metal-substrate (MS) and substrate-air (SA), typically coming from amorphous oxides.
The total loss tangent for these thin layers is given by Σp i tan δ i , where surface interface type i has loss tangent tan δ i and participation ratio of the stored energy where the normal volume integral is replaced by a surface integral dA for a thin dielectric layer with thickness t i , dielectric constant ϵ i , and a surface electric field E i . The participation ratio is normalized by the total capacitor energy W = CV 2 /2, where C is the total capacitance and V the voltage. When designing the qubit, the qubit capacitance C is usually fixed to a desired parameter. Because the results are more easy to interpret in terms of design distances, it is convenient to describe the qubit capacitance in terms of a length using For C = 100 fF, a value used for a qubit non-linearity of about 200 MHz, one finds L = 11.3 mm.
For thin films, the electric fields of the top and bottom dielectrics can be considered separately. Thus the electric fields E 0 can be solved for ϵ = ϵ 0 , the free space value, and then the participation ratio is multiplied by 1 for the solution on the air side and ϵ s for the substrate side. The surface dielectrics can be taken into account with the three participation ratios 4 where the area integrals correspond to the appropriate surfaces for each type, and the bracketed terms are called surface energies. Tangential fields are only included for the SA formula, as appropriate for thin films 4 . For the above MA and MS surface energies, the electric field is for only one side of the metal. Thus for the total surface energy U calculated in the next sections, the above MA and MS energies in brackets should be U/2. Dielectric constants are for a silicon substrate ϵ s = 11.7, aluminum oxide ϵ MA = ϵ MS = 9.8, and silicon dioxide ϵ SA = 3.8; the relative weights of the MA:MS:SA dielectric terms are 0.10:14:3.8.

Differential parallel plate capacitor
The simplest geometry is a parallel plate capacitor, which allows a simple calculation of the surface loss due to constant electric fields. A differential geometry is illustrated in Fig. 3. This contribution is typically needed when transmon qubits are made Qubit design with taper. Drawing of prototypical qubit device, with relative dimensions approximately to scale. The qubit capacitance C ≃ 100 fF is made from two ribbons (shaded gray) of width b − a = 100 μm and length ℓ = 1300 μm, separated by distance 2a = 100 μm. Wires (drawn in red) connect to the sub-μm Josephson junction in a conventional design. Surprisingly, the loss from the small junction wires is about equal to that coming from the large ribbons. This paper proposes tapering these wires (shaded blue) as a near-optimal design. Fig. 2 Example of full transmon design. Example design of a differential transmon qubit that incorporates several of the capacitance structures described here. Red shows the junction and tapered wire, blue is a ribbon capacitor, and green is a coplanar capacitor. The outer ground plane is gray. The capacitances and losses would be added to give a good approximation for the entire design.
using bump-bonded substrates, where the second substrate acts as a ground plane above the qubit metal pads and thus adds capacitance to the qubit. This structure can be treated as parallel plate with each plate having width w and length ℓ and a separation s to the ground plane, with capacitance where the 1/2 factor coming from the differential design of the qubit, where the capacitance of each parallel plate is in series. The electric field in each differentially driven capacitor is E p ¼ 1 2 V=s, and the total surface energy is where a factor of 2 comes from the two parallel plates, and another from surface loss at the 2 plates of the capacitor. The participation ratio for the parallel-plate capacitor is Participation ratios are written with first the dielectric factor, then the dielectric thickness, and finally the geometric factors for the design.

Thickness correction
The finite thickness of the metal film changes the surface electric fields mostly at the edges of the film. Since the edge fields will be similar for different geometries, their effect will be calculated here for a simple flat coaxial film. The resulting simple correction to the surface energy can then be applied to different geometries. It is useful to start with a 2-D solution of a coax line, with an inner conductor of radius r and an outer conductor of radius R as illustrated in Fig. 4a. The solution for the radial electric field on the surface of the inner conductor is with its strength decreasing with radius x as The electric field energy (ϵ/2)∫E 2 dv is calculated from a volume integral dv of the electric field E. Because the interest here is for the surface energy in a 2-D geometry, we compute the surface energy U/ℓ for a line length ℓ so that the full energy will be multiplied by the surface thickness and length ℓ. For the coax geometry, the surface energy of the inner metal at radius r is The surface energy coming from the substrate, the red line in Fig. 4a, is a cut through the middle of the coax where the factor of 2 before the integral comes from the left and right substrate sides. Figure 4b shows a flat coax, where the circular inner conductor is replaced by a thin film of width 2r. The electric field magnitude along the coordinate x of the thin film is found from numerical solutions for all x to be given by a conformal-mapping solution which fits well for R > 2r. The electric field is perpendicular to the metal surface but parallel to the substrate surface. The voltage integral checks properly  Side view of a differential parallelplate capacitor. The parallel plate has width w and length ℓ, using a separation s of a vacuum gap. The differential voltage drive is ±V/2. The surface energy is U p . The surface energy for the metal surface (jxj < r) is where the factor of 4 is for the top/bottom and left/right parts of the metal, and the logarithmic divergence in the integral at the edge is cut-off at half the thickness t of the film. Numerical simulation for a film with a rectangular cross-section of thickness t shows that the electric fields within t/2 of the outside corner have a power law behavior with exponent p = − 1/3, as appropriate for a 90 degree corner 4,11 . As an initial approximate solution, this power law dependence of the corner field is then matched to the computed field E f ðr À t=2Þ at a distance t/2 from the corner. At a distance r c from the corner, the corner field is Including all 4 corners, with 2 sides per corner, the line energy for the corner is approximately With 1 + 2p = 1/3, the numerical factor in Eq. (24) is 6 and does not depend on t.
The total surface energy for the metal is the sum of the two energies where c m is the corner correction for the finite thickness of the metal. Figure 6 gives c m obtained from numerical integration of the surface energy. The corner correction is slowly varying with relative film thickness t=r and has a typical value close to the value 6 obtained above by scaling of the corner fields.
It is useful that the surface energy is predicted well even for a thick film, with thickness as much as one-half the width. The edges typically contribute about 1/3 of the total surface energy. Also shown is the case of a semicircular edge, which lowers the surface energy a non-negligible but small amount, providing a lower bound for the correction of a rounded edge. This result shows that a constant term added to the logarithmic cut-off term well represents the corner fields. Note the similarity to Eq. (12). Here, the bracket term in Eq. (25) is slightly larger than the corresponding π constant in Eq. (12), as expected since the flat coax has large edge fields. The correction factor lnð4r=tÞ ! lnð4r=tÞ þ c m will be used in all formulas for the metal edge.
The surface energy for the substrate surface (r < x < R) is where the factor of 2 is for the left/right parts of the substrate. Like found for the metal surface, numerical integration for finite thickness gives a corner correction 1.6. Since typically r ( R, the total substrate surface energy is This is smaller than the surface energy for the metal surface since it does not include a sharp edge. The correction factor lnð4r=tÞ ! lnð4r=tÞ þ c s will be used in all formulas for the substrate edge.
Differential ribbon capacitor Considered next is the capacitance between the two leads of the qubit, modeled as two long and straight ribbons as illustrated in Fig. 7. Each ribbon has metal spanning a distance a to b from the centerline, with length ℓ ≫ b and a metal thickness t. A conformalmapping solution from Ref. 8   ribbon capacitance for a differential voltage V is (31) where K(k) is the complete elliptic integral of the first kind. Equation (33) is an excellent approximation to Eq. (32). The effective dielectric constant has contribution from both the air (ϵ 0 / 2) and substrate (ϵ s ϵ 0 /2). From the conformal-mapping solution Eq. (5) of Ref. 8 , the surface fields are where the E field is parallel to the surface on the substrate and perpendicular on the metal. The surface integral is evaluated in three sections: giving Note that S c = S i + S o . The surface energy of the center metal section is where the factor of 4 comes from the two ribbons and the top/ bottom surfaces. The dimensionless surface integral is obtained from S a /a = S c , along with adding the corner correction c m for a finite thickness. The surface energy of the inner and outer substrate sections is where the factor of 2 is from the two sides of the ribbon. The substrate surface energy is smaller than the metal by approximately a factor of 2.
The ribbon capacitor has participation ratios coming from the surface-air, metal-substrate, and substrate air interfaces, calculated using Eqs. (3)-(5), (45) and (48) The only difference in the 3 participation ratios is the dielectric factors and the small change from the corner constant. The black lines in Fig. 8 are a plot of the dimensionless surface energy S a (c m )/K 2 for the metal (solid) and S a ðc s Þ=K 0 2 for the substrate (dashed) as a function of the normalized distance (b − a)/a. The metal surface energy is greater because of the higher corner constant c m > c s . As the distance b − a increases, the surface energy decreases. Typical designs use (b − a)/a~1. Note that the surface energy drops by a non-negligible amount with the lower corner constant, showing that the edge fields from the finite thickness are important.
For the case where all of the capacitance comes from the ribbon C r = ϵ 0 L, the participation for the metal-substrate interface is The last factor is the geometric mean of the ribbon and coplanar curves of Fig. 8, shown in red.

Differential coplanar capacitor
The qubit can also have capacitance to ground. This can be modeled as a coplanar structure as shown in Fig. 9, where each side of the qubit has a pad with width 2a and length ℓ ≫ a, with a ground plane at a distance b from the centerline. As this is the "dual" of the ribbon capacitor, with metal and substrate switched, similar conformal solutions can be used with minor modifications. . Also plotted in red is S a =KK 0 for the case of all capacitance coming from the ribbon or coplanar geometry.
The differential capacitance is where C K is defined in Eq. (32), and the initial factor of 1/2 comes from the two coplanar capacitors in series. From Eq. (25) of Ref. 8 , the electric field for each coplanar capacitor is where now the field is perpendicular to the substrate in the inner and outer sections, and parallel in the center. The surface energy of the metal sections is similar to the ribbon case except for an extra factor of 2 to account for the series capacitors, as can be seen from Fig. 9 since ℓ only accounts for half of the total length. The metal and substrate surface energies are Note the similarities to the ribbon formulas. The participation ratios are twice as large as the ribbon and with K replaced by K 0 For the case where all the capacitance comes from the coplanar structure, the participation is the same as the ribbon design, for example A single-ended coplanar design is used to test resonators. In this case, the coplanar capacitance of Eq. (53) does not have the initial 1/2 term. The surface energy U and participation ratios are a factor of 2 larger. The participation p r MS ðC c Þ includes these two factors, so Eq. (60) is unchanged for the single-ended design.
Differential ribbon capacitor with ground Planar transmons are typically designed to have a ground plane surrounding the qubit capacitor, as shown in Fig. 2. For the ribbon capacitor considered previously, a ground plane is added here from minus infinity to −c and c to infinity, where c > b, as shown in Fig. 10. The capacitance and surface loss is computed numerically and then fit to functions based on the previous ribbon formulas.
The surface electric field is well described a simple modification to the ribbon case of Eq. (35) Integration of surface charge from the numerical solutions gives a simple modification to the ribbon differential capacitance of Eq.
C rg ' C r =½1 À ðx e =cÞ 2 0:23 ; (62) x e ¼ b À 0:15ðb À 1:2aÞ : (63) Figure 11 shows the numerical results (points) and the fit function where the contribution of S ao corresponds to the outer metal of a coplanar capacitor between b and c S ao ðb; c; t; c m Þ ¼ The surface loss for both the inner and outer substrate gaps gives the fit function where the second contribution of S a corresponds to the substrate of a coplanar capacitor between b and c. Figure 11 shows the numerical results are well represented by the fit functions.

Differential junction wires
The connections between the Josephson junction and the capacitor electrodes are made through two junction wires of total length 2d, as shown in Fig. 12. Starting with the simple case Fig. 9 Differential coplanar. a Cross section of a differential coplanar capacitor, with metal conductors from −∞ to −b, −a to a, and a to ∞. The surface energies for the metal and substrate are U m c and U s c respectively. b Top view, showing each differential electrode with length ℓ and driven by ±V/2. The gray bar shows typical location of the junction wires. The x-direction is horizontal and the shaded region corresponds to the substrate. of treating these wires as round with radius r and placed end-toend each with length d, the surface field can be calculated numerically using the potential matrix Eq. (97) for a 2-D geometry with cylindrical symmetry. For a differential voltage V, the surface electric field as a function of distance y from the junction is well described by as shown in Fig. 13. In comparison with Eq. (9), the second term is equivalent to a coax of inner radius r and outer radius 2y. The first term 1/2 represents this coax placed in series with a second coax of the same dimensions, which represents the fields emanating from one circular wire, expanding to a distance 2y, and then converging in to the other circular wire. This 2-D numerical calculation also allows the radius r to change with distance y. Modeling a linear taper with r = S y, the electric field is found to be well described by Eq. (69) with r replaced by r (y), as long as the taper is not too large S < 0.4; larger slopes are found not to reduce the electric field significantly. Figure 13 shows numerical results for both a straight and tapered cylindrical wire, with good agreement to the approximation formula Eq. (69).
A solution for a flat wire can be obtained by assuming the wire has the x-dependence of the electric field as given in Eq. (16), but with an overall dependence of E fw with y that is determined numerically. Equation (100) in the appendix shows how to solve this problem with a potential matrix. Numerical solutions for both straight and tapered flat wires show that a good fitting function is which has the form of E f in Eq. (15) but with 2R replaced by 4y. It is again valid for small slope S < 0.4. The factor of 4 in the logarithm can be understood as a factor of 2 from the coax to the wire geometry, and another factor of 2 from the circular to flat coax formula in Eqs.  over the wire length where the factor of 2 before the integral accounts for both junction wires. The last formula was fit to numerical integration. Because of the d=r factor, this surface energy can be large, so a more optimal solution is to taper the wire as explained below. Similarly from Eq. (29), the surface energy of the substrate for a straight wire of constant width is lnð4r=tÞ þ c s ln 2 ðd=rÞ d r ; The participation ratios for straight wires are where multiplicative factors are given by lnð4r=tÞ þ c s ln 2 ðd=rÞ : As found previously, the equations differ only in the relative dielectric constants and the corner constant. The capacitance of the straight junction wires is found from numerical simulation C sw ' 4:1 ½ðϵ s þ 1Þ=2 ϵ 0 d= lnðd=rÞ : (81)

Tapered junction wires
The large d=r ratio in the above participation ratios contributes to a large surface energy, since the small width of the wires produce large electric fields at its surface. As surface loss decreases with increasing size, it is natural to increase the width of the wire to lower loss. A solution to minimize surface energy is to taper the wire, increasing the wire width with increasing distance y from the junction as shown in Fig. 12. The contribution to the line energy, the surface energy per line length dy, is the integrand of Eq. (72), where r is now a function of y. The integrand is minimized at distances y/t = (10, 100, 1000) for a half-width r=y ¼ ð0:363; 0:402; 0:425Þ, respectively. An effective solution is to taper the wire according to rðyÞ ¼ maxðr 0 ; ðy À 5tÞSÞ with the taper starting at y = 5t, optimizing the slope S for lowest energy. Numerical integration of the line energy gives the metal surface energy for a tapered wire that is fit by The metal surface loss for the junction wires is plotted in Fig. 14 for the straight and tapered cases, obtained by numerical integration of Eq. (72). At small distances d ≲ 5 μm, the two results are similar, but at large distances the logarithmic scaling makes the tapered loss significantly lower. It is standard practice to increase the overall size of the qubit capacitor to lower its loss. When using a large d, it is thus increasing important to optimally design the junction wires with a taper.
The formulas for the participation ratios for a tapered wire are It is recommended using a continuous taper as described above, not a stepped taper as in previous designs, since the continuous taper is optimal at every distance from the junction x; the sharp corners of the steps will produce larger electric fields and increase the surface energy. It is not reliable to accurately compare the surface loss of stepped versus tapered wiring since numerical solutions do not have meshing dense enough, which is difficult for 2D simulations and especially problematic for 3D. The capacitance of the tapered junction wires is found from numerical simulation Comparisons and transmon devices These formulas agree well with a prior numerical simulation, as detailed in Table 1. The first example shows good agreement with numerical results from Ref. 4 . Note the only difference in the MS and SA formulas are from the corner constants c m and c s . The second example does not agree well with the MS geometry of Ref. 10 , although the results here are for a flat substrate with no trenching d t = 0. It is unexpected that the prior numerical results with trenching gives a higher participation ratio for all surfaces. This table suggests that numerical calculations may give participation ratios with errors as high as a factor of 3-10. Surface loss closely scales as the inverse of the system size, as described previously in Ref. 4 . However, the calculation for the participation ratio from the junction wires has the opposite effect, as its participation increases with length. Thus there is a crossover in distance d where the surface loss of the wire goes from relatively unimportant to dominant. Formulas for predicting this crossover is an important result of this work. Table 2 shows the participation ratios for the 3 interfaces and 5 qubit capacitance types, for an example geometry of size scale of 100 μm that is appropriate for current devices. Here a constant thickness 2 nm of the surface oxides is assumed. The ribbon has the same participation as the coplanar geometry, as expected. Of course, predictions depend on actual device parameters, which can be readily made with these formulas.
For the qubit capacitance, the metal-substrate (MS) interface dominates the surface participation. For the ribbon design, the substrate-air (SA) is about 5 times smaller due to the dielectric factors, half the surface, and a lower corner constant c s . However, the wire loss is not much smaller and clearly indicates that for present designs this contribution should be carefully considered. Importantly, the tapering of the wire will produce a significant improvement in qubit performance, about a factor of 3.
When qubit designs use multiple chips that are bump-bonded together, a parallel plate capacitance is often formed between the qubit chip and ground. Table 2 shows that the participation ratio of this structure needs to be considered even for a plate separation of s = 5 μm, especially since the thickness of the other surfaces are likely less than 3 nm.
Although the formulas predict surface energy will decrease slightly with taper slopes greater than 0.4, doing so is not recommended since numerical simulations show that electric fields do not decrease in this range. Besides, the surface energy only slightly decreases above a slope of 0.2.
An interesting question is how much more surface loss is there for thin films, arising from the large fields at the edges. It is possible to compare surface energy for a round coax and flat coax of the same width using Eqs. (12) and (25), which shows that the ratio of the metal surface energy is lnð4r=tÞ þ c m π ' 4:0 (90) for r ¼ 50 μm and t = 0.1 μm, typical dimensions considered here. Although the metal-film edges produce more loss, the increase is still acceptable. Note that the logarithm factor is 7.6, so that about 1/3 of the surface energy comes from the corners within t/2 of the edges. The MA and MS participation formulas in Eqs. (3) and (4) use surface energies U/2 for the two sides of the film, which are then multiplied by dielectric constant factors. However, since the metal film usually sits on top of the substrate, this splitting of surface energy should change somewhat. One expects the air side of the surface energy to include both sides of the top corner and the outside of the bottom corner, while the substrate side only includes the film edge of the bottom corner. Since these two sides of the corner contributes similarly, one expects the constant factor added to the logarithm to be about 1.5 c m for the air side and and 0.5 c m for the substrate side. For example, this modification changes the MA prediction of Table 1 from 0.060 to 0.077, closer to the numerical result 0.010.
Since the MS interface clearly dominates in the participation ratio, there has been effort to minimize this oxide layer by surface treating the silicon wafer before depositing the metal film 12,13 . The MS thickness and loss tangent are thus parameters that should be measured carefully to optimize a design. The qubit capacitor is much larger size than the junction and its wires are often made in a separate step patterned with optical lithography, while the junction and wire is patterned with electron-beam lithography. If the surface treatment is easier or even possible with the optical lithography step, it is then recommended that the taper is brought down to within 1 μm or so of the junction to minimize its loss. In this case the data in Fig. 14 would be used to estimate the loss from both sections of wire; because of the logarithmic The top three are for the primary qubit capacitance, and the bottom two are for straight and tapered wires that connect to the junction with capacitancẽ 7 fF. For comparison purpose, they all use a length ℓ such that the total capacitance is 100 fF. Geometry parameters are thickness t = 0.1 μm; parallel plate (s, w, ℓ p ) = (5, 100, 1130) μm; ribbon and coplanar (a, b, ℓ r , ℓ c ) = (50, 100, 1391, 1138) μm; junction wires ð2d; r; r 0 Þ ¼ ð100; 0:1; 0:1Þ μm and S = 0.4. Dielectric parameters are (ϵ s , ϵ MA , ϵ MS , ϵ SA ) = (11.7, 9.8, 9.8, 3.8). For simplicity, here the oxide thickness is assumed to be t MA = t MS = t SA = 2 nm; results can be simply scaled with expected thickness. Total loss can be estimated by multiplying the surface loss tangents 10 ; typical values for amorphous insulators are 0.005 14 . Comparison of prior numerical results from finite element analysis with formulas from this paper. The first example shows good agreement for dependence, there would still be some contribution from even the short junction section.

Two-level states
Surface loss typically comes from two-level states (TLS) 14 , which saturate and produce less loss at high excitation fields. Using the numerically computed surface fields, the dependence on power can be found by scaling the reduction in loss from the local electric field E with where the saturation electric field E s depends on microscopic parameters of the TLS 14 .
Since saturation measurements are typically made with coplanar resonators, numerical integration of the surface loss is shown in Fig. 15 for three values of a, each with the gap equal to the inner metal width b = 2a. As expected, for large saturation fields (loss at low power) the largest resonator gives lowest loss. At large fields, the loss of all three resonators converges. This behavior can be understood using dimensional analysis: scaling all the lengths by D decrease the electric field by E~1/D, but increases the surface integration by D. For loss at low power, the integral scales as E 2 D~1/D. But when saturated, EE s D~E s gives constant scaling. Figure 15 also shows volume saturation, for example coming from TLS in the substrate.
The analysis so far has treated the dissipation continuously. However, surface loss comes from a bath of two-level states, with individual states that are spectroscopically observable for smallarea devices 14 . Simple models predict both the magnitude and the density of TLS, so its spectrum can be extremely useful for identifying the physical location of the loss.
The dipole moment of the TLS couples to the electric field of the 0 to 1 qubit transition. This produces a qubit splitting with random frequency and splitting size, but with a maximum splitting size given by Eq.
were d TLS /x j is the relative size of the dipole to the dielectric thickness, E 10 is the qubit energy, and e 2 /2C is the qubit charging energy. Note that S max is proportional to the qubit electric field and inversely proportional to the square-root of the qubit capacitance. For a junction capacitor with parallel-plate separation 2 nm and a qubit capacitance 2 pF, a value S max ¼ 74 MHz was measured. For a transmon qubit with C = 0.1 pF, the above scaling gives where E/V has a dimension of inverse distance and has been computed here for the various surface electric fields. Since twolevel-states tend to have universal behavior, especially if one considers amorphous oxides, this formula is useful for estimating S max from other surfaces. For the MS interface of a ribbon capacitor, Fig. 16 shows a plot of S max versus the distance from the inner corner r c , which includes edge corrections at a distance less than the half-thickness t/2. The  size of the largest splittings are in the few hundred kilohertz range.
The number of splittings is proportional to the capacitor volume. Figure 2 of Ref. 14 shows that the size of the splittings have a log-normal distribution, so that the largest splittings are between S max =3 and S max and have a density 0.5/μm 2 GHz. The expected TLS density of the ribbon capacitor can be estimated by the effective integrated area A(S), obtained by multiplying r c by twice the length of the ribbon 2.8 mm and a factor 3/2 to account for the thicker 3 nm thick surface oxide. Since the observed splittings are dominated by those close to S max , the splitting density ρ S between splittings S 1 and S 2 is thus approximately given by ρ S ' ð0:5=μm 2 GHzÞ½AðS 2 Þ À AðS 1 Þ : If one assumes the qubit splitting measurements spans a 2 GHz frequency range, then the first observable splitting should occur on average for an integrated area A = 1 μm 2 . As shown in Fig. 16, TLS should be statistically observable even within a few nanometers from the metal edge. The largest splittings at 3 nm should have size 300 kHz, with an average spacing of about one per 200 MHz in the qubit frequency. For a parallel plate capacitor, the effective distance for the electric field is the separation multiplied by ϵ MA = 9.8. For the example of Table 2, this gives 49 μm. One finds a splitting size of 13 kHz, and an effective area of 1.5 times the capacitor area.
Junction wire results are shown in Fig. 17 for the untapered and tapered cases. These plots were obtained by numerically breaking up the wire into about 100k sections, then computing S max and the differential area dA for each section. The curve is obtained by sorting S max from large to small, and then cumulative summing over the corresponding dA to obtain the integrated area A. The tapered case shows lower splittings S max , consistent with the continuum theory. The TLS become statistically observable for A > 1 μm 2 , which predicts splittings in the several MHz range. The dependence on d shows that the dominant contribution to the TLS are for distances greater than about 10 μm; shorter distances are unimportant because they have small areas. The dominance of an intermediate length scale is perhaps a surprising result, and shows why detailed theory is needed to optimize the wire design.
This result suggests that undercutting the junction wires into the substrate can be an effective solution to decrease the contribution of the metal-substrate interface. Since there is little contribution at small distances, it is not essential to undercut around the junction, which should improve the reliability of the fabrication and the stability of the junctions.

Summary
Calculation of participation ratios and surface loss is challenging because of the divergence of the electric fields at metal edges. Previously, these fields were solved in the infinitely thin limit using solutions from conformal mapping. Here, the solutions were extended to the useful limit where the thin surface oxide (few nm) is less than the metal film thickness (0.1 μm), and less than the typical film size (100 μm). The finite thickness condition was solved via a calculation that matched the conformal fields to edge fields, then checked and refined with numerical simulation. Going forward, these formulas are also useful when checking numerical simulations for systematic errors due to meshing.
Formulas are given for common capacitor structures. By separating out the geometery of actual designs, participation ratios can be calculated accurately and then used to optimize the design. This is an important check on numerical calculations since misleading results can come from finite meshing when structures range in size from nanometers to millimeters.
For junction wires, a solution for the capacitance and surface loss was obtained using well-formed models, approximations and numerics, which should give accurate and reliable formulas. A tapered junction wire was shown to have superior performance compared to straight wires when the wire length is longer than about~10 μm. This design feature is important for the latest generation of devices that use large capacitor size to lower surface loss. A further design improvement for the taper was suggested.
These electric field solutions enable a prediction of the TLS spectrum, which could be invaluable to identify where the TLS comes from in the qubit design.
Finally, it is hoped that these results will encourage researchers to precisely test surface loss theory, and measure in additional experiments the various surface loss parameters. By doing so, this should speed the optimization and development of long coherence time qubits.

Numerical calculation of surface electric fields
For thin films suitable for superconducting qubits, it is useful to numerically calculate the electric fields, for example for a thin film of finite thickness. Fortunately, realistic transmon designs are well approximated by simple geometries with fields that can be well described using simple fitting functions, so that they can be physically understood and optimized. Two-dimensional geometries are particularly amenable to efficient numerical solutions and thus their method of solution will be described here first. For simplicity, the calculations here will assume a constant dielectric constant ϵ. Corrections due to the substrate and vacuum are included in the main text. Figures 7, 9 and 10 show geometries to be considered here. The first is 2dimensional, with solutions given per unit length in the third dimension, with results typically scaled with length ℓ. The second solution uses cylindrical symmetry to turn a 3-dimensional problem to 1-D. The last uses an approximation to the edge fields so that a thin film wire can be similarly calculated in 1-D.
Numerical solutions can be obtained through inverting a matrix. For a 2-D geometry with translational invariance in the z direction, the problem is first broken into an vector of points in the x-y plane that have line charge q ! . The voltage V ! can be solved with the matrix equation where the potential matrix M has elements  16) and (70), and numerically breaking up the wire into small area sections. The tapered wire shows lower maximum splitting, consistent with the continuum results. For the untapered wire, the observable areas A > 1 μm 2 (arrow) has S max in the 1-4 MHz range, whereas for tapered it is below 1.5 MHz. Note that the dominant contribution comes from wire surfaces at a distance greater than about 10 μm.
where ρ ij is the distance between point i and j. For metal electrodes the voltage is set instead, so the charge can be obtained using q ¼ M À1 V ! , where the inverse matrix M À1 can be thought of as a capacitance matrix.
The time to solution grows as the cube of the number of points, which can be solved quickly for size 1k -10k. For a 3-D geometry with cylindrical symmetry, the potential matrix can be solved for a circular ring of total charge q, giving a potential matrix with elements where ρ ij is the distance between points in the r-z plane, and r i and r j are the radial components. The Python ellipk(m) function is equivalent to K(k) but with m = k 2 , and allows negative m arguments. For a similar 3-D geometry of a flat coax, the potential matrix for the inner conductor is where y ij is the distance between points i and j on the centerline of the wire. In comparison with the matrix for the cylinder geometry Eq. (97), the difference is the absence of the factor of 4 in the ellipk argument.

DATA AVAILABILITY
The data that support the findings of this study are available from the corresponding author upon reasonable request.