Entanglement across separate silicon dies in a modular superconducting qubit device

Assembling future large-scale quantum computers out of smaller, specialized modules promises to simplify a number of formidable science and engineering challenges. One of the primary challenges in developing a modular architecture is in engineering high fidelity, low-latency quantum interconnects between modules. Here we demonstrate a modular solid state architecture with deterministic inter-module coupling between four physically separate, interchangeable superconducting qubit integrated circuits, achieving two-qubit gate fidelities as high as 99.1 ± 0.5% and 98.3 ± 0.3% for iSWAP and CZ entangling gates, respectively. The quality of the inter-module entanglement is further confirmed by a demonstration of Bell-inequality violation for disjoint pairs of entangled qubits across the four separate silicon dies. Having proven out the fundamental building blocks, this work provides the technological foundations for a modular quantum processor: technology which will accelerate near-term experimental efforts and open up new paths to the fault-tolerant era for solid state qubit architectures.


INTRODUCTION
Progress in quantum operations over multi-node networks could enable modular architectures spanning distances from the nanometer to the kilometer scale [1][2][3][4][5] . Heralded entanglement protocols, whereby entanglement is generated probabilistically, have now reached entanglement rates up to 200 Hz [6][7][8][9][10][11][12] . Superconducting systems have established direct exchange of quantum information over cryogenic microwave channels [13][14][15][16][17][18] , which is particularly useful toward interconnects of intermediate range such as between dilution refrigerators. Yet, in the context of superconducting qubit based processors, none of these methods are likely to outperform local gates between qubits, which can achieve coupling rates in the tens of MHz and fidelities reaching 99.9% [19][20][21][22][23] . Importantly, modules consisting of closely spaced and directly coupled separate physical dies retain many of the benefits of distributed modular architectures without the challenge of remote entanglement. Increased isolation between modules reduces cross-talk and correlated errors, for example due to high energy background radiation [24][25][26] , and by fabricating smaller units and selecting the highest yielding units for device assembly, higher device yield is achievable 27,28 . Mastering 3D integration and modular solid state architectures has thus been a long-standing objective [29][30][31] .
We demonstrate herein a modular superconducting qubit device with direct coupling between physical modules. The device, which consists of four eight-qubit integrated circuits (QuICs) fabricated on individual dies and flip-chip bonded to a larger carrier chip, achieves coupling rates and entanglement quality approaching the state-of-the-art in intra-chip coupling.

Design of a modular superconducting qubit device
The multi-die device assembly is constructed through flip-chip bonding of four nominally identical dies to a larger carrier die as shown in Fig. 1a. The carrier chip assumes a similar role to the chip multiprocessor in a classical multi-core processor while also providing microwave shielding, circuitry to interface between the individual QuICs and signal routing for the device I/O. The smaller individual dies comprise the QuICs, each consisting of four flux tunable and four fixed transmon qubits 32 , and corresponding readout resonators and flux control lines as shown in Fig. 1b. The readout is multiplexed with four qubits and resonators per readout line and qubits are driven through the readout on this test platform. Qubits are labelled with a letter for the die position from left to right and a number for the qubit position within the die, e.g., B6. Entangled pairs are labeled according to the adjacent qubits, e.g., B6-C1. The QuIC dies are designed to be identical in order to maximize fabrication yield and enable modular assembly. The benefits to fabrication yield are evident in considering the number of distinct permutations that exist for a single device assembly: for a wafer with 220 QuIC dies, there are over 2.2 billion possible unique device assemblies.
The device Hamiltonian is designed to enable two-qubit parametric gates [32][33][34][35][36] between pairs of qubits on separate dies (see Methods). Coupling between qubits on separate chips is mediated through capacitive couplers on the QuIC and the carrier side, resulting in a cross-chip, charge-charge interaction. The carrier chip contains couplers with paddles at each end which are positioned below similar paddle-shaped couplers extending from the qubits on the QuIC as shown in Fig. 1a. This is similar in concept to the vacuum gap capacitors used in superconducting lumped element LC resonators 37,38 and in coupling qubits to resonators 39 . There is no intentional coupling between qubits on the same die in this test platform so as to isolate the basic interchip coupling mechanism and avoid complexities arising from larger circuits such as frequency collisions and leakage. However, the qubit and coupler design can be adapted to a larger lattice with intra-chip connectivity.

Device fabrication, assembly, and validation
The QuIC chips are fabricated using standard lithographic techniques on a Si wafer, which is then diced to create individual dies. The Josephson junctions which form the SQUID loops of the transmon qubits are fabricated through double-angle evaporation of Al. Superconducting circuit components, including the Al pads for the Josephson junctions and Nb ground planes, signal routing and coplanar waveguides and resonators, are fabricated by pattern, deposition and lift-off steps 40 .
Flip-chip bonding of the carrier and QuIC modules is accomplished through the deposition and patterning of indium bumps of height 6.5 μm and 40 μm diameter onto the carrier chip. The QuIC chips are flipped and aligned to the carrier before thermo-compression bonding, creating a superconducting bond between the carrier and QuIC chips. The fabrication process is described in detail in the Methods section. The indium bump heights post-bonding determine the vertical separation between the QuIC chips and carrier, as shown in Fig. 1a.
Importantly, the capacitance between the carrier and QuIC paddles is inversely proportional to the height of the indium bump bonds, h, as expected for a parallel plate capacitor. The bare coupling rate between qubits, g is directly proportional to this capacitance and thus follows the same dependence on h. Due to bonding process variation, the indium bump height spans a range of 1.5-4 μm. As shown in Fig. 2, this corresponds to a range for g of 8.8-26.1 MHz for the coupling rate.
Despite the range of anticipated couplings, the simulated fidelity for parametric gates in this design is relatively unaffected. Figure 2 shows simulation results of both the parametric CZ unitary gate error in the absence of loss and dephasing channels (coherent error) and the coherence-limited gate error (incoherent error) as a function of the bump height. The incoherent error is obtained assuming an ideal coherent exchange between the qubits while the coherent error takes into account the unwanted interactions arising from the capacitive coupling and flux modulation. For the coherence-limited fidelity calculation, we use a relaxation time, T 1 , of 73/18 μs and a dephasing time, T 2 , of 43/15 μs for fixed/tunable qubits. Over the full range of indium bump height expected from the bonding process, the predicted maximum achievable fidelity (taken as the minimum of the coherence-limited and unitary fidelity) varies from just under 99.0-99.5%. For an initial proof of concept, this range is acceptable; however, to push toward fidelities exceeding 99% or to employ this as part of a tunable coupler scheme 41,42 , efforts will be needed to reduce the spread. Additional calibration of the force applied during the bonding process and design revisions to reduce the sensitivity of the coupling to bump height by changing the paddle geometry could reduce this variation further for gate schemes requiring a tighter tolerance. While attaining the required accuracy could be a challenge, we note that achieving higher coupling rates (higher than our targets here, which are limited by ZZ coupling) is in fact easier than with standard 2D (lateral) capacitive coupling, requiring simply increasing the paddle widths or reducing the target bump height.
The device assembly, designed and fabricated as described above, is measured in a dilution refrigerator at 10 mK. To assess the accuracy of the simulations and modeling conducted during device design, we characterize the device Hamiltonian (qubit and resonator frequencies, and coupling rates between elements) and compare with predictions from simulation. Qubit frequencies are within 2.1% of predicted values for the f 01 transition and 11% for the qubit anharmonicity at zero applied flux bias (see Methods), demonstrating good agreement and indicating the inter-chip coupling technology does not impact the steady-state device physics in an unexpected manner.
Experimental determination of the bare coupling rates The capacitive coupling formed by the inter-chip couplers results in a charge-charge interaction between the coupled qubits, q 1 and q 2 . In the dispersive regime, where the detuning between qubits is large compared to the bare coupling rate (given here in radial units, g ¼ 2πg), jω 01;1 À ω 01;2 j )g, we can calculate the bare coupling rate from the measured dispersive shift, χ qq . The relationship between χ qq andg is given by Eq. (1) for the general case of two flux-tunable transmons, which differs from the treatment of transmon-resonator dispersive shifts. Note here we are working in the transmon limit and the equation below is the result of a perturbative expansion of the Hamiltonian eigenstates and eigenenergies as a function of applied magnetic flux, following the treatment in ref. 35 . E J,eff (Φ) is the effective Josephson energy of the DC-SQUID, a function of the applied magnetic flux through the SQUID, Φ, and is defined, along Schematics (not to scale) illustrating the multi-core architecture. a Isometric view of the device assembly. The qubits (blue circular structures) are fabricated on the QuIC die and have one arm with a paddle-shaped coupler extending to the edge of the chip. The chips are flip-chip bonded onto the carrier chip using indium bump bonds (yellow) and the qubit couplers are aligned above couplers on the carrier chip (teal) as shown in the inset as well as the cross-sectional view. b False-colored schematic of a single QuIC including readout resonators and readout lines (magenta and green), indium bumps (yellow), flux bias lines (orange) and the qubits and paddles of the inter-chip couplers (blue). The physical qubits are labelled 0-7 while Roman numerals correspond to the design specification for the qubit (see Methods). Note that component geometries are not drawn exactly as fabricated: the schematic is intended primarily to depict the circuit layout as opposed to details into individual feature geometries.

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(1) (2) We measure the dispersive shift through time Ramsey measurements taken with the tunable qubit biased at its maximum frequency. In our modified time Ramsey measurement, an X/2 pulse is applied to a qubit, q 1 , causing the qubit to precess about the equator. After a time delay, Δt, a Z pulse is applied which rotates the qubit through a phase ϕ = 2πΔtδf, where δf is the detuning of the pulse frequency relative to the qubit frequency, f 01 (the application of the Z pulse is a slight modification on the standard Ramsey sequence of an X/2 pulse followed by a delay and another X/2 pulse which enables better signal visibility)). Finally, another X/2 pulse is applied and the qubit state is measured. The resulting excited state visibility oscillates as a function of the time delay, reaching full visibility when the Z rotation perfectly offsets the phase accumulated from the precession during the delay time. From the period of the oscillations, the difference between the qubit frequency and the applied pulse frequency (already detuned from the expected qubit frequency by δf), and by consequence the qubit frequency itself as the applied pulse frequency is well defined by the control electronics, can be determined with high precision.
To measure χ qq , the time Ramsey measurement is performed on a qubit q 1 with adjacent qubit q 2 in the ground state and again in the excited state. The difference between the f 01 measured for q 1 at both points gives a precise measurement of χ qq . The measurement is then performed in the opposite direction, with the state of q 1 varied while the frequency of q 2 is measured. The bare coupling rate calculated from the dispersive shift, as given by Eq. (1), should be equivalent in both directions for a pure ZZ interaction, to within the error of the measurement. While the design target for all couplers was 12 MHz for a 3 μm indium bump height post-bonding, the observed coupling rate varied across the chip from 13.26 ± 0.59 MHz to 18.94 ± 0.39 MHz (see Fig. 2). This was within the anticipated range due to indium bump height variation (see Methods for further details, in particular Table 1).

Cross-chip entangling gate performance
We calibrated and benchmarked gates on ten out of twelve interchip pairs. The remaining two pairs could achieve population transfer but due to frequency targeting error in the fabrication process, the gate modulation frequencies were outside of the frequency band of the control electronics and degraded AC flux control resulted in low fidelity. The primary benchmarking methods employed were twoqubit randomized benchmarking (RB) and interleaved randomized benchmarking (iRB) 43,44 . We quote the estimate from iRB when the RB protocol estimates an average gate fidelity of F RB ! 92%, which bounds the iRB estimate to at most 20% of the reported gate error due to imperfect gate randomization 43 . Below this empirical threshold, the assumptions of the error model can lead to large uncertainty and an overestimate of the gate fidelity for iRB. Table 2 provides a summary of the CZ gate fidelities measured for each of the ten pairs and compares them with the coherence limited fidelity (the maximum achievable fidelity predicted from the measured relaxation and dephasing times of the qubit pair). The coherence limited fidelity is computed from the T 1 and T 2 under modulation, e T 1 and e T 2 , ie. the coherence times as measured while an AC flux bias is applied to the tunable qubit at the gate modulation frequency, emulating conditions during gate operation. e T 1 and e T 2 for the tunable qubit in each pair, the limiting qubit in regards to coherence, are also recorded in the table.
Comparing the measured fidelities with the coherence limited fidelities, the fidelity is almost always limited by the qubit coherence suggesting the inter-chip coupling mechanism does not limit gate error directly. Furthermore, we have compared qubit coherence times for inter-chip-coupled qubits to a baseline of similar qubits that are not coupled by inter-chip couplers and coherence times do not appear to be limited by the inter-chip coupling technology itself (see Methods). This suggests that gate fidelities are limited by the same sources of error arising in monolithic devices and are not directly, or indirectly through impacts to qubit coherence, negatively impacted by the inter-chip coupling technology.
Apart from four gates with two level systems which could explain the increased dephasing under modulation, CZ gate fidelities were above 90% with 5 out of 12 gates demonstrating >95% measured fidelities. While Table 2 lists only CZ fidelities as CZ gates were within the AC flux control band for all pairs and they allowed a straightforward comparison to the coherence limited fidelity, the maximum gate fidelity measured was a 99.1% ± 0.5% iRB for an iSWAP gate on the C1-D6 pair, which we expand upon in Fig. 3.

Multi-die bell inequality violation
We now turn our attention to assessing the viability of a future modular quantum processor based on these techniques.
Importantly for this analysis, the inter-chip connections on our test device are established by unique qubits, and, in addition, qubits fabricated on the same chip are not coupled. We thus investigate the simultaneous quality of two-qubit connections, for the three disjoint pairs. This step is important for assessing functional challenges toward leveraging non-local quantum states in larger scale algorithms. Following a tradition established for multi-node or modular experimental efforts in superconducting qubits 28,[45][46][47] , we design a test for the deterministic violation of a Bell inequality with this inter-chip platform. We describe a figure of merit hW Σ i ¼ P k hW k i, where W k is a witness to entanglement of connection k, applying the standard Bell observable for two-qubits, with Q = Z n , R = X n , S ¼ XmÀZm ffiffi and signal above hW Σ i > 2N certifies that the network supports genuine entanglement over at least one connection simultaneously. Moreover, investigating the individual Bell signals 〈W k 〉 can test entanglement over each connection independently.
Our experimental procedure is shown in Fig. 4. We choose three connections that bridge all four chips in a disjoint pattern (A0-B7, B0-C7, C1-D6). We prepare the three pairs in an equal superposition of two-qubits: . Then, we measure the qubits in the 〈ZZ〉 basis or 〈XX〉 basis. A total of 100 experiments were run, having 10 4 shots per basis, collecting measurement data simultaneously for all pairs. A summary of results is in Table 3, where all three connections violate the Bell test by at least three standard deviations. With high confidence, therefore, the test platform supports simultaneous disjoint, pair-wise entanglement involving all four chips. In addition, our total figure of merit, hW Σ i ¼ 6:651 ± 0:067 exceeds the classical bound by nearly ten standard deviations.

DISCUSSION
Concluding, we demonstrate that the flip-chip bonded, multi-die fabrication process with inter-chip coupler technology is capable of achieving high fidelity entanglement, including gate fidelities regularly exceeding 95% and up to 99% in the best case, and simultaneous entanglement between silicon dies violating the Bell test by over three standard deviations.
Future work should explore the potential benefits of this modular approach beyond the intrinsic advantages in regards to flexible device construction and yield. This includes increased isolation between qubits on separate physical die, an important factor particularly in developing robust hardware  suitable for near-term error correction schemes. Recently, the impacts of cosmic and background radiation on solid state devices have been of significant interest due to the correlated errors that result and the challenge these pose to fault tolerant quantum computing [24][25][26] . In this case and more generally, the physics of quasi-particle trapping and phonon propagation through superconducting qubit chips would be interesting to explore on multi-die devices. Phonons should collect on the boundaries of the individual die and not propagate to qubits on other dies, reducing correlated errors. In addition, while the use of indium bump bonds means we cannot replace individual QuICs post-bonding, this modular architecture would have even higher yield benefits if QuIC selection could be done after measuring the QuICs cold, instead of after room-temperature metrology. This type of flexibility, which could come from either having a test set-up for individual QuICs or a configurable interconnect between the carrier die and QuICs, is also an interesting avenue for future study.
Finally, we note that the true impact of this technology will be in its integration with state-of-the-art processing architectures. With additional intra-chip circuitry and changes to the qubit topology on the individual QuICs, this technology can be extended to form a seamless modular quantum processor that is flexible in regards to the number and type of modules integrated and, with sensitivity to fabrication yield and intra-die cross-talk limited only by the module size, highly scalable. By enabling the fabrication of devices consisting of hundreds to thousands of qubits which are sufficiently isolated to mitigate correlated errors, this technology provides a clear path forward toward fault tolerant computing.

METHODS Fabrication and bonding process
The carrier chip is composed of cavities etched in Si, coated with patterned superconducting metal, and indium bumps (deposited outside of the cavities on the flat outermost surface) which after bonding form the superconducting connection between carrier and QuICs. Carrier chips are fabricated from high resistance Si wafers. The fabrication flow starts with a photolithography process to create cavity patterns on wafers followed by a Bosch etch (DRIE) step to fabricate 24 μm deep pockets with vertical sidewalls. The surface is then conformally coated with a 560 nm-thick Nb/MoRe stack, deposited by sputtering (PVD), to form a continuous superconducting shield. Vertical cavity sidewalls are confirmed to have a continuous metal film connecting the top surface to the cavity bottom surface. A thin layer of MoRe alloy is deposited on top of Nb film to seal the Nb surface, enabling an oxide-free metal-tometal interface for reliable electrical connection between the Nb device layer and the In bumps in the bonding areas.
The metal film stack is then patterned by a two-plane photolithography process followed by a reactive ion etching (RIE) step with a certain etching selectivity to the Si substrate. During the first exposure, focus and dose settings are selected to target the top wafer surface patterning, while in the second exposure settings are changed to target the cavity bottom surface only, which is 24 μm deeper. Once the Nb/MoRe stack etching is completed, a negative-tone photoresist lithography is used to transfer the In bump patterns onto the top metal surface by lift-off processing 48 . Electron-beam evaporation is used to deposit a 6.5 μm thick indium layer, producing a high quality, easy to lift-off film. An automatic lift-off tool that uses a combination of chemical cleaning and physical energy produced by high-pressure jets removes the In film from non-patterned areas, completing the process. No Josephson junction fabrication steps are required as no active components are located on the carrier chip. Future designs could include transmons in the carrier chip as part of, for example, a quantum bus to provide longer-range bus coupling between qubits instead of the direct coupling employed in this initial design.
To establish a superconducting connection between the carrier chip and the four separate QuIC chips, a flip-chip bonder is used. Each QuIC device is precisely aligned and thermo-compression bonded to the carrier chip. Prior to bonding, both carrier and QuIC chip surfaces are solvent cleaned followed by an atmospheric downstream plasma cleaning to chemically clear surfaces of native oxides. This process also temporarily passivates the In bumps from oxidation and helps to generate a strong chemical bond between In bumps and the corresponding pads. The multi-chip bonding process consists of sequential bonding of four separate QuICs to the designated locations on the carrier chip. For each bonding, the carrier and QuIC chips are aligned to each other with a horizontal accuracy of better than ± 2.5 μm. After the horizontal alignment is completed, a vertical parallelism adjustment is done using autocollimation and laser-levelling methods with an accuracy of ± 0.5 μm. The ensuing thermo-compression process consists of three different phases. In the first phase, force and temperature values are gradually increased and stabilized. In the second phase, the actual thermo-compression bonding takes place for two minutes. To prevent thermal aging of QuICs that are already bonded, the carrier chip temperature is maintained at 30 ∘ C, while the QuICs are heated to 70 ∘ C only during bonding. In the final phase, the stack is cooled to 30 ∘ C with a nitrogen flow. The same process is repeated sequentially for all the QuICs.

Device hamiltonian and parametric gates
To design the device Hamiltonian, the circuit parameters were extracted using quasi-static electromagnetic simulations and a positive second order representation 49 was used to solve the linearized circuit. The nonlinear effects of the Josephson junctions are subsequently accounted for through a perturbative treatment. The designed Hamiltonian parameters for this device are provided in Table 4, including the maximum and minimum f 01 transition frequencies over the flux bias tuning range, the anharmonicity at the maximum of the tuning range, η ¼ f 12;max À f 01;max , the frequency of the readout resonator coupled to the qubit, f RO , and the qubit-readout resonator dispersive shift, χ q,RO . The coupling rate between qubit pairs was designed to be 12 MHz at a 3 μm indium bump height for all couplers.
Due to fabrication process variation, the Josephson junction width, and hence the Josephson energy, of each fabricated junction will differ slightly from the design target. Using the relationship between the room temperature conductance of a junction and its Josephson energy at cryogenic temperatures 50 , a more accurate prediction for the device Hamiltonian can be obtained for fabricated devices using the same modelling process as during the initial device design, but replacing the target EJ values with the predicted EJ values from room temperature conductance measurements. Changes to the Josephson energy of the single junction in a fixed transmon or the two junctions in a DC-SQUID tunable transmon primarily impact the qubit frequencies, with little impact on qubit anharmonicities, readout resonator properties, or coupling rates.
We plot in Fig. 5 the design target, predicted and measured f 01;max , demonstrating agreement between the predicted frequencies and those measured cold, to within ± 108 MHz or 2.2% in the worst case. The discrepancies are within the prediction error we expect due to uncertainty in the empirically determined linear coefficient relating room temperature conductance to inductance at cryogenic temperatures, and uncertainty in  the conductance measurement itself. The qubit anharmonicities are compared with the design target and are accurate to within 11%, demonstrating a systematic offset that will be corrected in future designs. The device Hamiltonian is designed to enable parametric gates between one tunable (T) qubit coupled to one fixed qubit (F). In this scheme, an AC flux bias at RF frequency f p is applied to the tunable qubit around its parking flux bias. Under flux modulation, the transmon frequency oscillates at harmonics of the modulation frequency around its time-averaged frequency f T ;01 . Transmon frequency modulation gives rise to sidebands at frequencies f T;01 þ kf p , separated by the modulation frequency around the average frequency. When the modulation frequency is tuned such as to align one sideband with the transition frequency of the fixed qubit, a coherent exchange takes place between the two qubits at a rate equal to the bare coupling strength renormalized by the sideband weight. When the tunable qubit is parked at the maximum of the tuning band, only even sidebands have a non-zero weight and the sideband k = ± 2 is used. Entangling gates are then enacted by modulating the tunable qubit at half the average detuning between the qubits' transition frequencies. To obtain the iSWAP gate, the interaction between states 01 j i and 10 j i is activated at the modulation frequency f p ¼ jf T;01 À f F;01 j=2 Δ=2 (with the convention FT j i). For the CZ gate, the interaction between 11 j i and 02 j i is activated at f p = (Δ + η T )/2 (CZ 02 ) or between 11 j i and 20 j i at f p = (Δ − η F )/2 (CZ 20 ). The gate time is adjusted to provide a π rotation for iSWAP and 2π rotation for CZ between the corresponding two-qubit states.

Analysis of bump heights and coupling rates
After cryogenic tests were complete, the indium bump heights were measured at various locations across the device. This was done in a destructive manner by shearing the chip to separate the QuIC and the carrier chips, then measuring the indium bump diameter, as shown in Fig.  6. Working under the assumption that before and after bonding the indium bumps are approximately cylindrical in shape, and with the diameter and height known before bonding, the diameter as measured after shearing provides an estimate for the bump height post-bonding. The measured coupling rates could then be compared with post-hoc simulated coupling rates computed for each coupler based on the measured bump heights. We obtain qualitative agreement between the simulated and measured coupling rates, however the measured coupling rates are~20% lower than expected from design. Future studies will look to address this discrepancy. Some of the reasons for the latter are the overestimation of the bump height size and inaccuracies in material properties assumed in the simulation. In addition the measured coupling values are effectively reduced by a term representing the next-nearest neighbor couplings to resonators, which exist in a higher band than the transmons. Fig. 5 Comparison of predicted and measured transition frequency, f 01 and anharmonicity, η at zero applied flux bias. Note that while the design target is constant from one die to the next (all dies are designed to be identical), small variations in the predicted and measured qubit frequencies are present due to fabrication process variation, which can be measured at room temperature. Good agreement between the predicted and measured qubit frequencies, to within ± 108 MHz, is obtained. Anharmonicities show a systematic offset from the design targets but are still within 11% of the target value. Error bars on the predicted values represent the standard deviation in the values obtained from a Monte-Carlo simulation where the expected variation in the simulation inputs is accounted for (room temperature metrology error, error in the qubit charging energy, etc). Fig. 6 Magnified image of a region of the carrier chip. This image shows the indium bumps post-bonding and post-shearing, a destructive process whereby a cut is made through the device separating the QuIC chips from the carrier chip. The diameter and height of the indium bumps are known pre-bonding, such that by measuring the bump diameter post-bonding, a rough estimate for the bump height can be obtained assuming the bump is cylindrical in both cases: h post ¼ h pre D pre =D post À Á 2 . Fig. 7 Comparison of T 1 and T 2 for qubits with inter-chip coupling (inter-chip) compared to qubits on devices from similar wafers without inter-chipcouplers (baseline). The baseline data includes 4 fixed qubits and 27 tunable qubits while the inter-chip data includes 12 fixed and 12 tunable qubits, and for each qubit the measured values are averaged over several measurements taken over the course of a week. The boxes plotted depict the four inter-quartile ranges for the distribution of average values with outliers shown as hollow circles. Tunable qubits have lower T 1 and T 2 due to the coupling of the flux bias line to the qubit and are thus plotted separately here. Fig. 8 Timeseries of the iRB fidelity and T 1 of the tunable qubit on the C1-D6 pair. The tunable qubit has a lower T 1 relative to the fixed qubit on the edge and is thus the limiting factor in regards to incoherent error. The repeated measurement sequence calibrates readout parameters, parks the tunable qubit at its maximum frequency, measures the coherence time and benchmarks the gate. Error bars represent the 95% confidence bounds on the fitted parameter (fidelity and T 1 ) for each measurement.

Impact of inter-chip couplers on qubit coherence and 2Q gate stability
An important question to address is whether inter-chip coupling exposes qubits to additional loss or dephasing channels relative to standard intra-chip lateral couplers. As the electric field between the paddles of the coupler passes through vacuum rather than a silicon substrate, no additional dielectric losses are expected. Furthermore, the galvanic connection across the carrier chip is small enough relative to the 3-8 GHz band of interest that it can be treated as a lumped element and is not expected to produce any additional resonant coupling between qubits and the electromagnetic environment (chip modes, package modes, etc.) up to frequencies in excess of 15 GHz. It is thus not expected that these couplers should impact the qubit relaxation (T 1 ) or dephasing (T 2 ) times. This was reflected in experimental results, as shown in Fig. 7 where we compare T 1 and T 2 for a device with interchip coupling compared to devices from similar wafers with no coupling at all. No statistically significant difference in the T 1 and T 2 times was observed relative to the baseline.
In addition to comparing the coherence between inter-chip qubits and intra-chip qubits, we also assess the entangling gate stability and relaxation time, T 1 over a period of 24 h, as plotted for the C1-D6 pair in Fig. 8. For each data point plotted, the qubits are re-tuned, readout is calibrated, and the two-qubit gate is benchmarked using interleaved RB. Qubit re-tuning is done by parking the tunable qubit at its maximum frequency and calibrating the gate pulses for the fixed and tunable qubit. Readout calibration involves preparing ground and excited states to update the classifier that will be used to discriminate single shot measurements. T 1 decay is monitored through repeated coherence measurements taken after re-tuning and readout calibrations and before benchmarking. Temporal fluctuations show a drop in the gate fidelity when the T 1 falls below 10 μs, but generally it remains stable to within four percentage points with a distribution centered around 98%. Fluctuations in T 1 is an active research topic in the field of superconducting qubits 25,26 .