Semiconductor spins are one of the few qubit realizations that remain a serious candidate for the implementation of large-scale quantum circuits. Excellent scalability is often argued for spin qubits defined by lithography and controlled via electrical signals, based on the success of conventional semiconductor integrated circuits. However, the wiring and interconnect requirements for quantum circuits are completely different from those for classical circuits, as individual direct current, pulsed and in some cases microwave control signals need to be routed from external sources to every qubit. This is further complicated by the requirement that these spin qubits currently operate at temperatures below 100 mK. Here, we review several strategies that are considered to address this crucial challenge in scaling quantum circuits based on electron spin qubits. Key assets of spin qubits include the potential to operate at 1 to 4 K, the high density of quantum dots or donors combined with possibilities to space them apart as needed, the extremely long-spin coherence times, and the rich options for integration with classical electronics based on the same technology.
The quantum devices in which quantum bits are stored and processed will form the lowest layer of a complex multi-layer system.1,2,3 The system also includes classical electronics to measure and control the qubits, and a conventional computer to control and program these electronics. Increasingly, some of the important challenges involved in these intermediate layers and how they interact have become clear, and there is a strong need for forming a picture of how these challenges can be addressed.
Focusing on the interface between the two lowest layers of a quantum computer, each of the quantum bits must receive a long sequence of externally generated control signals that translate to the steps in the computation. Furthermore, given the fragile nature of quantum states, large numbers of quantum bits must be read out periodically to check whether errors occurred along the way, and to correct them.4 Such error correction is possible provided the probability of error per operation is below the accuracy threshold, which is around 1% for the so-called surface code, a scheme which can be operated on two-dimensional (2D) qubit arrays with nearest-neighbor couplings.5, 6 The read-out data must be processed rapidly and fed back to the qubits in the form of control signals. Since each qubit must separately interface with the outside world, the classical control system must scale along with the number of qubits, and so must the interface between qubits and classical control.
The estimated number of physical qubits required for solving relevant problems in quantum chemistry or code breaking is in the 106–108 range, using currently known quantum algorithms and quantum error correction methods.7, 8 For comparison, state-of-the-art processors contain more than one billion transistors (http://www.intel.com/pressroom/kits/quickreffam.htm). Furthermore, the structure of these transistors bears a lot of resemblance with that of promising semiconductor-based qubits.9, 10 However, an important difference is that conventional processor chips have only ≈103 input-output connections (IO’s), for instance Intel’s land grid array 2011 socket has 2011 pins that contact the backside of the processor (http://www.intel.nl/content/www/nl/nl/processors/core/core-i7-lga-2011-datasheet-vol-1.html). This brings the transistor-to-IO ratio over 106. This scaling of the number of pins with the number of devices is empirically described by Rent’s rule.11, 12 In the absence of multiplexing or on-chip control logic, the limit for the qubit count is probably similar to the pin-limit of the package, which is currently around 103 (http://www.intel.nl/content/www/nl/nl/processors/core/core-i7-lga-2011-datasheet-vol-1.html).
Therefore, the notion that semiconductor quantum bits that are manufactured by complementary-metal-oxide-semiconductor (CMOS)-compatible technology are easily scalable, is too simplistic. While many qubit architectures and strategies for scaling have been proposed,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40 a completely worked out pathway to create qubit systems that can be expanded to a large-scale quantum processor yet has to be defined and a key step is the design of a scalable classical-quantum interface.
Here, we focus on the quantum-classical interface requirements and possible solutions for qubits encoded in electron spins in semiconductor quantum dots and donors.9, 10 We thereby consider specifically quantum dots that are probed and controlled using electrical signals, referring to ref. 1 for a discussion of optically addressed quantum dots. Electrically controlled quantum dots and donors are two promising qubit realizations that have much in common both conceptually and in terms of qubit specifications and hardware requirements. There is significant scope to make these realizations compatible with industrial CMOS technology, which is optimized for high-yield, reproducibility and cleanliness. Indeed, there is a lot of effort in this direction and qubits that are partly fabricated with industrial technology have already been realized.41
We begin with a brief summary of electron spin qubits in quantum dots and donors, then derive the control signal requirements and challenges, and next present possible solutions to overcome these challenges. These focus on dense 2D tunnel coupled spin qubit arrays, sparse arrays with coherent links between them, and on the possibility of operating spin qubits at 1 or 4 K, allowing for more complex electronics to be integrated with the qubits.
Electron spin qubits in quantum dots or donors
We first briefly introduce electron spin qubits in electrically detected quantum dots and donors as a starting point for discussing the control and interfacing requirements (for more extensive reviews, see refs 9, 10).
A schematic of a prototypical quantum dot device is shown in Fig. 1a. A combination of bandgap offsets and electrostatic gates are used to confine one or more free electrons (or holes41,42,43; for brevity we will refer to electrons throughout the text) in a small space in a semiconductor, typically a few tens of nm in diameter. For qubit experiments, the gate voltages are usually tuned so the quantum dots contain exactly one electron each, although for certain initialization and read-out protocols, an electron is pushed off a dot or onto a neighboring dot. Figure 1b shows a schematic of a donor-based device. Donor atoms such as phosphorous in silicon have one excess electron compared to the atoms in the surrounding lattice, and at low temperatures this electron is bound to the donor atom (acceptors with one excess hole can be used as well; we will just refer to donors for brevity). With a gate voltage, this electron can be pushed off the donor or a second electron can be bound to the donor, provided the required electric fields are below values that result in population of the silicon conduction band (or valence band in case of acceptors). In both cases, an additional gate can be placed in between or close to adjacent sites in order to control the tunneling of electrons between the sites via a gate voltage, a crucial ingredient of most electron spin qubit proposals.13, 14 Qubit experiments with such systems have been performed so far with the sample attached to the mixing chamber of a dilution refrigerator, at operating temperatures of 10–100 mK.
The canonical encoding of a qubit in these systems is in the spin split levels, and , of the electron on each site, in the presence of a static magnetic field.13, 14 However, alternative encodings have been proposed theoretically and explored experimentally, whereby specific collective spin states of two or three electrons in two or three quantum dots are used to represent and , see Fig. 2.44,45,46,47,48 For each of these encodings, direct current (DC) voltages may be used to fine tune qubit transition frequencies. This is immediate for the encodings based on two or three electron spins, where qubit splittings are directly set by gate voltages. Also for single-spin qubits, the spin splitting is typically sensitive to electric fields.49,50,51
Regardless of the chosen qubit encoding, one generally requires the ability to individually rotate every qubit about two different axes in the corresponding qubit Bloch sphere, and to entangle neighboring qubits with each other; see Fig. 2 for rotation axes of different qubit encodings. Altogether, this forms a universal set of quantum gates, which can be used to perform arbitrary logic.52 Both single-qubit and two-qubit gates can be accomplished in one of two modes: (1) fast gate voltage pulses that rapidly switch the Hamiltonian so that the qubit(s) will start evolving around a new axis (in Hilbert space) or (2) radio-frequency or microwave-frequency electric or magnetic fields resonant with the energy difference between specific single- or two-qubit states. Gate durations vary from sub-ns to microsecond timescales.9, 10
Spin states are hard to detect directly, but can be converted to charge states via a sequence whereby a charge movement between dots or from a dot to a nearby electron reservoir is made to be spin state dependent, via “spin-to-charge conversion”.53, 54 Simultaneous single-charge detection then reveals what the spin state was before the measurement. Real-time single-charge detection can be accomplished in several ways. In the first method, the conductance through a nearby charge detector is probed, either at baseband55 or via radio frequency (RF) modulation.56 The charge detector can be a narrow channel called quantum point contact (QPC) or a small island that itself is capacitively coupled to the quantum dot or donor. In either case, the conductance through it directly depends on the charge occupation of the dot or donor (see Fig. 1a, b). Alternatively, the ability of charges to move back and forth in response to an oscillating excitation can be probed. This amounts to an electrical susceptibility measurement, which is commonly implemented by looking at the reflection of an RF signal applied to one of the quantum dot gates57 or reservoirs.58 Single-shot measurement times down to 200 ns have been achieved in specific settings,59 and read-out fidelities as high as 99.8% have been reported.60
Qubit reset or initialization could be achieved by thermalization to the ground state, but that would be very slow given that spin relaxation times are often in the millisecond to second range.9, 10 Faster approaches include initialization by measurement52 and spin-selective tunneling from an electron reservoir or dot to a dot or donor.54, 61, 62
Finally, we note that microscopic variations in the semiconductor substrate and non-uniformities in the gate patterns lead to substantial variations from site to site in a realistic device. While progress has been made and high-quality double quantum dots have been reported,63 an attractive but challenging solution would be to reach a uniformity level where a common (set of) DC voltage(s) would suffice to place each of several quantum dots in the desired configuration; for example, systematically having a dot-to-dot variation in required gate voltage for single electron occupancy smaller than the charging energy. Donor fabrication introduces more challenges, but the strong confining potential can have specific advantages here due to the intrinsic large energy scales. Fabrication based on scanning-tunneling-microscopy64 as compared to ion implantation has the further advantage that uncertainties in donor placement and capacitive coupling to nearby stray donors are significantly reduced. However, a systematic study on the relevant variations for a large array is missing. Furthermore, nominally identical operations currently require DC gate voltages, gate voltage pulses, and microwave control signals that all differ in amplitude or duration from qubit to qubit.
Control signal requirements
The discussion of electron spin qubits in quantum dots or donors leads us to the following commonly recurring requirements for the control signals. As can be seen from Fig. 2, not all requirements apply to each of the encodings, and this can be a criterion for comparing the merits of different encodings with each other.
an independently calibrated and tuned DC gate voltage on every site (typically up to ±1 V)
independently calibrated and tuned gate voltage pulses on every site (typically up to tens of mV and with sub-ns rise times)
independently calibrated and tuned microwave magnetic or electric fields at every site (typically −40 to −20 dBm, 1–50 GHz bursts of 10 ns to 1 μs duration)
a high precision of each of the control signals to achieve error rates comfortably below the 1% accuracy threshold
initialization, operations and read-out on timescales short compared to the relevant decoherence time.
We now examine some of these requirements in more detail, and in particular consider which requirements can be relaxed. In the next section, we will present some general guidance for meeting the necessary requirements.
For the pulsed control signals, often only one of the two pulse stages requires precise tuning. For instance, the precise strength of the exchange interaction is important when the exchange is turned “on”, but the exchange strength in the “off” state merely needs to be below some threshold, which is a much more relaxed constraint. The exchange is commonly controlled by changing gate voltages along the so-called detuning axis that controls the relative potential of neighboring dots (see Fig. 2). To reach the “off” state, it suffices to pulse gate voltages to a sufficiently far detuned condition. Similarly, when performing exchange gates at the so-called symmetry point (see the caption of Fig. 2), it suffices to pulse the gate voltages to any condition where the residual exchange is sufficiently suppressed, though this may require larger voltage amplitudes than when pulsing the detuning. Similarly, accurate level alignment is needed during read-out of a single spin based on spin-selective tunneling to a reservoir,54, 62 but when not reading out it suffices to stay in the regime with one electron per site. Spin read-out of two-electron spin states is typically even more forgiving, as it suffices to pulse from somewhere deep in the regime with one electron on each dot, to somewhere in the so-called pulse triangle with two electrons on one of the dots.65, 66 Therefore, one could imagine that voltage pulses to, say, control exchange gates or initiate read-out can be made uniform across multiple (all) dots, by fine-tuning the exact qubit operating points via DC bias voltages. The main assumption in these examples is that the qubit is not sensitive to the exact DC gate voltage while in the “off” state. As the qubit transition frequency may in fact vary with DC gate voltage,49, 50, 67 unintentional single-qubit -rotations could occur and these must be tracked or corrected separately for every qubit.
For microwave control signals, we need to separately consider the microwave frequency vs. amplitude and duration. The simplest approach is to assume that all qubits will need to be resonant with either a single frequency or a small number of frequencies. This can be achieved by g-factor control or Stark shifting, through either DC or pulsed control voltages,49, 50 to bring qubits on specific sites in or out of resonance with the excitation. For conventional electron spin resonance (ESR) whereby a global microwave magnetic field is applied,49, 68,69,70 the same microwave can be used to achieve the same angle of rotation on multiple qubits provided the amplitude variations are sufficiently small and the resonance frequency of all qubits resonant with the excitation is sufficiently uniform. Uncontrollable spin-orbit coupling renormalizing the g-factor can give qubit-to-qubit variations in the resonance frequency of order 10 to 100 MHz at B = 1.5 T (ref. 67). A possible strategy to overcome such variations is operating at significantly lower magnetic field. Globally applied alternating current (ac) magnetics fields could give rise to excessive dissipation and heating, and the magnetic field profile may suffer from distortions due to all the metal interconnects. A strategy could be to integrate local microwave lines that are close to the qubits and only address subsections of the larger qubit array. Superconducting lines could further reduce dissipation.
For electric-dipole spin resonance, whether based on intrinsic spin–orbit interaction41, 71 or on local magnetic field gradients to allow electric fields to drive spin transitions,51, 72, 73 dot-to-dot variations in the confining potential may impose different microwave amplitudes for every qubit. All-electrical control is often argued to be beneficial because of fast and local control. Essential in the design will be the interconnection between the microwave source and the individual qubits. Power dissipation will be significantly reduced compared to ESR, but avoiding cross-talk will be challenging. A solution for cross-talk could include to spatially separate qubits with equal resonance frequency.
The main message from this technical discussion is that even though some requirements can be relaxed, especially if the quantum dot properties are homogeneous, at least a subset of signals (DC, pulsed, or microwave) will need to be independently calibrated and delivered to each and every qubit.
Control signal wiring solutions
How can we route qubit-specific classical control signals to a large number of quantum dot or donor qubits? The common understanding in the field is that directly connecting via wires or coax lines say 108 sub-100 mK qubits to room temperature voltage sources, pulse sources, and microwave sources, is impractical for several reasons. At the qubit chip level, it conflicts with Rent’s rule in classical systems11, 12 and practical limits to the number of pins on a chip. At the level of the transmission lines from room temperature to the chip, heat transport causes a heat load of a few mW on the 4 K plate. For comparison, cooling powers of currently used pulse tube systems are in the range of a few W at 4 K. Below 4 K, superconducting lines can be used, which are poor thermal conductors and thus minimize heat load, but power dissipated in the attenuators can heat up the coldest parts of the dilution refrigerator. A common view is that instead a combination of two ingredients will be required:
A first layer of classical electronics residing next to the qubits and commensurate with the inter-qubit spacing
Other layers of classical electronics may reside farther away from the qubit plane and at higher temperature, as the data rates between layers higher up in the quantum computer architecture are orders of magnitude smaller than those between the physical qubits and the first control layer.
Within this framework, important choices include
What qubit density to work with?
At what temperature do the qubits reside? Is operation at 1.5 or 4 K possible?
What is the functionality of the first electronics layer?
What specifications must the electronics meet (clock speed, noise, resolution, frequency range, memory, power dissipation)?
These questions are interrelated, for instance the qubit density and the cooling power (which depends on the temperature) impact the functionality and specifications of the electronics that can be achieved. We next discuss platforms based on a dense qubit array or a sparse qubit array, and an operation temperature ranging from 100 mK to 4 K.
Dense qubit array and cross-bar addressing
The most widely used mechanism for two-qubit gates using quantum dots is based on the exchange interaction.74,75,76 This interaction couples the spin states of two electrons when their respective wave functions overlap, i.e., when the respective dots are tunnel coupled.13 The two-qubit exchange gate is very fast: it can be operated on sub-ns timescales, limited in practice by the bandwidth of the control electronics rather than by the underlying physics. In the absence of nuclear spin noise that is mostly relevant in III–V quantum dots,9 the fidelity is often limited by electrical noise, usually charge noise from the amorphous materials and interfaces, and electrical noise on the gates. Coherent spin exchange between neighboring spins has been extensively realized in double dots as well as in linear arrays of three dots,9, 39, 77, 78 and scaling up a linear array to larger sizes is relatively straightforward.
Scaling to a large two-dimensional array of tunnel coupled dots presents a great opportunity for realizing highly dense qubit arrays, but also presents practical challenges to wire up all the qubits, given the geometric constraints. To make things concrete, in order to have sufficient tunnel coupling between neighbors in the array, the center-to-center distance between dots must be no more than a few 100 nm in GaAs, <100 nm for qubits defined in silicon (a result of the three times larger effective mass in Si), and <20 nm for donors (due to the strong confinement potential). Taking a 100 nm qubit-to-qubit pitch as an example, a 2D array of 1 mm2 would allow space for a massive 108 qubits. However, with at least one control line per qubit, fan-out of the control lines requires multiple layers of interconnects. If the interconnects and control lines can come from all sides, but have the same width as the quantum dots, a 4 × 4 array requires two layers (the first layer to contact the outer dots, the second to contact the inner dots), five layers are needed for a 10 × 10 array and 50 layers for a 100 × 100 array. There is clearly a practical limit to the size of a monolithic array that can be wired up in this way.
A possible strategy to partly overcome this fan-out problem is to borrow concepts from dynamic random access memory (DRAM). Rather than connecting every gate continuously to a voltage source, an individual gate is connected to a capacitor that stores the desired voltage. The voltages can be set efficiently via a cross-bar addressing scheme40 (Fig. 3). Given that a single electron charge e is the smallest amount of charge that can be added to the capacitor, the capacitance required to achieve a gate voltage resolution ΔV must be . For ΔV = 1 μV, this gives C > 160 fF. Furthermore, thermal noise in the circuit when the switch is closed translates to an uncertainty in the gate voltage given by , which is a function of the capacitance but independent of the circuit resistance. Reaching an uncertainty V rms = 1 μV at a temperature of 50 mK would require a capacitance larger than 800 fF. One challenge with this approach is the chip area required for such relatively large capacitances. Conventional planar approaches with 10 fF/μm2 are not compatible with the envisioned small dot spacing so that other solutions such as concentric pillar capacitors will be needed.
These charge-storage electrodes may have to be periodically refreshed, due to leakage or variations in the capacitive coupling to nearby structures. Such refreshing is routinely done in classical electronics. For instance, a typical refreshing interval time of DRAM is 64 ms where a refresh cycle is performed within 30 ns. If the 1% weakest electrodes can be excluded, the interval time can be extended to a second. While the tolerances of quantum dot voltages are much more stringent, leakage is strongly reduced at a few Kelvin or below, so such an approach might be feasible. Experimental drifts of approximately one Coulomb oscillation per hour ≈8 mV/h have already been observed in charge-storage electrodes integrated with quantum devices.79 However, more research is needed to demonstrate these drifts using electrodes that have a size comparable to the quantum dots and to minimize possible leakage pathways.
Globally controlling these floating electrodes could be done via an efficient cross-bar addressing scheme, using horizontal and vertical control lines that each have a spacing corresponding to the dot-to-dot distance. Assuming a dot-to-dot pitch of 50 nm, consistent with requirements for quantum dots, would imply an interconnect pitch of 50 nm, which is similar to what is possible with 14 nm node technology, the most advanced that is commercially available today (http://www.intel.com/content/www/us/en/silicon-innovations/intel-14nm-technology.html). Furthermore, 50 nm is below the 70 nm transistor gate pitch for the 14 nm node. Therefore, unless dot dimensions can be kept slightly larger, integrating a single transistor above every quantum dot requires continued scaling of conventional CMOS devices, dictated by Moore’s Law.
A cross-bar approach can also provide a relatively economical avenue for qubit control. For instance, we can apply a voltage pulse on one of the vertical lines (combined with the DC voltage required by that site via a bias-tee) and use the horizontal line to select to which qubit the pulse is applied. As discussed in the section of control signal requirements, it should be possible to allow the same pulse amplitude to induce an exchange gate or initiate read-out across multiple dots. In this case, parallel addressing of multiple dots will be possible, as well as addressing for instance all dots or half of the dots (any combination of dots compatible with cross-bar selectivity is possible). It has indeed been shown that the cross-bar approach can be used to run the surface code, both in donor and dot platforms.32, 40 It was also shown that surface code variations can be implemented with reduced local control.37, 38
Initiating parallel read-out is possible with a cross-bar approach as well, with vertical lines used to select the set of qubits underneath and horizontal lines used to carry the corresponding read-out signals. It may be possible to re-use the same cross-bar that is used for control, also for read-out, for instance using dispersive gate read-out.57 An RF signal is then applied to a vertical line (again added to a DC gate voltage) and the horizontal lines select the qubit that is read out. This procedure comes at a cost. In its simplest form, an array of N qubits requires repetitions of this read-out protocol to measure all the qubits.
This slow-down has two sides. First, it requires that probability of error of a qubit during read-out cycles stays far below the accuracy threshold. Here, the extremely long memory times of spin qubits under dynamical decoupling, of order one second,49, 69 are crucial. Second, it slows down the net clock cycle of the surface code operation by a factor . Here, we note that it is not clear what the optimal effective clock cycle is. Too slow is not good since it slows down the computation. Too fast is not good either, since then the classical processors cannot keep up processing the massive data streams produced by the surface code syndrome measurements, and this will pose a hard boundary. This flexibility in choosing the clock cycle of the classical computer may turn out to be an important advantage of electron spin qubits over, e.g., superconducting qubits.
As a more sophisticated and efficient read-out variant, it may be possible to combine the cross-bar approach with frequency multiplexing80 when using RF techniques for read-out.57, 58 In this case, each horizontal line can carry multiple read-out signals simultaneously. The demonstrated on-chip resonators80 will be challenging to fit locally into a dense array. However, frequency multiplexing could also be achieved by clever crossbar operation. For example, if the gates that control the interdot tunnel coupling are connected to vertical lines, these can be frequency-modulated so that each vertical line has a different modulation frequency. The resonance frequency of the readout circuits, measured along the horizontal lines, will then shift corresponding to the respective modulation frequency. This frequency multiplexing enables simultaneous read-out along horizontal lines. Global simultaneous read-out is then obtained by connecting each horizontal line to a separate circuit or by frequency multiplexing each horizontal line. If k frequencies can be simultaneously read out, k qubits can be read out in parallel. This gives further design flexibility and room for optimization.
An important consideration for any of the above uses of cross-bar addressing is whether power dissipation in the switching circuits is compatible with dilution refrigerator temperatures. The desired functionality of the control circuits will determine the number of required active components, the total power dissipation, and the minimum operation temperature. Dynamic power dissipation is a major source of power dissipation in classical electronics, here a single switch contributes P = CV 2 αf, with C is the circuit capacitance, V the applied voltage, and α the activity factor relative to clock cycle with frequency f. For example, if refreshing the voltage on the floating gate would involve compensating a 10 μV drift at 1 V gate voltage and at a conservative refresh rate of 1 MHz per qubit, dissipation would amount to 8 pW for a capacitance of 800 fF, the lowest capacitance that can give 1 μV noise and resolution, as discussed above. The additional power needed to drive the switching of the transistors could be dissipated at higher temperature stages. Large dilution refrigerators are now capable of providing cooling power beyond 1 mW at 100 mK. Therefore, many millions of transistors could potentially operate in combination with floating gates at the lowest temperature stage, provided they can be interconnected to higher temperature stages with dissipationless (superconducting) lines. Simple functionalities such as multiplexing strategies could become compatible with the discussion here and research to find the optimal hybrid, with essential electronics operating at the lowest temperature and all other electronics at higher temperature stages is, therefore, key to scaling spin qubits.
Sparse qubit arrays and local electronics
Several alternative spin qubit coupling mechanisms exist besides direct exchange coupling, that allow the building of two-dimensional spin qubit arrays without the need for direct tunnel coupling between neighboring qubits in four directions (north, south, east, west). Many of these mechanisms have in common that they allow the separation of the qubits by larger distances, varying from roughly 1 μm to roughly 1 mm. Proposals for coupling spin qubits at a distance rely on the use of superconducting resonators,15, 18, 26, 29 capacitive coupling,23, 24, 36 ferromagnets,28 superconductors,27, 31 intermediate dots or dot arrays,19, 20, 33, 34, 39 or surface acoustic wave cavities.30 An alternative approach consists of shuttling electrons across the chip between distant quantum dots, where the electrons are propelled by surface acoustic waves21, 22, 81 or time-varying gate voltages.16, 35, 82, 83 Whereas with enough motivation, any of these platforms could be realized in industry cleanrooms, those that only require additional gate metal are most easily integrated with CMOS technology.
When combining coupling mechanisms at a distance with local registers of tunnel coupled qubits, a modular structure arises as illustrated in Fig. 4. Modular architectures are currently considered across a wide variety of platforms, from trapped ions to superconducting qubits to impurity spins of NV centers in diamond.84 Quantum error correction schemes such as the surface code can be naturally implemented on modular or distributed quantum computers. For instance by moving two logical qubits onto the same local register, two-qubit logical gates can be performed with known methods.85
Widely spaced qubit arrays can alleviate fan-out and wiring problems, simply by allowing more space for routing as also seen in Fig. 4. Yet, even if this allows space to connect each qubit to one or more control lines running off the chip, we mentioned before that connecting individual qubits to sources and generators a large distance away is not viable. Therefore, the more important advantage of space between the qubits may be that it allows a first layer of control electronics that is commensurate with the inter-qubit spacing to be placed directly above or in the qubit layer. If placed above the qubit layer, this classical layer can be interfaced with the qubit layer via an interposer, flip-chip (C4) technology or similar methods. Thermal isolation between the quantum and classical chips could be provided by using superconducting vias for connection. In this way, heating of the qubits by thermal dissipation in the classical circuitry is minimized. When transistors are realized in the same plane as the qubit layer, they could be integrated directly with traditional CMOS fabrication.
Depending on the actual spacing between qubit arrays and on the power budget, the functionality of the classical layer can be more or less advanced.86 At the lowest level, simple multiplexing strategies based on switches can be implemented. What would have more impact is if analog to digital converters (ADC), digital to analog converters (DAC), and vector modulation could be implemented locally in the first classical layer. In this case, only digital signals must flow between the first classical layer and a second layer higher up in the control structure, potentially even at room temperature, where the digital data is processed. The required bandwidth of the communication channel between the classical layers is then much smaller, as per qubit one or a few bits of information must be transmitted per clock cycle, instead of time traces containing a large number of analog data points. Even then, data rates to room temperature are substantial. For example, if 108 qubits are repeatedly read out at 1 μs intervals and each qubit measurement provides one bit of information, the data flow amounts to 100 Tb/s. Control will require a few bits and several operations per surface code cycle. Therefore, local error decoding would be highly attractive but also most demanding in terms of circuit complexity.
The feasibility of this approach hinges on a number of questions that each constitute a full research question, for which only an initial analysis has been performed to date. First estimates indicate that footprints on the order of (100 μm)2 and a power budget in the microwatt range per qubit could be sufficient to implement DC bias sources, AC control DAC’s (operating at 300 MS/s), pulse memory and control logic with currently available 65 nm technology.87 These would implement the complete set of low level control circuits for baseband controlled qubits. If appropriate low-power microwave modulators can be designed, EDSR control would also be possible. Further optimization, the use of a more advanced technology node, and a reduced functionality could lead to a substantial reduction in the required footprint. The dissipation could potentially be reduced by several orders of magnitude if the transistors are fully optimized for low temperature operation by reducing the supply voltage.88 Cooling power itself would not be a severe limitation if electronics can be operated at 1.8 K or higher (for comparison, the Large Hadron Collider magnet system has eight cryocoolers that together provide a cooling power of 144 kW at 4.5 K and 20 kW at 1.9 K (ref. 89)), but a key question is whether the resulting temperature gradient between qubits and electronics can be maintained in conjunction with a sufficient interconnect density. Regarding error decoding, it has been shown that the best-performing surface code algorithm lends itself to parallelization,90 and that it requires about 2 μs per round and qubit on a current high performance CPU.91 Substantial improvement can be hoped for with an application-specific integrated circuit, but it remains to be seen if the resulting circuit complexity and power consumption will be acceptable. Alternatively, other decoders that are less computation-intensive may become an option,92, 93 including decoders based on neural networks.94, 95 To put the electronics footprint in perspective, convenient qubit spacings to allow reliable gate operations from the physics perspective range from 1–10 μm for capacitive couplers,23, 24, 36 from 1–100 μm for spin shuttles16, 35, 81,82,83 and from 100–1000 μm for superconducting resonators15, 18, 26, 29. A final consideration is that the constraints on power dissipation as well as the interconnects between electronics and qubits would be greatly reduced if spin qubits could be operated at higher temperature, without excessive compromises in the fidelity of initialization, coherent operations, memory time, and read-out. We explore this attractive possibility in more detail in the next section.
Much would be gained by qubits that can operate at 1 to 4 K. At 4 K, the cooling power of a single commercial pulse tube cooler as used in qubit experiments today is 1–2 W. By comparison, powerful dilution refrigerators offer a cooling power of 1 mW at 100 mK. At T < 100 mK, we, therefore, expect that only very simple functionality can be realized without excessive heat dissipation. Superconducting classical circuits96 dissipate very little power, but are complex in design, lack the memory function, and have a large footprint. Operating spin qubits at 4 K, with a thousand-fold increase in available cooling power, makes the prospect of electronics commensurate with and right next to the qubit plane more realistic. An integrated quantum-classical structure would have multiple advantages in solving the fan-out problem, would simplify the RF wiring and reduce signal losses.
A major attraction of Si-MOS-based quantum dots and donor-based qubits is that they can have energy scales that are compatible with 1 to 4 K operation. Proper operation requires that the relevant energy scales are about five times larger than the thermal energy, which is 340 μeV at 4 K. Charging energies of donors and small quantum dots are easily in excess of 10 meV and orbital energies can be of order 10 meV as well,97 satisfying this requirement. However, in silicon there is also a valley degree of freedom. Silicon has a sixfold degeneracy due to crystal symmetry, which is broken at the interface leaving two relevant valley states. These lowest-energy valley states can be split via a sharp confinement potential, e.g., the silicon-SiO2 or Si/SiGe interface, and a vertical electric field. In Si/SiGe devices, valley splittings are typically no more than 100 μeV in current devices.51 Possibly this energy scale can be significantly increased by reducing dot size or adopting novel growth approaches. Alternatively, the valley could be initialized using advanced methods such as a measurement-based active reset for high-temperature operation. By comparison, in Si-MOS dots, the valley splitting has reached almost 1 meV,49, 98 and could also be pushed up further by reducing the device dimensions and increasing the electric field by confinement gates. This would allow initialization in the lowest-energy orbital and valley state.
Spin splittings in all spin qubit measurements to date are far below the thermal energy at 1–4 K. This would pose problems for conventional single-spin initialization and read-out schemes.54 Simply increasing the magnetic field and hence the spin splitting would imply impracticable qubit operation frequencies of (sub) THz and potentially too short relaxation times. Instead, high-fidelity initialization and read-out of spin states can make use of the single-dot singlet-triplet splitting, which is typically somewhat below the orbital or valley splitting (whichever is lower) due to the exchange interaction.9 For initialization, two electrons are loaded on the same dot, occupying the ground state valley and orbital state with the spins in a spin singlet configuration. One electron is then moved to the neighboring dot by adjusting the gate voltages, creating a state with one electron on each dot. If the movement is diabatic with respect to the difference in Zeeman energy between the dots, the spins will remain in their spin state and thus be initialized in the singlet state, which is a natural initial state for a S − T 0 qubit.65, 99 When using qubits, the spin singlet can be rotated to via single- and two-qubit gates if desired. If the difference in Zeeman energy is large compared to the exchange energy, diabatic pulsing might not be an option. Instead, adiabatic transfer of one electron to the neighboring dot will directly result in the state65 (Fig. 2). Spin read-out at temperatures exceeding the spin splitting can be realized based on Pauli spin blockade,70 whereby two electrons can or cannot come together on the same dot depending on their relative spin states. The (relative) spin state can then be inferred from charge-sensing,9 as was shown also in recent experiments using Si-MOS quantum dots.41, 75
With one well-initialized electron on each dot, qubit splittings can be chosen in a comfortable range, say 5–200 μeV, which corresponds to accessible microwave frequencies of 1–50 GHz. Hence by combining a large energy splitting for initialization and read-out with a lower level splitting during qubit manipulation, the frequencies for driving qubits do not have to be scaled up with the operating temperature.
The spin relaxation time T 1 will be reduced with higher temperature. Below 100 mK, T 1 is typically very long, especially in silicon, with measured T 1 times of over one second62, 98; see ref. 100 for a theoretical analysis on the limiting relaxation mechanisms. At low temperature, the temperature dependence of T 1 is dictated by one-phonon (direct) processes, and the relaxation rate will increase roughly linearly with temperature.9 However, the relaxation rate can have a much stronger temperature dependence at higher temperatures due to two-phonon transitions, such as 1/T 1 ∝ T 7–9 (Raman) and/or (Orbach), where ΔE is the energy to the first orbital state. For donors, the transition to the exponential temperature dependence due to Orbach transitions occurs at 6 K for phosphorus, 11 K for arsenic, 4 K for antimony, and 26 K for bismuth, all at a magnetic field of 0.3 T. The measured T 1 is above one second at 4 K in all cases.101 For silicon quantum dots, there are few experimental reports on the temperature dependence of T 1.102 Based on the large orbital splitting of order 10 meV that can be realized in silicon quantum dots,97 one would expect the transitions to two-phonon processes to occur at relatively high temperatures as well. However, imperfect interfaces give rise to spin-orbit coupling between the valley states, and this opens a new channel for relaxation as observed in experiment,98 which will have a strong sample-to-sample dependence. Nevertheless, long T 1 times have been achieved even in systems with very small valley splitting.51 This suggests that at least in this temperature range, multi-phonon processes do not dominate and more research on the temperature dependence is needed. Nonetheless, the long relaxation times leave a lot of margin, and we anticipate that it is possible to substantially increase the operating temperature of silicon spin qubits.
Decoherence from hyperfine interaction with nuclear spins in the substrate will be approximately temperature independent. An important question is to what extent both low-frequency and high-frequency charge noise will be enhanced by thermal excitations. Charge noise affects spin states most strongly during gates based on exchange or capacitive coupling (Fig. 2), but also a single spin is sensitive to electric fields through the Stark effect, and this sensitivity is higher if local magnetic field gradients are present. Established models indicate that low-frequency charge noise increases linearly with T, and such signatures are seen in recent experiments on SiGe and SiMOS dots.103 In GaAs, a quadratic dependence of high-frequency charge noise was observed between 50 and 250 mK. If silicon devices exhibit similar behavior, this would strongly impact two-qubit gate fidelities. Significant improvements in the quality of exchange oscillations (the basis for most two-qubit gates, and for single-qubit gates in some qubit representations) were recently obtained by keeping the qubits at all times at the so-called symmetry point (Fig. 2a).104, 105 At this operating point, the spin states are to first order insensitive to the energy detuning between neighboring dots. This detuning is typically the main channel through, which charge noise affects the qubit splitting. Even coupling spin qubits via resonators may be possible at 4 K, despite the fact that the resonator will be thermally populated.106 Altogether, we believe that potential 4 K operation of spin qubits is an attractive possibility.
Wiring up large qubit arrays is a common, central challenge across all qubit platforms. From the above discussion, we see that electron spin qubits in quantum dots or donors offer several particularly attractive features for overcoming this challenge. First, the sub-100 nm lateral dimensions of quantum dots or donors allow for highly dense qubit registers that nevertheless can be wired up with multiplexing and cross-bar approaches with charge-storage electrodes. The feasibility of such approaches strongly benefits from the extremely long coherence times of electron spins in nuclear-spin-free host materials such as isotopically purified 28Si,49, 69, 107 which relax the requirements of parallel read-out and control that short-lived qubits must meet. Second, multiple ideas have been proposed for interconnecting qubit arrays over micron to mm distances. This leaves flexible space for interconnects and integrated electronics. Third, spin qubits on dots or donors may be operated at temperatures of 1–4 K, where the available cooling power is about 1000 times larger than below 100 mK, the typical operating temperature today. This would greatly simplify the integration of a first layer of classical control electronics right next to the qubits, again strongly relaxing the interfacing challenges.
These proposed solutions and approaches are not mutually exclusive. For instance, charge-storage electrodes can be beneficial also in sparse arrays, and a classical layer with (very) limited functionality could be incorporated with dense arrays. Furthermore, it is clear that there is still a big step to take from formulating general ideas as done here, to a complete proposal for an actual device, including device lay-outs, dimensions, power budgets, and so forth. Nevertheless, it is clear that spin qubits offer several particularly attractive possibilities in this direction. Finally, the continuous development of semiconductor technology provides further perspective that the wiring challenges can in fact be overcome, paving the way for the construction of a large-scale universal quantum computer.
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We thank D.P. DiVincenzo and our respective group members for valuable discussions.
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