Fig. 2 | npj Flexible Electronics

Fig. 2

From: High-performance flexible BiCMOS electronics based on single-crystal Si nanomembrane

Fig. 2

Illustration of ion implantation processes and their simulations a Process flow for ion implantations. i, Preparation of SOI wafer. ii, Formation of a lightly doped p-well for NMOS. iii, Formation of a heavily doped p + regions for the source/drain contacts in PMOS and for the base region in BJT. iv, Formation of a heavily doped n + regions for source/drain contacts in NMOS and emitter/collector regions in BJT. Note that a patterned screen oxide was covering “the emitter region” (step iii) or “the emitter and the collector regions” (step iv) of BJT in order to reduce the implantation depth. b Simulated doping profiles for each type of device formed on the same layer. The simulated ion implantation values (dose and energy) were used to fabricate the actual doped Si NM. c Plots of doping profiles in each of the corresponding regions. (i) NMOS (n+ source/drain regions, p-well and the net doping), (ii) PMOS (p+ source/drain regions and substrate), (iii) NPN BJT (n+ emitter, p+ base, n-collector and the net doping)

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