Abstract
Integrating ferroelectric negative capacitance (NC) into the fieldeffect transistor (FET) promises to break fundamental limits of power dissipation known as Boltzmann tyranny. However, realizing the stable static negative capacitance in the nontransient nonhysteretic regime remains a daunting task. The problem stems from the lack of understanding of how the fundamental origin of the NC due to the emergence of the domain state can be put in use for implementing the NC FET. Here we put forth an ingenious design for the ferroelectric domainbased fieldeffect transistor with the stable reversible static negative capacitance. Using dielectric coating of the ferroelectric capacitor enables the tunability of the negative capacitance improving tremendously the performance of the fieldeffect transistors.
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Introduction
Dimensional scalability of field effect transistors (FETs) has reached the Boltzmann tyranny limit because of transistors’ inability to handle the generated heat^{1}. To reduce the power dissipation of electronics beyond this fundamental limits, negative capacitance (NC) of capacitors comprising ferroelectric materials has been proposed as a solution^{2}. The FET with a negativecapacitance ferroelectric layer has gained an enormous attention of researchers^{3,4,5,6,7,8,9,10,11,12}. However, after impressive initial progress that has resulted in a rich lore massaging the aspects of technological benefits of the prospective stable static negative capacitance, the advancement in the field decelerated considerably. The lack of a clear selfconsistent physical picture of the origin and mechanism of the stable static negative capacitance^{7,11,12,13,14} not only retarded the craved technological progress, but has led to numerous invalid fabrications and misleading claims^{9}.
In this work, we put forth a foundational mechanism of the NC in ferroelectrics demonstrating inevitable emergence of the NC due to formation of polarization domains. We establish a practical design of the stable and reversible NC FET based on the domain layout. The proposed device is tunable and downscales to the 2.5–5 nm technology node.
In what follows we review the stateoftheart and basic concepts behind exploring ferroelectrics as the NC elements which constitute the base for our new results. We also mark the potential pitfalls in the NC implementing in the so far suggested NC FETs caused by depreciating the immanent role of domains. Figure 1 demonstrates the principles of integrating the ferroelectric layer with the NC into the FET and the crucial role of domain states. The performance of the FET is quantified by the socalled subthreshold swing \(S\,S={(\partial \left({\log }_{10}{I}_{d}\right)/\partial {V}_{g})}^{1}\) that describes the response of the drain current I_{d} to the gate voltage V_{g}. The lower the value of the SS, the lower power the circuit consumes. In a basic bulk metalinsulatorsemiconductor fieldeffect transistor (MIS FET), shown in Fig. 1a, which generalizes the MOSFET structure, the subthreshold swing is
Here the first factor, SS_{b}, presents the response of I_{d} to the voltage V_{s} at the conducting channel region, and the second factor, the socalled body factor, m, characterizes the response of the voltage V_{s} to the applied voltage V_{g}. Figure 1a shows the equivalent electronic circuit, with C_{g} and C_{s} standing for the gate dielectric and semiconducting substrate capacitancies, respectively.
The fundamental constraint of the energy/power efficiency of the MIS FETs arises from the thermal injection of electrons over an energy barrier enabling drain current flow and thus preventing the reduction of factor SS_{b} below the 60 mV dec^{−1}, because the body factor m > 1 at C_{g}, C_{s} > 0. To overcome this limitation, the FETs incorporating the NC into its design has been proposed^{2}. Indeed, replacing the gate dielectric with material with negative capacitance C_{NC} would make the body factor m < 1, thus, pushing the SS below the Boltzmann limit.
Ferroelectric materials appear as best candidates for realizing negative capacitance in FETs^{2}. The emergence of the NC in a ferroelectric capacitor follows from the Landau doublewell landscape of the capacitor energy W as a function of the applied charge Q^{15} (blue line in Fig. 1b). The downward curvature of W(Q) at small Q implies that the addition of a small charge to the ferroelectric capacitor plate, induces nonzero polarization and reduces its energy. Hence the negative value of the capacitance \({C}_{NC}^{1}={d}^{2}W/d{Q}^{2}\). Remarkably, even the domain formation due to fundamental instability of a monodomain state^{16,17,18,19,20,21}, maintains the negative capacitance^{16,22,23,24,25,26}. The energy W(Q) of the multidomain state is lower then that of the monodomain state while the downward curvature at Q = 0 is conserved, see the red line in Fig. 1b illustrating an exemplary W(Q) for the capacitor hosting two domains. A detailed parsing of particularities related to the monodomain state instability and specific manifestations of the multidomain state is presented in Supplementary Note 1.
An inevitable multidomain formation posits the need for a detailed exploring possible ways of realization design of the NC FETs. While the multidomain configuration preserves the NC, the domain formation may trigger some undesired effects detrimental to realizing the NC FET. In particular, domains cause inhomogeneous charge^{21} and electric field^{27} distribution, endangering the conducting channel in the most commonly discussed metalferroelectricsemiconducting MFS FETs (Fig. 1c), as the voltage dispersion they cause becomes comparable with the transistor operation voltage. This problem can be mended by putting the ferroelectric layer into the pretransitional (incipient) regime just above the transition temperature, where the NC effect still persists, but the fieldinduced polarization distribution is uniform^{5,28,29}. However, this would limit the desirable decreasing of the body factor keeping it above 0.99^{29}. Another way out is introducing an intermediate dielectric (insulating) buffer layer between the ferroelectric and semiconductor^{10}, which corresponds to MFIS FET architecture shown in Fig. 1d. This, in its turn, would not help much because smoothing the field nonuniformity would occur only at distances well exceeding the spatial scale on which the NC potential amplification effect is still actual. A detailed analysis of particularities related to pitfalls of the discussed above architectures of the specific multidomain state is presented in Supplementary Note 2.
The design with the floating gate electrode placed between ferroelectric and dielectric layers^{30,31} appeared to resolve this problem and to level the field inhomogeneities right below the electrode. The resulting MFMIS structure is the conventional FET with the overimposed MFM capacitor, see Fig. 1e. This architecture has attracted some critique^{32}, since it was believed that the antiparallel domains formation inside the MFM capacitor would destabilize the NC. However, as we established in Luk’yanchuk et al.^{24}, it is precisely the twodomain configuration that provides the stable and operable NC because of the possibility of manipulating the domain wall by the applied charges, not accounted for in Hoffmann et al.^{32}.
Here we introduce and devise the working regime of the MFMIS FET in which the NC effect emerges from the integrated MFM capacitor hosting two domains. We show that the MFMIS architecture not only free from the perils mentioned above but allows for an enormous improving MFMIS FET characteristics by coating the MFM capacitor with the dielectric capacitor in parallel connection. The proposed coating design that we call cMFMIS FET, shown in Fig. 1f, provides degrees of freedom enabling a complete tunability of the dielectric parameters of the NC FET.
Results and discussion
Twodomain negative capacitance of the MFM capacitor
The nanodotscale twodomain MFM is a major element of the MFMIS FET enabling the NC response via the chargecontrolled motion of the DW. Following^{24}, we discuss in detail the negative capacitance of the MFM capacitor, which is the base of our proposed device. Shown in Fig. 2a is the general view of MFMIS FET. Figure 2b presents the vertical and horizontal crosssections of a nanoscale ferroelectric discshape MFM capacitor integrated in the MFMIS FET. At the zero charge Q_{f} at the electrodes of the MFM capacitor, corresponding to the zero voltage at the transistor, the DW sits in the middle of the capacitor, see left hand side of Fig. 2b. The intrinsic charges at the respective electrodes redistribute in order to compensate the depolarization charges of each domain (keeping the total charge Q_{f} = 0) and to banish the electric field inside the ferroelectric disc, reducing thus the electrostatic energy. The finite charge Q_{f}, induced by the voltage V = V_{g} applied to the transistor gate, displaces the DW from its middle zerovoltage position, see right hand side of panels b. Accordingly, the intrinsic charges rearrange (maintaining the total charge Q_{f}) to compensate the depolarization fields of now unequal domains.
The NC response arises since the length, hence the energy of the displacing DW, is sensitive to the shape of a ferroelectric capacitor. To ensure the best controlled performance of the NC, we choose a disclike form of a capacitor. When moving apart from the middle, the DW not only compensates the electric field arising due to the charge transferred to the electrodes but, minimizing its surface selfenergy, shrinks in the width w and bends because of the cylindrical shape of a ferroelectric. As a result, the DW overshoots towards the edge beyond the electrostaticsdemanded equilibrium position at which the internal electric field would have disappeared. Hence the net electric field does not vanish but flips over and goes from the negatively charged electrode to the positively charged one. This counterintuitive outcome precisely expresses the phenomenon of the negative capacitance. Note, however, that at some threshold value of the applied charge, \({Q}_{f}^{* }\), when it becomes approximately equal to the depolarization charge of the uniformly oriented polarization, Q_{0}, the DW reaches the edge of the ferroelectric layer and leaves the sample. The monodomain state with positive capacitance restores; this corresponds to the termination of the red branch in Fig. 1b.
The quantitative description of the NC of the diskshape twodomain ferroelectric capacitor is given by Luk’yanchuk et al.^{24}
where we explicitly spotlighted the capacitance C_{f} = ε_{0}ε_{f}S_{f}/d_{f} > 0, which is the capacitance of the monodomain MFM capacitor in the stable state at Q = ±Q_{0} = ±S_{f}P_{0} (minima of the W(Q) dependence in Fig. 1b). The negative factor, − γ_{2}D_{f}/ξ_{0}, reflects the features brought in by the DW displacement in the twodomain configuration. Here D_{f} and d_{f} are the diameter and height of the capacitor, respectively, \({S}_{f}=\pi {D}_{f}^{2}/4\) is the area of the ferroelectric plate surfaces, and P_{0} is the polarization of the ferroelectric in the equilibrium state. The coherence length ξ_{0} ≃ 1nm describes the DW thickness, the dimensionless geometric factor γ_{2} ≈ 4.24 reflects the internal profile of polarization inside the DW and the DW bending in the cylindrical gate, and ε_{f} and ε_{0} are the dielectric constant of the ferroelectric material and the vacuum permittivity, respectively.
Figure 1b displays the energy advantage of the twodomain state (whose energy is shown by the red curve), with respect to the usually considered uniform NC state (the blue dashed curve), both states preserving the same charge Q at the electrodes. To create the twodomain state from the uniformlypolarized state one has to suppress polarization in a fraction of the ferroelectric occupied by the DW, while to depolarize the monodomain state by the electric field due to the uniformly distributed charge Q, one would have had to suppress the ferroelectricity within the whole volume which is much more energetically costly.
As a next step, we integrate the MFM twodomain NCcapacitor into the MFMIS FET architecture.
The MFMIS FET
This device comprises the gate stack overimposed on a semiconducting substrate in which the source and drain parts are connected by the gateoperated conducting channel, see Fig. 2a. The gate stack includes the MFM capacitor and the gate insulating layer separating it from the substrate. This is the highκ dielectric layer, preventing a charge leakage between the lower capacitor’s plate and the semiconducting channel.
The top MFM capacitor plate is the gate electrode connecting the transistor to the external voltage source. The bottom capacitor electrode is an intermediate electrically isolated floating gate electrode of the transistor that preserves the entire charge, most commonly the zero total charge, constant, stabilizing the ferroelectric twodomain state. Furthermore, the floating gate makes the potential along the ferroelectric interface even, maintaining, therefore, a uniform electric field across the gate stack and substrate. Along the way, the floating gate resolves a frequent issue of neutralizing the parasitic charges that may be trapped by interfaces during the fabrication and functioning. Maintaining the working charge and providing a regular rubbing out the parasite leaking charges with the removal time faster than the leakage time^{31} is achieved via the standard discharging methods. For instance, it is implemented by either harnessing the FowlerNordheim tunneling and the hot electrons injection^{33}, or by circuiting the gate by the auxiliary chargecarrying current, I_{Q}, contact, see Fig. 1e, to a certain source for a given combination of electric inputs ensuring the proper sequence of discharging and high resistance modes^{34}.
An effective electronic circuit of the MFMIS FET, shown in Fig. 1e, is similar to that of the multidomain MFIS FET (Fig. 1d). The difference is that now the task of leveling the depolarization field inhomogeneities is taken by the floating gate electrode. Therefore, the gate dielectric layer can be safely engineered as an utmostly thin one, down to the technologicallyacceptable limit of a few nanometers. This increases C_{d} with respect to ∣C_{NC}∣, opening doors to making the gate capacitance negative, \({C}_{g}^{1}={C}_{d}^{1} {C}_{NC}^{1} \,<\, 0\). Yet it is hard to achieve a required largeness of C_{d} with respect to ∣C_{NC}∣ due to the restrictions imposed by materials compatible with the silicon CMOS technologies. To meet the challenge, we devise a coated cMFMIS FET that critically changes the situation and breaks ground for the unlimited enhancement of the performance of the NC FET transistor.
The cMFMIS FET
The coating of the ferroelectric layer with the dielectric oxide sheath confined by the same electrodes, see Fig. 2c, d straightforwardly incorporates an additional capacitor with the capacitance C_{c} > 0 in parallel to C_{NC}. This results in a radical improvement of the controlled tuning of the gate capacitance. In particular, manipulating with the sizes of the coating oxide layer and with the geometrical design of the device as a whole, provides a broad variation in its performance characteristics and functioning regimes. The panels (c) and (d) exemplify possible designs. The panel (c) shows an annuluslike coating capacitor, while panel (d) displays a rectangular design of the coating layer and, in addition, the possibility of increasing the area of the floating gate electrode with respect to the top gate electrode. The latter design allows for controllable increasing capacitances of the coating and gatedielectric layers most efficiently, maintaining the miniaturization of the device. Note, that in all the geometries, the core ferroelectric should maintain its disclike shape ensuring the optimal manipulation with the DW.
Shown in Fig. 1f is the equivalent circuit of cMFIS FET. The important advance is that the gate capacitance becomes
which permits tuning C_{g} over the widest range of values by the appropriate modifying the parameters of the coating capacitor. We reveal the rich dependence of C_{g} on the coating layer size, L_{c} choosing the rectangular geometry of the coating layer (Fig. 2c). The capacitance of the diskshape twodomain ferroelectric capacitor, C_{NC}, is given by Eq. (2). The capacitances of the coating and gate dielectric layers are taken in a standard form as C_{c} = ε_{0}ε_{c}S_{c}/d_{c} and C_{d} = ε_{0}ε_{d}S_{d}/d_{d}, respectively. Here \({S}_{f}=\pi {D}_{f}^{2}/4\), \({S}_{c}={L}_{c}^{2}{S}_{f}\) and \({S}_{d}={L}_{d}^{2}\) are areas of the ferroelectric, coating dielectric and gate dielectric plate surfaces, respectively.
The behavior of C_{g} defined by Eq. (3) is most generic and does not depend critically on the specific choice of materials. For practical applications, we choose both, the coating layer and the gatedielectric layer, be composed of the Sicompatible dielectric HfO_{2} with the respective dielectric constants ε_{c}, ε_{d} being approximately equal to 25. The ferroelectric disc of the diameter D_{f} ≃ 6 nm and thickness d_{f} ≃ 3 nm, can be fabricated out of the ferroelectric phase of HfO_{2} or its Zrbased modification, Hf_{0.5}Zr_{0.5}O_{2} with ε_{f} ≃ 50^{13}. In fact, ε_{f} is the only relevant material parameter that defines the NC properties of the twodomain ferrolectric layer; therefore, the consideration applies equally well to other similar ferroelectrics, for instance, to perovskite oxides, like strained PbTiO_{3} with about the same ε_{f}. The height of the gate dielectric layer is taken as d_{d} ≃ 3 nm, whereas the thickness of the coating layer, d_{c}, is equal to d_{f}. The size of the rectangular floatinggate electrode, L_{d}, defining the size of the gate dielectric capacitor, is taken as 1.2L_{c}.
Figure 2e displays the derived normalized gate capacitance, c_{g} = C_{g}/S_{d} as function of L_{c}. The presented c_{g}(L_{c}) dependencies are the Eq. (3) plots, into which the given above capacitancies, C_{NC}, C_{c}(L_{c}) and C_{d}(L_{c}) are substituted. Looking at the plots, one discriminates the three distinct regimes of the gate functioning set by two critical sizes, L_{c1} < L_{c2}, of the coating layer: (i) the supercapacitance, L_{c} < L_{c1}, (ii) the negativecapacitance, L_{c1} < L_{c} < L_{c2}, and (iii) the nearzero capacitance, L_{c2} < L_{c}. All these three distinct regimes are of tremendous relevance for applications. Below, we restrict ourselves to the detailed analysis of the NC regime, i.e., the regime where c_{g} < 0, leaving the detailed discussion of regimes (i) and (iii) to forthcoming publication. Note that although in the NC regime the average polarization of the ferroelectric nanodot is aligned with the voltage drop across the capacitor, the electric field inside the coated layer is directed oppositely to it. Accordingly, the polarization induced inside the dielectric oxide sheath is opposite to the polarization of the ferroelectric nanodot, see Fig. 2f. It is important that the absolute value of the NC capacitance can be done arbitrary small on approach to the resonance regime ∣C_{NC}∣ = C_{c} of Equation (3), i.e., upon L − L_{c2} → 0^{−}. In this regime the nonlinear effects in the Q − V characteristics of the MFM capacitor become of prime relevance.
An unrestricted range of variation of c_{g}, from minus infinity to zero, as seen from Fig. 2e, allows for the unlimited tuning of the magnitude of the gate NC. In particular, the possibility of making it arbitrary small, enables us to overcome a previously insurmountable obstacle of the proper matching between the gate, C_{g}, and substrate, C_{s}, capacitancies and obtain the desirable value of the body factor
within the NC FET operational interval 0 < m < 1, getting thus the remarkably low values of SS(1), the task not achievable by previously suggested architectures.
Now the task is to find the optimal coating size L_{c}, given the normalized substrate capacitance c_{s} = C_{s}/S_{d}, that ensures matching to targeted value of m. To that end, we employ Eq. (4) which defines the implicit L_{c} dependence of c_{s} at given m. The shown in Fig. 3a family of L_{c}(c_{s}) curves for different m, confined between m = 0 (red) and m = 1 (brown) characteristics, represents the stable working interval for our exemplary cMFMIS FET.
The region below the brown line where m > 1, i.e., SS > 60 mV dec^{−1}, corresponds to small sizes of the coating layer, L_{c} < L_{c1}. The region above the m = 0 curve but below the L_{c} = L_{c2} line is the hysteretic loss of the reversibility region. Therefore, the proper choice of L_{c}, in the interval L_{c1} < L_{c} < L_{c2}, enables the desired magnitude of m for a given value of the substrate capacitance c_{s}. Although in our model example, the lateral size of the coating layer varies between L_{c1} ≈ 24 nm and L_{c2} ≈ 38 nm, it can be significantly reduced down to practically the diameter of the ferroelectric disc, by increasing the dielectric constant of the coating material by factor of four.
Practical design. Optimal match between gate and substrate
The established characteristics of the cMFMIS FET enable us to go beyond the past prima facie technological concepts and turn to the practical design in relevant industrial environment. The critical challenge^{9} emerging when engineering the NC FET, is the complex and highly nonlinear nature of C_{s} since the latter comprises contributions from the capacitance of the depleted layer, from the quantum capacitance due to charge carriers injected into the conducting channel, from the interface charges, and, finally, from the source/drain geometrical capacitancies. While being of a relatively low value when coming mainly from the capacitance of the depletion layer in the lowconducting regime at small voltages, C_{s} increases dramatically, typically by order of magnitude, due to the injection of conducting electrons into the channel caused by the gate bias near and above the threshold value.
Using our established concept of L_{c}(c_{s}, m) characteristics, Fig. 3a, enables the determining an optimal match between the NC gate capacitance and the semiconducting substrate capacitance ensuring the bestperformance SS and stability of the transistor. To exemplify the nonlinear behavior of the substrate, we take the normalized capacitance \({c}_{s}^{{{{\rm{sth}}}}}\simeq 1{0}^{2}\) Fm^{−2} in the lowvoltage subthreshold regime and \({c}_{s}^{{{{\rm{th}}}}}\simeq 1{0}^{1}\) Fm^{−2} in the highvoltage nearthreshold regime. Next, we set the condition m = 0 at the steepest point of the I_{d}(V_{g}) curve, i.e., in the nearthreshold gate voltage where \({c}_{s}={c}_{s}^{{{{\rm{th}}}}}\). This condition visualized by the point A in Fig. 3a, provides us with the optimal value of the size of the coating layer, \({L}_{c}^{{{{\rm{opt}}}}}\approx 28\) nm. Decreasing the gate voltage V_{g} to subthreshold values, reduces c_{s} and moves it to the left from the point A along the black line until reaching the point B corresponding to \({c}_{s}={c}_{s}^{{{{\rm{sth}}}}}\) at V_{g} ≈ 0. The body factor at the point B is m = 0.9 which gives SS ≈ 54 mV dec^{−1}.
The possible transfer I_{d}(V_{g}) characteristics^{9} are schematically illustrated in Fig. 3b. The optimal characteristic (red line) derived according to the devised above operating procedure starts with the relatively modest SS ≈ 54 mV dec^{−1}, steepens upon the increase in V_{g}, and reaches its steepest value in the nearthreshold region. The location of points A and B corresponds to the capacitancies \({c}_{s}^{{{{\rm{th}}}}}\) and \({c}_{s}^{{{{\rm{sth}}}}}\) of panel a. The optimal regime maintains the steep slope of the I_{d}(V_{g}) dependence over the entire voltage working range and includes not only the subthreshold, but also near and above threshold regimes, preserving the stable and hysteresis free I–V_{g} transfer characteristics at the same time.
Because of the nonlinearity of c_{s}, the transfer characteristics of the designed cMFMIS FET with \({L}_{c}={L}_{c}^{{{{\rm{opt}}}}}\) demonstrates the better performance at the same onoff current switching ratio, I_{on}/I_{off}, than the shown by the green curve commonly assumed NC FET with the voltageindependent substrate capacitance c_{s} (although having the steeper initial SS). At the same time, an attempt to engineer the NC FET having the nonlinear c_{s} with an initially steeper SS (exemplified by the blue curve), results in the hysteretic switching instability.
Practical design. Compact gate model
In order to provide incorporating the twodomain cMFMIS FET architecture into the industriallystandardized circuiting, we design the scalable compact model describing the Q_{g}–V_{g} characteristics of the coated NC gate stack. In the lowvoltage and lowcharge operational mode of the NC FET, this compact model is defined by the linear relation Q_{g} = C_{g}V_{g}, where C_{g} is given by Eqs. (2) and (3). Looking forward to extensive applications of our compact model for the description of the cMFMIS FET, we expand the compact model’s working range over to the nonlinear regime where substantial shifts of the domain wall and even its escape from the sample may occur.
The complete set of the Q_{g}–V_{g} characteristics of the gate is defined by the individual electric properties of its components, including the gate dielectric capacitor, coating capacitor, and the MFM capacitor which form the equivalent circuit shown in Fig. 1f and which are characterized by the linear, \({V}_{d}={C}_{d}^{1}{Q}_{d}\), \({V}_{c}={C}_{c}^{1}{Q}_{c}\), and nonlinear, \({V}_{f}={V}_{f}\left({Q}_{f}\right)\), constitutive relations respectively. In general, the V_{g}–Q_{g} characteristics can be parametrically plotted as functions of the running parameter Q_{f}
based on the relations Q_{g} = Q_{d} = Q_{c} + Q_{f}, V_{g} = V_{d} + V_{f}, and V_{f} = V_{d} for the circuit in Fig. 1f.
The nonlinear constitutive relation, \({V}_{f}\left({Q}_{f}\right)\), of the MFM capacitor is the core relation that defines different regimes of the gate functioning. Shown in the Fig. 3c, are the results of the phasefield simulations (crosses), see Methods, and the analytical outcome of the developed scalable compact model (solid lines). The Q_{f}–V_{f} characteristic reveals two different operational modes of the MFM capacitors. The NC lowcharge branch, \({V}_{2}\left({Q}_{f}\right)\) (red curve), corresponds to the twodomain state where the domain wall motion is responsible for the electric properties of capacitor. The highcharge branch, \({V}_{1}\left({Q}_{f}\right)\) (blue curve), with the positive differential capacitance, C_{f} = dV/dQ > 0, corresponds to the monodomain state where the domain wall is gone. As a result, the Q_{f}V_{f} characteristic of the ferroelectric capacitor is presented by the synthetic dependence
where \({Q}_{f}^{* }\) is the charge at which the branches \({V}_{2}\left({Q}_{f}\right)\) and \({V}_{1}\left({Q}_{f}\right)\) meet.
The corresponding to the monodomain state branch of the V_{f}Q_{f} characteristic, is given by the parametric dependence of V_{1}(Q_{f}) upon the polarization P,
derived from the uniform GinzburgLandau equation. The coefficients \({a}_{3}^{* }\), \({a}_{33}^{* }\) and a_{333}, and the background dielectric constant ε_{i} are defended in Methods.
For the V_{2}(Q_{f}) function describing the twodomain case we use the analytical approximation^{24}
where ψ(s) (0 < s < 1), introduced in Luk’yanchuk et al.^{24}, is the function accounting for the geometry of the system which we fit by
In the linear in Q_{f} approximation, where s → 0, Eq. (8) gives C_{NC} in Eq. (2).
Combining branches given by Eqs. (7) and (8) provides an excellent approximation for the results of the numerical simulations of the compact model, see Fig. 3c. The slight overshoots at \(\pm {Q}_{f}^{* }\) correspond to numerical singularities appearing at the moments where the DW leaves the MFM capacitor.
To summarize, the achieved understanding that the fundamental mechanisms of the NC is the domain action, bestows closing the gap between the concept of the ferroelectric negative capacitance and its realization in electronic devices. It enables designing a stable NCbased FET, whose coatingshell architecture of the gate promises a notable enhancement of prospective performance and high tunability of characteristics allowing the perfect match with advanced FET architectures. Our findings lay out the way for scaling the NC FET nanoelectronics down to 2.5–5 nm technology nodes via utilizing the CMOScompatible ultrathin and ultrasmall ferroelectric disc as a core of the NC gate.
Methods
Functional
To carry out the numerical modeling of polarization structures in a ferroelectric layer, we use the most thoroughly studied free energy functional for the PbTiO_{3},
where the sum is taken over the cyclically permutated indices {i, j, k, l} = {1, 2, 3} (or {x, y, z}). Functional Eq. (10) includes the GinzburgLandau (GL) energy of the strained ferroelectric layer^{35} written in a form given in^{36} (the squarebracketed term), the polarization gradient energy^{37} (the term with coefficients G_{ijkl}), and the electrostatic energy, including the coupling of polarization with electric field^{19}, E_{i} = − ∂_{i}φ, described through the electrostatic potential φ (the two last terms). The strainrenormalized GL coefficients for the PbTiO_{3} layer (accounting partially for the elastic energy) are taken as^{35}, \({a}_{1}^{* }\),\({a}_{2}^{* }\) = 3.8 × 10^{5}(T − 479^{∘}C) − 11 × 10^{9}u_{m} C^{−2}m^{2}N^{−1}, \({a}_{3}^{* }\) = 3.8 × 10^{5}(T − 479^{∘}C) + 9.5 × 10^{9}u_{m} C^{−2}m^{2}N^{−1}, \({a}_{11}^{* }\), \({a}_{22}^{* }\) = 0.42 × 10^{9} C^{−4}m^{6}N, \({a}_{33}^{* }\) = 0.05 × 10^{9} C^{−4}m^{6}N, \({a}_{13}^{* }\),\({a}_{23}^{* }\) = 0.45 × 10^{9} C^{−4}m^{6}N, \({a}_{12}^{* }\) = 0.73 × 10^{9} C^{−4}m^{6}N, a_{111}, a_{222}, a_{333} = 0.26 × 10^{9} C^{−6}m^{10}N, and a_{123} = −3.7 × 10^{9} C^{−6}m^{10}N. The misfit strain is taken as u_{m} = −0.013. The gradient coefficients are taken as for PbTiO_{3} bulk material^{37} (with all possible cubic index permutations), G_{1111} = 2.77 × 10^{−10} C^{−2}m^{4}N, G_{1122} = 0.0, and G_{1212} = 1.38 × 10^{−10} C^{−2}m^{4}N. The background dielectric constant of the nonpolar ions was taken as ε_{i} ≃ 10^{38} for PbTiO_{3} and ε_{i} ≃ 25 for semiconducting layer. The vacuum permittivity is ε_{0} = 8.85 × 10^{−12} CV^{−1}m^{−1}.
Phasefield simulations
The minimum of the energy functional Eq. (10) is found by solving relaxation equation
where δF/δP is the variational derivative of Eq. (10); the timescale parameter γ, which does not influence the sought energy minimum is taken equal to unity. The electrostatic Poisson equation ε_{0}ε_{i}∇^{2}φ = ∇ ⋅ P, describing the spatial distribution of the polarization, is solved on the each respective relaxation step.
For practical implementation of simulations, we have used the opensource FEniCS computing platform^{39}. To create the tetrahedral finiteelement meshes we used an opensource 3D mesh generator gmsh^{40}. For the case of the MFM capacitor, the computational region is a cylindrical volume Ω, restricted by the side boundary, ∂Ω_{s}, and by the top, ∂Ω_{t}, and bottom, ∂Ω_{b}, boundaries, see Fig. 4a. For the case of the MFSM heterostructure, the computational region is a rectangular box Ω, that includes the ferroelectric layer, Ω_{F}, and the semiconducting layer, Ω_{S}, see Fig. 4b. The computational region, Ω, is restricted by the left, right, front and backside boundaries ∂Ω_{s} and by the top, ∂Ω_{t}, and bottom, ∂Ω_{b}, boundaries.
The solutions for the polarization, P(r), and electrical potential, φ(r), distribution were sought in the functional space of the piecewise linear polynomials. For simulation of the MFMcapacitor, controlled by charge Q, we use free boundary conditions for P(r) on the whole surface of the cylinder. At the same time, it was assumed that the electrodes produce almost uniform zdirected electric field, E_{z} = − ∂_{z}φ, spreading through the capacitor. The boundary constraint \(Q/{S}_{f}={\bar{P}}_{{z}}+{\varepsilon }_{0}{\varepsilon }_{i}{E}_{{z}}\) was used at the electrode interfaces to fix the applied charge Q that tunes the displacement of the DW in the spontaneously emerging twodomain structure. The bar denotes averaging over the interface surface.
For simulation of the MFSM heterostructure, the relaxation Eq. (11) was solved for the ferroelectric part of the sample while the electrostatic Poisson equation was solved for the whole domain. Boundary conditions for all the variables were taken to be periodic in the x direction. The size of the simulation rectangular box in xdirection, corresponding to the period of the spontaneously emerging domain structure was considered as an energyminimizing parameter which was optimized for each series of calculations. Boundary conditions for P on ∂Ω_{t} and ∂Ω_{b} as well as on the front and back surface boundaries of the rectangular box were taken as free boundary conditions. The Dirichlet boundary conditions were imposed on φ at the bottom and top surfaces of the box such that φ(∂Ω_{b}) = −U/2 and φ(∂Ω_{t}) = +U/2, to reproduce the application of the voltage U to the electrodes. The effective charge at the electrode was calculated as \(Q={S}_{f}(\bar{P}+{\varepsilon }_{0}{\varepsilon }_{i}{\bar{E}}_{{z}})\).
To approximate the time derivative in Eq. (11), we used the variabletime BDF2 stepper^{41}. The initial conditions for polarization distribution were taken to be random in the range of −10^{−6}–10^{−6} C m^{−2} for the polarization magnitude at the first timestep of simulation. The system of the nonlinear equations arising from the discretization of Eq. (11) was solved using the Newtonbased nonlinear solver with line search and generalized minimal residual method with the restart^{42,43}. On each time step of the simulation in MFSM heterostructure, the linear system of equations obtained from the discretization of electrostatic Poisson equation was solved separately using a generalized minimal residual method with restart.
Data availability
The data generated and analyzed during this study are available from the corresponding author upon reasonable request.
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Acknowledgements
This work was supported by H2020 RISEMELON action (I.L.), and by Terra Quantum AG (I.L., A.R., and V.M.V.). The work of V.M.V. was supported in part by Fulbright Foundation.
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I.L., Y.T., A.R., A.S. and V.M.V. conceived the work and performed calculations. I.L. and V.M.V. wrote the manuscript.
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Luk’yanchuk, I., Razumnaya, A., Sené, A. et al. The ferroelectric fieldeffect transistor with negative capacitance. npj Comput Mater 8, 52 (2022). https://doi.org/10.1038/s41524022007382
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DOI: https://doi.org/10.1038/s41524022007382
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