The ferroelectric field-effect transistor with negative capacitance

Abstract

Integrating ferroelectric negative capacitance (NC) into the field-effect transistor (FET) promises to break fundamental limits of power dissipation known as Boltzmann tyranny. However, realizing the stable static negative capacitance in the non-transient non-hysteretic regime remains a daunting task. The problem stems from the lack of understanding of how the fundamental origin of the NC due to the emergence of the domain state can be put in use for implementing the NC FET. Here we put forth an ingenious design for the ferroelectric domain-based field-effect transistor with the stable reversible static negative capacitance. Using dielectric coating of the ferroelectric capacitor enables the tunability of the negative capacitance improving tremendously the performance of the field-effect transistors.

Introduction

Dimensional scalability of field effect transistors (FETs) has reached the Boltzmann tyranny limit because of transistors’ inability to handle the generated heat¹. To reduce the power dissipation of electronics beyond this fundamental limits, negative capacitance (NC) of capacitors comprising ferroelectric materials has been proposed as a solution². The FET with a negative-capacitance ferroelectric layer has gained an enormous attention of researchers^{3,4,5,6,7,8,9,10,11,12}. However, after impressive initial progress that has resulted in a rich lore massaging the aspects of technological benefits of the prospective stable static negative capacitance, the advancement in the field decelerated considerably. The lack of a clear self-consistent physical picture of the origin and mechanism of the stable static negative capacitance^{7,11,12,13,14} not only retarded the craved technological progress, but has led to numerous invalid fabrications and misleading claims⁹.

In this work, we put forth a foundational mechanism of the NC in ferroelectrics demonstrating inevitable emergence of the NC due to formation of polarization domains. We establish a practical design of the stable and reversible NC FET based on the domain layout. The proposed device is tunable and downscales to the 2.5–5 nm technology node.

In what follows we review the state-of-the-art and basic concepts behind exploring ferroelectrics as the NC elements which constitute the base for our new results. We also mark the potential pitfalls in the NC implementing in the so far suggested NC FETs caused by depreciating the immanent role of domains. Figure 1 demonstrates the principles of integrating the ferroelectric layer with the NC into the FET and the crucial role of domain states. The performance of the FET is quantified by the so-called subthreshold swing $S\,S={(\partial \left({\log }_{10}{I}_{d}\right)/\partial {V}_{g})}^{-1}$ that describes the response of the drain current I_d to the gate voltage V_g. The lower the value of the SS, the lower power the circuit consumes. In a basic bulk metal-insulator-semiconductor field-effect transistor (MIS FET), shown in Fig. 1a, which generalizes the MOSFET structure, the subthreshold swing is

$$S\,S=\overbrace{\frac{\partial V_{s}}{\partial \left( {\log}_{10}I_d\right) }}^{S\,S_b}\overbrace{\frac{\partial V_{g}}{\partial V_{s}}}^{m},\quad m=1+\frac{C_{s}}{C_{g}}.$$

(1)

Here the first factor, SS_b, presents the response of I_d to the voltage V_s at the conducting channel region, and the second factor, the so-called body factor, m, characterizes the response of the voltage V_s to the applied voltage V_g. Figure 1a shows the equivalent electronic circuit, with C_g and C_s standing for the gate dielectric and semiconducting substrate capacitancies, respectively.

Fig. 1: Stability and feasibility of the ferroelectric-based NC FETs.

a Bulk MIS FET. Pale blue: p-type semiconducting substrate; dusty blue: source (S) and drain (D) of n-doped regions connected by conducting channel; sky blue: bottom ground electrode. The gate stack: gate electrode and oxide gate dielectric layer (yellow green). Right: equivalent circuit comprising gate dielectric capacitance, C_g, and capacitance to the ground, C_s, of the substrate. Solid lines depict electrodes, dashed lines depict interfaces without electrodes; V_g is the applied gate voltage, V_s is the channel potential. b The normalized energy, W/∣W₀∣, and polarization states of the ferroelectric (orange) capacitor as a function of the normalized driving charge Q/Q₀. Here Q₀ and W₀ are the equilibrium charge and energy of the monodomain short-circuited capacitor, respectively. The unstable energy branch (dashed line) depicts the energy of the monodomain state. The energy of a stable two-domain state is shown by the red curve. Pluses and minuses show the distribution of charges at the plates. c Multidomain structure of the MFS FET with redistributed electric charges at the top gate electrode and fringing electric fields (red loops) at the FS interface. Ferroelectric capacitance C_NC < 0 replaces C_g > 0 of the MIS FET. d MFIS FET incorporates the dielectric layer with C_d > 0. e MFMIS FET integrating a floating gate electrode into the MFIS FET between ferroelectric and dielectric layers. f The coated c-MFMIS FET: the dielectric shell (yellow) with C_c > 0 coats the ferroelectric layer.

The fundamental constraint of the energy/power efficiency of the MIS FETs arises from the thermal injection of electrons over an energy barrier enabling drain current flow and thus preventing the reduction of factor SS_b below the 60 mV dec⁻¹, because the body factor m > 1 at C_g, C_s > 0. To overcome this limitation, the FETs incorporating the NC into its design has been proposed². Indeed, replacing the gate dielectric with material with negative capacitance C_NC would make the body factor m < 1, thus, pushing the SS below the Boltzmann limit.

Ferroelectric materials appear as best candidates for realizing negative capacitance in FETs². The emergence of the NC in a ferroelectric capacitor follows from the Landau double-well landscape of the capacitor energy W as a function of the applied charge Q¹⁵ (blue line in Fig. 1b). The downward curvature of W(Q) at small Q implies that the addition of a small charge to the ferroelectric capacitor plate, induces non-zero polarization and reduces its energy. Hence the negative value of the capacitance ${C}_{NC}^{-1}={d}^{2}W/d{Q}^{2}$. Remarkably, even the domain formation due to fundamental instability of a monodomain state^{16,17,18,19,20,21}, maintains the negative capacitance^{16,22,23,24,25,26}. The energy W(Q) of the multidomain state is lower then that of the monodomain state while the downward curvature at Q = 0 is conserved, see the red line in Fig. 1b illustrating an exemplary W(Q) for the capacitor hosting two domains. A detailed parsing of particularities related to the monodomain state instability and specific manifestations of the multidomain state is presented in Supplementary Note 1.

An inevitable multidomain formation posits the need for a detailed exploring possible ways of realization design of the NC FETs. While the multidomain configuration preserves the NC, the domain formation may trigger some undesired effects detrimental to realizing the NC FET. In particular, domains cause inhomogeneous charge²¹ and electric field²⁷ distribution, endangering the conducting channel in the most commonly discussed metal-ferroelectric-semiconducting MFS FETs (Fig. 1c), as the voltage dispersion they cause becomes comparable with the transistor operation voltage. This problem can be mended by putting the ferroelectric layer into the pretransitional (incipient) regime just above the transition temperature, where the NC effect still persists, but the field-induced polarization distribution is uniform^5,28,29. However, this would limit the desirable decreasing of the body factor keeping it above 0.99²⁹. Another way out is introducing an intermediate dielectric (insulating) buffer layer between the ferroelectric and semiconductor¹⁰, which corresponds to MFIS FET architecture shown in Fig. 1d. This, in its turn, would not help much because smoothing the field nonuniformity would occur only at distances well exceeding the spatial scale on which the NC potential amplification effect is still actual. A detailed analysis of particularities related to pitfalls of the discussed above architectures of the specific multidomain state is presented in Supplementary Note 2.

The design with the floating gate electrode placed between ferroelectric and dielectric layers^30,31 appeared to resolve this problem and to level the field inhomogeneities right below the electrode. The resulting MFMIS structure is the conventional FET with the overimposed MFM capacitor, see Fig. 1e. This architecture has attracted some critique³², since it was believed that the anti-parallel domains formation inside the MFM capacitor would destabilize the NC. However, as we established in Luk’yanchuk et al.²⁴, it is precisely the two-domain configuration that provides the stable and operable NC because of the possibility of manipulating the domain wall by the applied charges, not accounted for in Hoffmann et al.³².

Here we introduce and devise the working regime of the MFMIS FET in which the NC effect emerges from the integrated MFM capacitor hosting two domains. We show that the MFMIS architecture not only free from the perils mentioned above but allows for an enormous improving MFMIS FET characteristics by coating the MFM capacitor with the dielectric capacitor in parallel connection. The proposed coating design that we call c-MFMIS FET, shown in Fig. 1f, provides degrees of freedom enabling a complete tunability of the dielectric parameters of the NC FET.

Results and discussion

Two-domain negative capacitance of the MFM capacitor

The nanodot-scale two-domain MFM is a major element of the MFMIS FET enabling the NC response via the charge-controlled motion of the DW. Following²⁴, we discuss in detail the negative capacitance of the MFM capacitor, which is the base of our proposed device. Shown in Fig. 2a is the general view of MFMIS FET. Figure 2b presents the vertical and horizontal cross-sections of a nanoscale ferroelectric disc-shape MFM capacitor integrated in the MFMIS FET. At the zero charge Q_f at the electrodes of the MFM capacitor, corresponding to the zero voltage at the transistor, the DW sits in the middle of the capacitor, see left hand side of Fig. 2b. The intrinsic charges at the respective electrodes redistribute in order to compensate the depolarization charges of each domain (keeping the total charge Q_f = 0) and to banish the electric field inside the ferroelectric disc, reducing thus the electrostatic energy. The finite charge Q_f, induced by the voltage V = V_g applied to the transistor gate, displaces the DW from its middle zero-voltage position, see right hand side of panels b. Accordingly, the intrinsic charges rearrange (maintaining the total charge Q_f) to compensate the depolarization fields of now unequal domains.

Fig. 2: Functioning of the MFMIS FET.

a A three-dimensional sketch of the MFMIS FET comprising a disc-shape ferroelectric capacitor with the negative capacitance. b Vertical and horizontal cross-sections of the MFMIS FET. At the zero gate voltage V = 0 (left hand side), the equilibrium location of the DW is in the middle of the ferroelectric disc. At the finite applied voltage, V = V_g, the DW displaces from the middle and bends (right hand side). c A sketch of the coated MFMIS FET, in which the ferroelectric disc is sheathed by the dielectric shell. The dielectric shell shares the top-gate and floating-gate electrodes with the ferroelectric disc, hence making a complimentary capacitor going in parallel with the ferroelectric capacitor. d Rectangular modification of the c-MFMIS FET. The extended area of coating and gate dielectric layer capacitors enhances the performance of the NC FET. e Normalized gate capacitance c_g as function of the coating size L_c. Colored areas show three distinct regimes of the gate functioning. f The sketch of the electric field (red arrows) and polarizations (black arrows) distribution inside the c-MFMIS FET upon applying voltage to the gate electrode.

The NC response arises since the length, hence the energy of the displacing DW, is sensitive to the shape of a ferroelectric capacitor. To ensure the best controlled performance of the NC, we choose a disc-like form of a capacitor. When moving apart from the middle, the DW not only compensates the electric field arising due to the charge transferred to the electrodes but, minimizing its surface self-energy, shrinks in the width w and bends because of the cylindrical shape of a ferroelectric. As a result, the DW overshoots towards the edge beyond the electrostatics-demanded equilibrium position at which the internal electric field would have disappeared. Hence the net electric field does not vanish but flips over and goes from the negatively charged electrode to the positively charged one. This counterintuitive outcome precisely expresses the phenomenon of the negative capacitance. Note, however, that at some threshold value of the applied charge, ${Q}_{f}^{* }$, when it becomes approximately equal to the depolarization charge of the uniformly oriented polarization, Q₀, the DW reaches the edge of the ferroelectric layer and leaves the sample. The monodomain state with positive capacitance restores; this corresponds to the termination of the red branch in Fig. 1b.

The quantitative description of the NC of the disk-shape two-domain ferroelectric capacitor is given by Luk’yanchuk et al.²⁴

$${C}_{NC}=-{\gamma }_{2}\frac{{D}_{f}}{{\xi }_{0}}{C}_{f},$$

(2)

where we explicitly spotlighted the capacitance C_f = ε₀ε_fS_f/d_f > 0, which is the capacitance of the monodomain MFM capacitor in the stable state at Q = ±Q₀ = ±S_fP₀ (minima of the W(Q) dependence in Fig. 1b). The negative factor, − γ₂D_f/ξ₀, reflects the features brought in by the DW displacement in the two-domain configuration. Here D_f and d_f are the diameter and height of the capacitor, respectively, ${S}_{f}=\pi {D}_{f}^{2}/4$ is the area of the ferroelectric plate surfaces, and P₀ is the polarization of the ferroelectric in the equilibrium state. The coherence length ξ₀ ≃ 1nm describes the DW thickness, the dimensionless geometric factor γ₂ ≈ 4.24 reflects the internal profile of polarization inside the DW and the DW bending in the cylindrical gate, and ε_f and ε₀ are the dielectric constant of the ferroelectric material and the vacuum permittivity, respectively.

Figure 1b displays the energy advantage of the two-domain state (whose energy is shown by the red curve), with respect to the usually considered uniform NC state (the blue dashed curve), both states preserving the same charge Q at the electrodes. To create the two-domain state from the uniformly-polarized state one has to suppress polarization in a fraction of the ferroelectric occupied by the DW, while to depolarize the monodomain state by the electric field due to the uniformly distributed charge Q, one would have had to suppress the ferroelectricity within the whole volume which is much more energetically costly.

As a next step, we integrate the MFM two-domain NC-capacitor into the MFMIS FET architecture.

The MFMIS FET

This device comprises the gate stack overimposed on a semiconducting substrate in which the source and drain parts are connected by the gate-operated conducting channel, see Fig. 2a. The gate stack includes the MFM capacitor and the gate insulating layer separating it from the substrate. This is the high-κ dielectric layer, preventing a charge leakage between the lower capacitor’s plate and the semiconducting channel.

The top MFM capacitor plate is the gate electrode connecting the transistor to the external voltage source. The bottom capacitor electrode is an intermediate electrically isolated floating gate electrode of the transistor that preserves the entire charge, most commonly the zero total charge, constant, stabilizing the ferroelectric two-domain state. Furthermore, the floating gate makes the potential along the ferroelectric interface even, maintaining, therefore, a uniform electric field across the gate stack and substrate. Along the way, the floating gate resolves a frequent issue of neutralizing the parasitic charges that may be trapped by interfaces during the fabrication and functioning. Maintaining the working charge and providing a regular rubbing out the parasite leaking charges with the removal time faster than the leakage time³¹ is achieved via the standard discharging methods. For instance, it is implemented by either harnessing the Fowler-Nordheim tunneling and the hot electrons injection³³, or by circuiting the gate by the auxiliary charge-carrying current, I_Q, contact, see Fig. 1e, to a certain source for a given combination of electric inputs ensuring the proper sequence of discharging and high resistance modes³⁴.

An effective electronic circuit of the MFMIS FET, shown in Fig. 1e, is similar to that of the multidomain MFIS FET (Fig. 1d). The difference is that now the task of leveling the depolarization field inhomogeneities is taken by the floating gate electrode. Therefore, the gate dielectric layer can be safely engineered as an utmostly thin one, down to the technologically-acceptable limit of a few nanometers. This increases C_d with respect to ∣C_NC∣, opening doors to making the gate capacitance negative, ${C}_{g}^{-1}={C}_{d}^{-1}-| {C}_{NC}^{-1}| \,<\, 0$. Yet it is hard to achieve a required largeness of C_d with respect to ∣C_NC∣ due to the restrictions imposed by materials compatible with the silicon CMOS technologies. To meet the challenge, we devise a coated c-MFMIS FET that critically changes the situation and breaks ground for the unlimited enhancement of the performance of the NC FET transistor.

The c-MFMIS FET

The coating of the ferroelectric layer with the dielectric oxide sheath confined by the same electrodes, see Fig. 2c, d straightforwardly incorporates an additional capacitor with the capacitance C_c > 0 in parallel to C_NC. This results in a radical improvement of the controlled tuning of the gate capacitance. In particular, manipulating with the sizes of the coating oxide layer and with the geometrical design of the device as a whole, provides a broad variation in its performance characteristics and functioning regimes. The panels (c) and (d) exemplify possible designs. The panel (c) shows an annulus-like coating capacitor, while panel (d) displays a rectangular design of the coating layer and, in addition, the possibility of increasing the area of the floating gate electrode with respect to the top gate electrode. The latter design allows for controllable increasing capacitances of the coating and gate-dielectric layers most efficiently, maintaining the miniaturization of the device. Note, that in all the geometries, the core ferroelectric should maintain its disc-like shape ensuring the optimal manipulation with the DW.

Shown in Fig. 1f is the equivalent circuit of c-MFIS FET. The important advance is that the gate capacitance becomes

$${C}_{g}=\frac{1}{{C}_{d}^{-1}+{({C}_{c}-| {C}_{NC}| )}^{-1}},$$

(3)

which permits tuning C_g over the widest range of values by the appropriate modifying the parameters of the coating capacitor. We reveal the rich dependence of C_g on the coating layer size, L_c choosing the rectangular geometry of the coating layer (Fig. 2c). The capacitance of the disk-shape two-domain ferroelectric capacitor, C_NC, is given by Eq. (2). The capacitances of the coating and gate dielectric layers are taken in a standard form as C_c = ε₀ε_cS_c/d_c and C_d = ε₀ε_dS_d/d_d, respectively. Here ${S}_{f}=\pi {D}_{f}^{2}/4$, ${S}_{c}={L}_{c}^{2}-{S}_{f}$ and ${S}_{d}={L}_{d}^{2}$ are areas of the ferroelectric, coating dielectric and gate dielectric plate surfaces, respectively.

The behavior of C_g defined by Eq. (3) is most generic and does not depend critically on the specific choice of materials. For practical applications, we choose both, the coating layer and the gate-dielectric layer, be composed of the Si-compatible dielectric HfO₂ with the respective dielectric constants ε_c, ε_d being approximately equal to 25. The ferroelectric disc of the diameter D_f ≃ 6 nm and thickness d_f ≃ 3 nm, can be fabricated out of the ferroelectric phase of HfO₂ or its Zr-based modification, Hf_0.5Zr_0.5O₂ with ε_f ≃ 50¹³. In fact, ε_f is the only relevant material parameter that defines the NC properties of the two-domain ferrolectric layer; therefore, the consideration applies equally well to other similar ferroelectrics, for instance, to perovskite oxides, like strained PbTiO₃ with about the same ε_f. The height of the gate dielectric layer is taken as d_d ≃ 3 nm, whereas the thickness of the coating layer, d_c, is equal to d_f. The size of the rectangular floating-gate electrode, L_d, defining the size of the gate dielectric capacitor, is taken as 1.2L_c.

Figure 2e displays the derived normalized gate capacitance, c_g = C_g/S_d as function of L_c. The presented c_g(L_c) dependencies are the Eq. (3) plots, into which the given above capacitancies, C_NC, C_c(L_c) and C_d(L_c) are substituted. Looking at the plots, one discriminates the three distinct regimes of the gate functioning set by two critical sizes, L_c1 < L_c2, of the coating layer: (i) the super-capacitance, L_c < L_c1, (ii) the negative-capacitance, L_c1 < L_c < L_c2, and (iii) the near-zero capacitance, L_c2 < L_c. All these three distinct regimes are of tremendous relevance for applications. Below, we restrict ourselves to the detailed analysis of the NC regime, i.e., the regime where c_g < 0, leaving the detailed discussion of regimes (i) and (iii) to forthcoming publication. Note that although in the NC regime the average polarization of the ferroelectric nanodot is aligned with the voltage drop across the capacitor, the electric field inside the coated layer is directed oppositely to it. Accordingly, the polarization induced inside the dielectric oxide sheath is opposite to the polarization of the ferroelectric nanodot, see Fig. 2f. It is important that the absolute value of the NC capacitance can be done arbitrary small on approach to the resonance regime ∣C_NC∣ = C_c of Equation (3), i.e., upon L − L_c2 → 0⁻. In this regime the nonlinear effects in the Q − V characteristics of the MFM capacitor become of prime relevance.

An unrestricted range of variation of c_g, from minus infinity to zero, as seen from Fig. 2e, allows for the unlimited tuning of the magnitude of the gate NC. In particular, the possibility of making it arbitrary small, enables us to overcome a previously insurmountable obstacle of the proper matching between the gate, C_g, and substrate, C_s, capacitancies and obtain the desirable value of the body factor

$$m=1+\frac{{C}_{s}}{{C}_{g}}=1+\frac{{C}_{s}}{{C}_{d}}+\frac{{C}_{s}}{{C}_{c}-| {C}_{NC}| }\,,$$

(4)

within the NC FET operational interval 0 < m < 1, getting thus the remarkably low values of SS(1), the task not achievable by previously suggested architectures.

Now the task is to find the optimal coating size L_c, given the normalized substrate capacitance c_s = C_s/S_d, that ensures matching to targeted value of m. To that end, we employ Eq. (4) which defines the implicit L_c dependence of c_s at given m. The shown in Fig. 3a family of L_c(c_s) curves for different m, confined between m = 0 (red) and m = 1 (brown) characteristics, represents the stable working interval for our exemplary c-MFMIS FET.

Fig. 3: Practical design of the c-MFMIS FET.

a A set of L_c(c_s) dependencies for determining the optimal parameters for the gate-substrate match in the c-MFMIS FET. The arrows define the procedure for selecting the optimal coating size ${L}_{c}^{{{{\rm{opt}}}}}$ providing the best performance and stability of the transistor. b Transport characteristics I_d(V_g) of the representative c-MFMIS FETs. The red curve shows I_d(V_g) for the optimally designed c-MFMIS FET. The green and blue curves show the I_d(V_g) dependencies for transistors with the steeper SS having the voltage-independent (green) and nonlinear in voltage (blue, with hysteresis) substrate capacitancies. c The charge-voltage characteristics, V_f(Q_f), of the disc-shape MFM capacitor. The monodomain and two-domain operational regions are displayed as the turquoise and purple, respectively, inter-shaded regions. The threshold charges $\pm {Q}_{f}^{* }$ at which the domain wall leaves the ferroelectric nanodot, mark the transition from the negative capacitance two-domain region (red curve) to the positive capacitance monodomain region (blue curves). The crosses stand for the results of the numerical simulations.

The region below the brown line where m > 1, i.e., SS > 60 mV dec⁻¹, corresponds to small sizes of the coating layer, L_c < L_c1. The region above the m = 0 curve but below the L_c = L_c2 line is the hysteretic loss of the reversibility region. Therefore, the proper choice of L_c, in the interval L_c1 < L_c < L_c2, enables the desired magnitude of m for a given value of the substrate capacitance c_s. Although in our model example, the lateral size of the coating layer varies between L_c1 ≈ 24 nm and L_c2 ≈ 38 nm, it can be significantly reduced down to practically the diameter of the ferroelectric disc, by increasing the dielectric constant of the coating material by factor of four.

Practical design. Optimal match between gate and substrate

The established characteristics of the c-MFMIS FET enable us to go beyond the past prima facie technological concepts and turn to the practical design in relevant industrial environment. The critical challenge⁹ emerging when engineering the NC FET, is the complex and highly nonlinear nature of C_s since the latter comprises contributions from the capacitance of the depleted layer, from the quantum capacitance due to charge carriers injected into the conducting channel, from the interface charges, and, finally, from the source/drain geometrical capacitancies. While being of a relatively low value when coming mainly from the capacitance of the depletion layer in the low-conducting regime at small voltages, C_s increases dramatically, typically by order of magnitude, due to the injection of conducting electrons into the channel caused by the gate bias near and above the threshold value.

Using our established concept of L_c(c_s, m) characteristics, Fig. 3a, enables the determining an optimal match between the NC gate capacitance and the semiconducting substrate capacitance ensuring the best-performance SS and stability of the transistor. To exemplify the nonlinear behavior of the substrate, we take the normalized capacitance ${c}_{s}^{{{{\rm{sth}}}}}\simeq 1{0}^{-2}$ Fm⁻² in the low-voltage subthreshold regime and ${c}_{s}^{{{{\rm{th}}}}}\simeq 1{0}^{-1}$ Fm⁻² in the high-voltage near-threshold regime. Next, we set the condition m = 0 at the steepest point of the I_d(V_g) curve, i.e., in the near-threshold gate voltage where ${c}_{s}={c}_{s}^{{{{\rm{th}}}}}$. This condition visualized by the point A in Fig. 3a, provides us with the optimal value of the size of the coating layer, ${L}_{c}^{{{{\rm{opt}}}}}\approx 28$ nm. Decreasing the gate voltage V_g to subthreshold values, reduces c_s and moves it to the left from the point A along the black line until reaching the point B corresponding to ${c}_{s}={c}_{s}^{{{{\rm{sth}}}}}$ at V_g ≈ 0. The body factor at the point B is m = 0.9 which gives SS ≈ 54 mV dec⁻¹.

The possible transfer I_d(V_g) characteristics⁹ are schematically illustrated in Fig. 3b. The optimal characteristic (red line) derived according to the devised above operating procedure starts with the relatively modest SS ≈ 54 mV dec⁻¹, steepens upon the increase in V_g, and reaches its steepest value in the near-threshold region. The location of points A and B corresponds to the capacitancies ${c}_{s}^{{{{\rm{th}}}}}$ and ${c}_{s}^{{{{\rm{sth}}}}}$ of panel a. The optimal regime maintains the steep slope of the I_d(V_g) dependence over the entire voltage working range and includes not only the subthreshold, but also near- and above threshold regimes, preserving the stable and hysteresis free I–V_g transfer characteristics at the same time.

Because of the nonlinearity of c_s, the transfer characteristics of the designed c-MFMIS FET with ${L}_{c}={L}_{c}^{{{{\rm{opt}}}}}$ demonstrates the better performance at the same on-off current switching ratio, I_on/I_off, than the shown by the green curve commonly assumed NC FET with the voltage-independent substrate capacitance c_s (although having the steeper initial SS). At the same time, an attempt to engineer the NC FET having the nonlinear c_s with an initially steeper SS (exemplified by the blue curve), results in the hysteretic switching instability.

Practical design. Compact gate model

In order to provide incorporating the two-domain c-MFMIS FET architecture into the industrially-standardized circuiting, we design the scalable compact model describing the Q_g–V_g characteristics of the coated NC gate stack. In the low-voltage and low-charge operational mode of the NC FET, this compact model is defined by the linear relation Q_g = C_gV_g, where C_g is given by Eqs. (2) and (3). Looking forward to extensive applications of our compact model for the description of the c-MFMIS FET, we expand the compact model’s working range over to the nonlinear regime where substantial shifts of the domain wall and even its escape from the sample may occur.

The complete set of the Q_g–V_g characteristics of the gate is defined by the individual electric properties of its components, including the gate dielectric capacitor, coating capacitor, and the MFM capacitor which form the equivalent circuit shown in Fig. 1f and which are characterized by the linear, ${V}_{d}={C}_{d}^{-1}{Q}_{d}$, ${V}_{c}={C}_{c}^{-1}{Q}_{c}$, and nonlinear, ${V}_{f}={V}_{f}\left({Q}_{f}\right)$, constitutive relations respectively. In general, the V_g–Q_g characteristics can be parametrically plotted as functions of the running parameter Q_f

$$\begin{array}{l}{V}_{g}=\left(1+\frac{{C}_{c}}{{C}_{d}}\right){V}_{f}({Q}_{f})+\frac{{Q}_{f}}{{C}_{d}}\\ {Q}_{g}={C}_{c}{V}_{f}({Q}_{f})+{Q}_{f}\,,\end{array}$$

(5)

based on the relations Q_g = Q_d = Q_c + Q_f, V_g = V_d + V_f, and V_f = V_d for the circuit in Fig. 1f.

The nonlinear constitutive relation, ${V}_{f}\left({Q}_{f}\right)$, of the MFM capacitor is the core relation that defines different regimes of the gate functioning. Shown in the Fig. 3c, are the results of the phase-field simulations (crosses), see Methods, and the analytical outcome of the developed scalable compact model (solid lines). The Q_f–V_f characteristic reveals two different operational modes of the MFM capacitors. The NC low-charge branch, ${V}_{2}\left({Q}_{f}\right)$ (red curve), corresponds to the two-domain state where the domain wall motion is responsible for the electric properties of capacitor. The high-charge branch, ${V}_{1}\left({Q}_{f}\right)$ (blue curve), with the positive differential capacitance, C_f = dV/dQ > 0, corresponds to the monodomain state where the domain wall is gone. As a result, the Q_f-V_f characteristic of the ferroelectric capacitor is presented by the synthetic dependence

$${V}_{f}\left({Q}_{f}\right)=\left\{\begin{array}{ll}{V}_{2}({Q}_{f})\quad &\,{{\mbox{if}}}\,\left|{Q}_{f}\right| \,<\, {Q}_{f}^{* }\\ {V}_{1}({Q}_{f})\quad &\,{{\mbox{if}}}\,\left|{Q}_{f}\right| \,>\, {Q}_{f}^{* }\end{array}\right.$$

(6)

where ${Q}_{f}^{* }$ is the charge at which the branches ${V}_{2}\left({Q}_{f}\right)$ and ${V}_{1}\left({Q}_{f}\right)$ meet.

The corresponding to the monodomain state branch of the V_f-Q_f characteristic, is given by the parametric dependence of V₁(Q_f) upon the polarization P,

$$\begin{array}{l}{V}_{1}(P)=-{d}_{f}\left(2{a}_{3}^{* }P+4{a}_{33}^{* }{P}^{3}+6{a}_{333}{P}^{5}\right)\\ Q(P)=-{S}_{f}\left(P-{\varepsilon }_{0}{\varepsilon }_{i}\frac{{V}_{1}(P)}{{d}_{f}}\right)\,,\end{array}$$

(7)

derived from the uniform Ginzburg-Landau equation. The coefficients ${a}_{3}^{* }$, ${a}_{33}^{* }$ and a₃₃₃, and the background dielectric constant ε_i are defended in Methods.

For the V₂(Q_f) function describing the two-domain case we use the analytical approximation²⁴

$${V}_{2}({Q}_{f})\approx -\frac{0.27}{\psi \left({Q}_{f}/{Q}_{0}\right)}\frac{{Q}_{f}}{{C}_{f}}\frac{{\xi }_{0}}{D},$$

(8)

where ψ(s) (0 < s < 1), introduced in Luk’yanchuk et al.²⁴, is the function accounting for the geometry of the system which we fit by

$$\psi (s)\approx {\left(1.0-0.027s-0.95{s}^{2}-0.34{s}^{3}+0.32{s}^{4}\right)}^{1/2}.$$

(9)

In the linear in Q_f approximation, where s → 0, Eq. (8) gives C_NC in Eq. (2).

Combining branches given by Eqs. (7) and (8) provides an excellent approximation for the results of the numerical simulations of the compact model, see Fig. 3c. The slight overshoots at $\pm {Q}_{f}^{* }$ correspond to numerical singularities appearing at the moments where the DW leaves the MFM capacitor.

To summarize, the achieved understanding that the fundamental mechanisms of the NC is the domain action, bestows closing the gap between the concept of the ferroelectric negative capacitance and its realization in electronic devices. It enables designing a stable NC-based FET, whose coating-shell architecture of the gate promises a notable enhancement of prospective performance and high tunability of characteristics allowing the perfect match with advanced FET architectures. Our findings lay out the way for scaling the NC FET nanoelectronics down to 2.5–5 nm technology nodes via utilizing the CMOS-compatible ultra-thin and ultra-small ferroelectric disc as a core of the NC gate.

Methods

Functional

To carry out the numerical modeling of polarization structures in a ferroelectric layer, we use the most thoroughly studied free energy functional for the PbTiO₃,

$$\begin{array}{l}F=\int \left({\left[{a}_{{i}}^{* }({u}_{m},T){P}_{{i}}^{2}+{a}_{{ij}}^{* }{P}_{{i}}^{2}{P}_{{j}}^{2}+{a}_{{ijk}}{P}_{{i}}^{2}{P}_{{j}}^{2}{P}_{{k}}^{2}\right]}_{{i\le j\le k}}\right.\\ \quad\quad\,\,\,\left.+\,\frac{1}{2}{G}_{{ijkl}}({\partial }_{{i}}{P}_{{j}})({\partial }_{{k}}{P}_{{l}})+({\partial }_{{i}}\varphi ){P}_{{i}}-\frac{1}{2}{\varepsilon }_{0}{\varepsilon }_{i}{(\nabla \varphi )}^{2}\right)\,{d}^{3}r,\end{array}$$

(10)

where the sum is taken over the cyclically permutated indices {i, j, k, l} = {1, 2, 3} (or {x, y, z}). Functional Eq. (10) includes the Ginzburg-Landau (GL) energy of the strained ferroelectric layer³⁵ written in a form given in³⁶ (the square-bracketed term), the polarization gradient energy³⁷ (the term with coefficients G_ijkl), and the electrostatic energy, including the coupling of polarization with electric field¹⁹, E_i = − ∂_iφ, described through the electrostatic potential φ (the two last terms). The strain-renormalized GL coefficients for the PbTiO₃ layer (accounting partially for the elastic energy) are taken as³⁵, ${a}_{1}^{* }$,${a}_{2}^{* }$ = 3.8 × 10⁵(T − 479^∘C) − 11 × 10⁹u_m C⁻²m²N⁻¹, ${a}_{3}^{* }$ = 3.8 × 10⁵(T − 479^∘C) + 9.5 × 10⁹u_m C⁻²m²N⁻¹, ${a}_{11}^{* }$, ${a}_{22}^{* }$ = 0.42 × 10⁹ C⁻⁴m⁶N, ${a}_{33}^{* }$ = 0.05 × 10⁹ C⁻⁴m⁶N, ${a}_{13}^{* }$,${a}_{23}^{* }$ = 0.45 × 10⁹ C⁻⁴m⁶N, ${a}_{12}^{* }$ = 0.73 × 10⁹ C⁻⁴m⁶N, a₁₁₁, a₂₂₂, a₃₃₃ = 0.26 × 10⁹ C⁻⁶m¹⁰N, and a₁₂₃ = −3.7 × 10⁹ C⁻⁶m¹⁰N. The misfit strain is taken as u_m = −0.013. The gradient coefficients are taken as for PbTiO₃ bulk material³⁷ (with all possible cubic index permutations), G₁₁₁₁ = 2.77 × 10⁻¹⁰ C⁻²m⁴N, G₁₁₂₂ = 0.0, and G₁₂₁₂ = 1.38 × 10⁻¹⁰ C⁻²m⁴N. The background dielectric constant of the non-polar ions was taken as ε_i ≃ 10³⁸ for PbTiO₃ and ε_i ≃ 25 for semiconducting layer. The vacuum permittivity is ε₀ = 8.85 × 10⁻¹² CV⁻¹m⁻¹.

Phase-field simulations

The minimum of the energy functional Eq. (10) is found by solving relaxation equation

$$-\gamma \frac{\partial {{{\bf{P}}}}}{\partial t}=\frac{\delta F}{\delta {{{\bf{P}}}}}\,,$$

(11)

where δF/δP is the variational derivative of Eq. (10); the time-scale parameter γ, which does not influence the sought energy minimum is taken equal to unity. The electrostatic Poisson equation ε₀ε_i∇²φ = ∇ ⋅ P, describing the spatial distribution of the polarization, is solved on the each respective relaxation step.

For practical implementation of simulations, we have used the open-source FEniCS computing platform³⁹. To create the tetrahedral finite-element meshes we used an open-source 3D mesh generator gmsh⁴⁰. For the case of the MFM capacitor, the computational region is a cylindrical volume Ω, restricted by the side boundary, ∂Ω_s, and by the top, ∂Ω_t, and bottom, ∂Ω_b, boundaries, see Fig. 4a. For the case of the MFSM heterostructure, the computational region is a rectangular box Ω, that includes the ferroelectric layer, Ω_F, and the semiconducting layer, Ω_S, see Fig. 4b. The computational region, Ω, is restricted by the left, right, front and back-side boundaries ∂Ω_s and by the top, ∂Ω_t, and bottom, ∂Ω_b, boundaries.

Fig. 4: Finite-element meshes.

a Cylindrical mesh used for two-domain simulations in the MFM setup. b Front-side view of rectangular mesh used for multi-domain simulations in the MFSM setup. The red and blue colors correspond to the up- and down- polarization directions, respectively.

The solutions for the polarization, P(r), and electrical potential, φ(r), distribution were sought in the functional space of the piece-wise linear polynomials. For simulation of the MFM-capacitor, controlled by charge Q, we use free boundary conditions for P(r) on the whole surface of the cylinder. At the same time, it was assumed that the electrodes produce almost uniform z-directed electric field, E_z = − ∂_zφ, spreading through the capacitor. The boundary constraint $-Q/{S}_{f}={\bar{P}}_{{z}}+{\varepsilon }_{0}{\varepsilon }_{i}{E}_{{z}}$ was used at the electrode interfaces to fix the applied charge Q that tunes the displacement of the DW in the spontaneously emerging two-domain structure. The bar denotes averaging over the interface surface.

For simulation of the MFSM heterostructure, the relaxation Eq. (11) was solved for the ferroelectric part of the sample while the electrostatic Poisson equation was solved for the whole domain. Boundary conditions for all the variables were taken to be periodic in the x direction. The size of the simulation rectangular box in x-direction, corresponding to the period of the spontaneously emerging domain structure was considered as an energy-minimizing parameter which was optimized for each series of calculations. Boundary conditions for P on ∂Ω_t and ∂Ω_b as well as on the front- and back surface boundaries of the rectangular box were taken as free boundary conditions. The Dirichlet boundary conditions were imposed on φ at the bottom and top surfaces of the box such that φ(∂Ω_b) = −U/2 and φ(∂Ω_t) = +U/2, to reproduce the application of the voltage U to the electrodes. The effective charge at the electrode was calculated as $Q=-{S}_{f}(\bar{P}+{\varepsilon }_{0}{\varepsilon }_{i}{\bar{E}}_{{z}})$.

To approximate the time derivative in Eq. (11), we used the variable-time BDF2 stepper⁴¹. The initial conditions for polarization distribution were taken to be random in the range of −10⁻⁶–10⁻⁶ C m⁻² for the polarization magnitude at the first time-step of simulation. The system of the nonlinear equations arising from the discretization of Eq. (11) was solved using the Newton-based nonlinear solver with line search and generalized minimal residual method with the restart^42,43. On each time step of the simulation in MFSM heterostructure, the linear system of equations obtained from the discretization of electrostatic Poisson equation was solved separately using a generalized minimal residual method with restart.