The SpinBus architecture for scaling spin qubits with electron shuttling

Quantum processor architectures must enable scaling to large qubit numbers while providing two-dimensional qubit connectivity and exquisite operation fidelities. For microwave-controlled semiconductor spin qubits, dense arrays have made considerable progress, but are still limited in size by wiring fan-out and exhibit significant crosstalk between qubits. To overcome these limitations, we introduce the SpinBus architecture, which uses electron shuttling to connect qubits and features low operating frequencies and enhanced qubit coherence. Device simulations for all relevant operations in the Si/SiGe platform validate the feasibility with established semiconductor patterning technology and operation fidelities exceeding 99.9%. Control using room temperature instruments can plausibly support at least 144 qubits, but much larger numbers are conceivable with cryogenic control circuits. Building on the theoretical feasibility of high-fidelity spin-coherent electron shuttling as key enabling factor, the SpinBus architecture may be the basis for a spin-based quantum processor that meets the scalability requirements for practical quantum computing.

The prospect of noisy intermediate scale quantum (NISQ) computing raises high expectations.However, it is likely that a significant part of the foreseen applications will only be accessible via quantum error correction to mitigate errors caused by noise, spurious coupling and crosstalk 1 .The resulting overhead leads to a need for millions of physical qubits, which requires highly nontrivial advances compared to today's devices.Electron-spin qubits in semiconductor quantum dots have the unique feature of being directly compatible with industrial CMOS processing 2 .At the level of few-qubit devices, all-electrical operation of single-and two-qubit gates above the error correction threshold have been demonstrated [3][4][5][6][7][8][9][10][11] .Furthermore, the operation of multi-qubit devices has been shown in several material systems [12][13][14][15] .Building on these promising results, the next challenge for semiconductor qubits is scaling-up in two dimensions while simultaneously maintaining high operation fidelities.A key challenge is the short range (≈ 100 nm) of the exchange interaction typically used for high-fidelity two-qubit gate operations.Architectures based on direct coupling thus lead to a crowding of gate electrodes and their wiring, referred to as the wiring fan-out problem, as well as significant inter-qubit crosstalk 16 .
To address these challenges, dense qubit arrays using crossbar network addressing schemes with reduced wiring density as well as sparse arrays of qubits with integrated classical electronics at cryogenic temperatures have been proposed 17 .Dense architectures based on crossbar addressing schemes typically apply the same control pulse to many qubits and thus require a challenging level of qubit homogeneity 18 .Tuning the qubit properties with local transistor-based circuits can somewhat ameliorate this issue, but imposes demands on transistor and capacitor size 19 that are well beyond current capabilities.Sparse arrays of qubits on the a) These authors contributed equally to this work.b) lars.schreiber@physik.rwth-aachen.dec) bluhm@physik.rwth-aachen.deother hand require a method for coherent qubit coupling in the order of 10 µm 17,20,21 .A possibility is to use electron shuttling, i.e., moving electrons between sites where qubits are manipulated, enabling local exchange-based twoqubit gates.Gate-based electron shuttling has been demonstrated in both GaAs/(Al,Ga)As and Si/SiGe.By implementing Landau-Zehner transitions between adjacent quantum dots in so-called bucket brigade mode, transport of single electrons and coherent transfer of electron spins has already been demonstrated [22][23][24][25][26][27] .Recently, single electron transport by socalled conveyor-mode shuttling was shown 28 , where a quantum dot used to trap the qubit is continuously translated to distant qubit sites, requiring a length-independent number of wires and also less tuning.In a 10 µm long prototype device, charge shuttling in one direction and back across a distance of 19 µm with a fidelity of 99.7 % has been achieved 29 .The concept and feasibility of coherent conveyor-mode electron shuttling was analyzed in detail by Langrock, Krzywda et al. 30 .The confinement potential is chosen much stronger than the background disorder potential, targeting an adiabatic motion that leaves the electron in the orbital ground state.With a shuttling velocity of a few m/s, electrons can be transferred fast enough to limit spin dephasing due to T * 2 -effects such as charge and hyperfine noise.However, nonadiabatic transitions between different valley and potentially orbital states set an upper bound on the velocity.For a minimal valley splitting of 20 µeV, a coherent transfer with an error rate below 10 −3 over a distance of 10 µm is predicted for a shuttling velocity of v = 8 m/s, which we assume throughout this paper.In a 1 µm Si/SiGe prototype device with natural abundance of Si isotopes (similar to reference 28 ), spin-coherent shuttling with maximum velocity of 2.8 m/s across an accumulated distance of at least 2.4 µm has been demonstrated.The spin dephasing time of the shuttled electron spin is enhanced by motional narrowing leading to a fidelity of approximately 99 % for the transfer of a spin quantum state over a nominal shuttling distance of 560 nm 31 .

SPINBUS ARCHITECTURE AND ITS ELEMENTS
In this manuscript, we present the SpinBus architecture, which leverages the conveyor-mode shuttling device named Quantum Bus (QuBus) as used in demonstration experiments 28,29,31 to connect qubits (Fig. 1a).Like established semiconductor qubit devices, the QuBus device employs a stack of electrostatic gates on top of a Si/SiGe heterostructure that confines electrons in the z-direction (Fig. 1b).Lateral screening gates define a one-dimensional channel in the xy-plane, while clavier gates placed above are used to generate moving quantum dots.Every fourth clavier gate is electrically connected, thus eliminating the need for fanning out each individual gate.Four phase-shifted sinusoidal signals V i , i = 1 ... 4, applied to the resulting four sets of clavier gates enable a continuous translation of the quantum dots.The signals V i have the form 28 Here, A S ∼ 100 mV is the signal amplitude and ϕ (t) = 2π f • t with frequency f is the phase with phase offset ∆ϕ i = π/2 (i − 1).Hence, the number of required signals is independent of the distance between qubit sites.A DC bias relative to the V i can be applied to Ohmic contacts to adjust the chemical potential.
Based on the QuBus component as coherent link, we propose a layout of tileable unit cells as building blocks for the quantum layer of the SpinBus architecture (Fig. 1c).The unit cell (Fig. 1d) provides the means for initializing, reading-out and performing gate operations in two specialized zones, i.e., the initialization and readout (IR) and the manipulation zone.Shuttling lanes connect both the operational zones and adjacent unit cells.We anticipate that a length of the shuttling lanes in the order of 10 µm will reflect a reasonable tradeoff between shuttling-induced errors and time versus space for wiring and local electronics 20 .The spatial separation between different manipulation zones and qubits avoids unwanted inter-qubit coupling and helps to address qubits individually, thus avoiding control crosstalk errors.This comes at the cost of shuttling errors, which add to the errors of locally executed gates.
The QuBus geometry is based on the recent demonstration experiments of conveyor-mode shuttling, where a separation of the screening gates by 200 nm, a gate width of 62 nm and a gate pitch of 70 nm have been used 28 .For the validation of the gate layouts with electrostatic finite-element-method (FEM) models (see Methods M1), we chose a slightly larger gate pitch of 100 nm including a global top gate that can be biased with a separate voltage V tg ∼ 100 mV.For the operation of some elements, micromagnets are placed in suitable locations approximately 150 nm above the quantum well.For magnetostatic modeling (see Methods M2), we assumed an external in-plane magnetic field B ext = 20 − 50 mT in the y-direction.
Two-dimensional connectivity is implemented by a threeway T-junction connecting two perpendicular shuttling lanes (Fig. 2a).Compared to a four-way junction, gate crowding is reduced and potential shaping simplified.The two supported operations are qubit motion in a straight line (straight shuttling) and around the corner (corner shuttling).Straight shuttling is implemented analogous to normal conveyor-mode operation, with the voltages on the perpendicular branch being constant.For corner shuttling, a quantum dot initially moving along the straight branch is stopped at the intersection and then transferred into the perpendicular branch.Fig. 2b shows the potentials during the adiabatic transfer using appropriately adjusted voltage pulses.Selected linecuts and the time evolution of the shuttling phases are presented in Extended Data Fig. 1.For both operations, the transport direction can be inverted by reversing the shuttling pulses.For coherent shuttling, the electron motion should reflect a smooth translation of the potential, rather than tunneling between disorderinduced stationary quantum dots.A useful metric for this requirement is the orbital splitting for the moving quantum dot containing the qubit.If it is similar to the values of 1-2 meV typically found in static quantum dots, one may expect the confinement to be dominated by the shuttling potential and thus a smooth transfer 30 .During straight shuttling, the orbital splitting equals or exceeds the threshold at all times (Fig. 2c).During corner shuttling, the orbital splitting drops to about 0.6 meV, slightly below the conservative target range (Fig. 2d).We expect that if needed, it can be increased by some combination of optimizing the geometry and pulse shapes, increasing the gate voltages, and dynamically adjusting the screening gate voltage.
The initialization and readout (IR) zone consists of a single electron transistor (SET) tunnel-coupled to a shuttling lane, thus enabling loading and detecting charges (Fig. 3a).Ohmic contacts on both sides of the SET provide source and drain reservoirs, and electrons are injected into the shuttling lane via the SET.Besides one plunger and two barrier gates for the SET, we propose two additional individually contacted gates at the beginning of the shuttling lane (Fig. 3b).The first controls the tunnel barrier to the SET and the second the potential of the first quantum dot in the QuBus channel.A second moving quantum dot can be controlled independently by the four sets of clavier gates.For qubit initialization and readout, Pauli spin blockade (PSB) in the resulting double quantum dot is utilized to enable simpler and faster readout discrimination than, e.g., spin-selective tunneling 32,33 .The required parallel magnetic field gradient ∆B is generated by a micromagnet placed directly above the shuttling lane adjacent to the SET.The initialization sequence follows standard procedures and is presented in Fig. 3c.It starts with loading two electrons into a first quantum dot (step I), forming a tunnel-coupled double quantum dot configuration (step II) while the second quantum dot is kept at a sufficiently higher potential during the adjustment of the inter-dot tunnel barrier (step III) to remain in a S(2,0) state.Sweeping the detuning ε transfers the S(2,0) state to a (1,1) configuration, where the gradient magnetic field splits the T 0 and S(1,1) into |↑↓ and |↓↑ (step IV).Thus, the |↓↑ will be occupied if the detuning is pulsed adiabatically with respect to orbital, spin and valley excitations, but including a short diabatic sweep over the ST − -crossing.Lastly, the spin-up state is shuttled away to be used as qubit.The spin-down electron can be kept in the first quantum dot as reference spin state for later readout.
The corresponding time traces for the shuttling phase ϕ (t) and detuning are shown in Extended Data Fig. 2. To implement readout, the initialization sequence is reversed and PSB is employed to determine the qubit's state.Any established method for SET readout can be used, though we speculate that baseband readout with cryogenic transistors [34][35][36] will yield the best performance-complexity trade-off.Single-and two-qubit gate operations are performed in the manipulation zone, which is formed by joining two shuttling lanes (Fig. 4a).Two independent QuBus elements en-able sufficient control over both detuning and tunnel coupling of a double quantum dot potential formed at the junction.Two micromagnets provide the necessary magnetic field gradients (Fig. 4b).For two-qubit gates and single-qubit gates, a micromagnet is placed off-center from the junction above one QuBus element.An additional micromagnet for single-qubit gates on the other side of the junction is located above the other QuBus element at a sufficient distance to avoid compromising the longitudinal field gradient at the junction.Thus, the manipulation zone allows performing singlequbit gates on two qubits independently.Shuttling the qubits 200 nm to 500 nm away from the junction for single-qubit gates can avoid crosstalk.Single-qubit gates are implemented by electric-dipole spin resonance (EDSR), in which an effective oscillatory transverse magnetic field for driving Rabi oscillations is generated by displacing the electron in a perpendicular magnetic field gradient.Unlike conventional EDSR manipulation, where the electron position oscillates typically up to one nanometer 3 , we propose a shuttling-mode EDSR building on the capability of moving the electron over arbitrary distances.For high fidelities, we estimate an oscillation amplitude in the order of 10 nm to be a good choice.The larger amplitude allows the use of significantly weaker magnetic field gradients, which reduces the sensitivity to charge noise.
For electron spin qubit platforms utilizing micromagnets, the natural choice for the implementation of CNOTlike two-qubit gates (see Methods M4) is the controlledphase (CPHASE) gate based on the exchange interaction J (t) between two tunnel-coupled quantum dots [37][38][39] , which is switched adiabatically with respect to a Zeeman energy difference ∆E Z between the two quantum dots.This configuration is achieved by shuttling both electrons to the junction at the center of the manipulation zone (Fig. 4c) with pulses as shown in Extended Data Fig. 3 while maintaining zero detuning.The control of the exchange coupling via the inter-qubit distance while maintaining zero detuning essentially amounts to barrier control, which features a lower charge noise sensitivity compared to controlling the exchange interaction via the detuning 5,40 .Fig. 4c shows the simulated potentials during the formation of a double quantum dot.The separation and barrier height during the two qubit gates are similar as in conventional quantum dot structures, thus validating the robustness of the procedure with respect to disorder.The absence of tunnel coupling to other sites further increases this robustness in comparison to arrays with multiple quantum dots.

FIDELITY OF QUANTUM OPERATIONS
To estimate the achievable performance, we simulated the dynamics of each quantum operation using the simulation package qopt 41 , including an optimization of the control pulses (see Methods M3).The fidelities were computed based on a noise model including quasistatic nuclear spin Step IV: applying a detuning sweep to transfer S(2,0) to |↑↓ followed by a shuttling pulse to inject the qubit into the shuttling channel.
noise affecting the Zeeman splitting as well as quasistatic and white charge noise with amplitudes extracted from past experiments 3,42,43 .With appropriate calibration, the combination of quasistatic and white charge noise can serve as a conservative proxy for 1/ f -noise typically found in real devices.We included coupling of the charge noise to the qubit via the detuning affecting the exchange coupling as well as via position fluctuations.The latter affect the single spin dynamics due to the magnetic field gradient as well as the exchange coupling at zero detuning.This noise model covers the effects we consider as experimentally most relevant and was shown to be in good agreement with experimental results 44 .For the initialization and readout procedure, we identified fast charge noise as the main limiting factor and obtained fidelities above 99.9 % if parasitic inter-dot orthogonal magnetic field gradi-ents remain sufficiently small (see Methods M2).To evaluate single-qubit operations, we applied a sinusoidal shuttling EDSR-pulse in resonance with the Zeeman splitting to a qubit model with spin and valley degree of freedom.We identified fast charge noise causing position fluctuations as the dominating noise contribution and find fidelities exceeding 99.9 % as long as the valley splitting is greater than 30 µeV and does not exhibit an exceptionally strong variation.For two-qubit gates, the relevant infidelity contribution arises from quasistatic position noise affecting the exchange interaction and we obtain a fidelity of 99.9 %.

OPERATING CONCEPT AND SYSTEM COMPLEXITY
The two-dimensional array of the architecture is well suited for the implementation of surface codes, which can be considered as the mainstream concept for quantum error correction 1 , as well as NISQ algorithms.As exemplary operation, we show the elementary surface code gate sequence in Fig. 5, requiring a square array of qubits with nearest-neighbor coupling.Every second qubit serves as data qubit storing quantum information, and every other one as ancilla qubit, each detecting one of two possible types of errors called X and Ẑ stabilizers 45 .As each manipulation zone can simultaneously operate two qubits, each unit cell is identified with one data qubit highlighted in blue and one adjacent ancilla qubit highlighted in green and yellow, respectively (Fig. 5a).An error detection cycle consists of initializing the ancilla qubits, CNOT gates with the four adjacent data qubits, which we choose as stationary, and subsequent readout of the ancilla qubits.Realizing such a cycle in the SpinBus architecture requires the shuttling of ancilla qubits to and from different manipulation zones between local gate operations (Fig. 5b).
As the wiring density can be a main limiting factor for the size of processor achievable with a given integration approach, we present an estimate of the number of required signals based on an economical operating strategy detailed in Supplementary information S2.Considering shuttling signals (also used for qubit control) and additional local AC and DC signals of the IR zone and the screening gates, a quantum processor chip with N unit cells requires 14 N + 4 AC and 3 N + 4 DC signals.While there are no inherent scaling limitations to our architecture at the quantum layer, the wiring requirements have to be compatible with cryostat wiring, packaging and back-end-of-line (BEOL) technology.We estimate that currently available wiring solutions in cryostats of about 1,000 coaxial cables 46 are the most limiting factor and can accommodate a quantum processor chip with 9 × 8 = 72 unit cells.This corresponds to 144 simultaneously operable qubits if two qubits per unit cell are loaded.Storing additional qubits away from manipulation zones can further increase the qubit number.

CONCLUSION
In summary, we have detailed a concept to leverage electron shuttling for the realization of a semiconductor-based quantum processor with 2D coupling, as required for quantum error correction based on the surface code.To validate the feasibility, we performed electrostatic simulations for all device layouts and modes of operation.For the estimation of operation fidelities, we used realistic noise models and obtained fidelities for single-and two-qubit gates exceeding 99.9 %.The fabrication is possible with present-day industrial semiconductor processing.Furthermore, the architecture is compatible with established packaging and wiring techniques such as back-end-of-line (BEOL) via fabrication and flip-chip bonding.While we considered an implementation in Si/SiGe, the SpinBus architecture can potentially be transferred to other types of gate-defined semiconductor qubits.
Our architecture proposal features a number of strengths, but it clearly hinges on the theoretically predicted feasibility of spin-coherent electron shuttling.While first experiments on spin-coherent transport are promising, an implementation with high fidelity and mitigating low values of the valley splitting in Si/SiGe (see Supplementary information S1 for details) will be an essential next step.Reaching the projected fidelities and required yield could quickly put semiconductor qubits on the map for NISQ-type quantum computing.The combination with cryoelectronic control systems, which is facilitated by the variable qubit spacing, robust coherence of semiconductor qubits, the purely capacitive load of gate electrodes and the relatively low operating frequency could carry to much larger systems, eventually enabling error corrected quantum computing.As outlined in Supplementary information S3, recent advances in cryoelectronics and packaging provide concrete perspectives on how this goal can be tackled.

M1. Electrostatic simulations and orbital splitting
For the calculation of the electrostatic potentials, we employed finite-element-method (FEM) simulations using COMSOL Multiphysics ® .For each operational element, as shown in Figs.2a, 3a, 4a of the main text, we solved Poisson's equation: with the electrostatic potential Φ, charge density ρ, dielectric constant of the sample ε(r) and the vacuum permittivity ε 0 .Dirichlet boundary conditions corresponding to the applied voltages were imposed at metallic gates.As the structure is intended to be filled with dilute electrons representing qubits whose behavior will be fully governed by the electrostatic potential in their absence, their charge was not included in ρ.We used the linearity of the model to simplify the variation of the applied voltages V i by calculating basis potentials Φ of each gate i separately and combining the resulting total potential Specifically, Φ i is the potential for gate i set to 1 V with all others at 0 V.This superposition approach is justified in regions where no or only very few electrons are present.In the IR zone, however, one needs to take the reservoir's contribution to ρ into account.To do so, we first used the Thomas-Fermi approximation and solved the Poisson equation selfconsistently, assuming a depleted 2DEG in the channel and SET, for a specific gate voltage configuration that leads to the intended occupation of the reservoirs.To simplify fine tuning of the gate voltages via the superposition approach, we subsequently modeled the reservoirs analogous to metallic gates, thus assuming perfect screening.The position of these gates was obtained from the region of nonzero charge density of the initial Thomas-Fermi solution.This neglects a change of the reservoir region in response to gate voltages and introduces a small error as the gradual screening by the 2DEG in the reservoirs is replaced by a hard boundary conditions.As the reservoirs are relatively far from the region of interest, these approximations are compatible with our goal of demonstrating the feasibility o create an appropriate potential.The potential energies shown in figures are referenced to the conduction band edge and given as V = −eΦ.
For quantifying the effect of the variations in confinement in the T-junction (Fig. 2), we calculated the orbital splitting for the simulated potential of the quantum dot confining the qubit by solving the time-independent Schrödinger equation in two dimensions for each time step.

M2. Micromagnet design
Considering the requirements for the gate operations, we identified suitable dimensions for Cobalt micromagnets which provide the necessary field gradients.The resulting geometries and corresponding gradients are summarized in Table 1.Using thin layers ensures sufficient remanent magnetization when operating at low external magnetic fields, which we substantiated with OOMMF 47 -simulations using material parameters from 48 .Note that the perpendicular field gradient ∆B ⊥ for two-qubit gates arising from the magnet geometry is neither required nor harmful.As it is weaker than in the single-qubit zone and the gate duration is comparable, resulting relaxation errors are expected to be negligible.

M3. Operation fidelities
To verify the feasibility of the architecture, we performed quantum dynamic simulations of each quantum operation using the simulation package qopt 41 .We calculated the quantum dynamics by solving the time-dependent Schrödinger equation for adequate model Hamiltonians to identify simple control pulses for initialization and readout, single-qubit gates and two-qubit gates.To extract meaningful fidelities, we included realistic noise values from past experiments 3,42,43 .All simulations were performed assuming the g-factor of Si.
For the initialization and readout procedure, we simulated a linear ramping pulse which converts between the S(2, 0) and |↓↑ -state by sweeping the potential detuning ε of a double quantum dot adiabatically, besides a jump over the avoided ST − -crossing.We utilized a Hamiltonian truncated to the relevant three-state basis of {|T 0 , |S , |T − }, taking the Zeeman splitting (B ), parallel (∆B ) and orthogonal (∆B ⊥ ) field differences between two dots from micromagnet simulations and experimental data for the exchange energy J(ε) from Dial et al. 42 .Including further fast charge noise of √ S ε = 0.02 neV/ √ Hz (adopted from Dial et al. 42 assuming a lever arm of 0.1) and optimizing a jump in ε at the avoided crossing of |T − and |S induced by unintentional orthogonal field gradients gives target state fidelities exceeding 99.9 % when choosing pulse lengths t ∼ 200 ns, fields of B ≥ 20 mT, ∆B ∼ 1 mT and a parasitic a inter-dot orthogonal magnetic field gradient ∆B ⊥ 0.3 mT.The separation of the electrons, which is well established, was assumed to occur perfectly adiabatically without thermal or dynamic excitation.
For single-qubit EDSR, spin and valley degree of freedom were considered in the Hamiltonian with σ i and τ i denoting Pauli matrices on spin and valley space, respectively, ∆ VS = ∆ VS,x + i∆ VS,y is a complex matrix element describing the coupling of the two lowest neardegenerate valley states in silicon 49 as a function of the electron position x and κ SVC,i = 0.01 µeV parametrizes a g-factor variation between the valley states.EDSR-pulses as enveloped sinusoidal drives were then optimized for resonance frequency with the software framework qopt 41 and evaluated with respect to a process fidelity in the sense of Wood et al. 50, taking into account leakage as valley excitations entail phase errors in subsequent operations 30 .From the simulations we identified fast charge noise as the dominating noise contribution, which we modeled as an effective positional fluctuation of √ S = 0.1 fm/ √ Hz based on the experiments of Dial et al. and Yoneda et al. 3,42 .Taking into account the design choice of weaker magnetic gradients ∂ B ⊥ ∼ 0.1 mT/nm, our results indicate displacement amplitudes of around 20 nm (peak-to-peak) as a viable operation point to uphold a Rabi frequency near 10 MHz.This displacement amplitude constitutes a trade-off between achievable Rabi frequency and decoherence due to leakage on the valley space from potentially non-uniform valley splitting over the increased traveling distance of the electron during the pulse compared to previous experiments.The possibility to reach a fidelity of 99.9 % was found to be strongly correlated with the presence of a valley splitting 30 µeV with sufficient spatially uniformity.Employing a model for ∆ VS incorporating alloy disorder effects on the valley splitting recently proposed in Wuetz et al. 51 then yields > 80% probability for fidelities > 99.9 % in the initial environment of the electron inside the manipulation zone under the assumption of E VS = 2 |∆ VS | = 100 µeV, which is a conservative value compared to the current state of the art 52 .Adjustment of the electron position within the range of manipulation zone, and therefore its valley environment, can further be utilized to circumvent spots with pathological behavior of the valley splitting that compromises the performance.Two-qubit interaction was examined by doubling the Hamiltonian Eq. ( 5), additionally introducing a dot distance d dependent exchange energy J(d), and optimizing a CZ-class gate from local invariants 53 with an adiabatic pulse bringing together both electrons.The exchange energy J(d) was calculated by solving the two-electron Schrödinger equation in one spatial dimension along the channel for each potential configuration of the shuttle pulse.d was obtained as the separation between the minima of the double well potential in the two QuBus elements adjacent to the manipulation zone.Physically, both gate voltage fluctuations as well as charge noise contribute to fluctuations in J. Rather than modelling these independently, which is difficult to calibrate based on experiments anyway, we introduced an effective noise in d.The relevant infidelity contribution then arose from quasistatic modifications affecting the exchange interaction, which we estimated conservatively from Yoneda et al. 3 to σ d = 10 pm.This mathematical parametrization of J-noise in terms position fluctuations can be expected to give a reasonable estimate because position variations directly translate to a change in the barrier height and width, which is the main factor for J in the assumed barrier control mode.The assumed magnetic field gradient of ∂ B ∼ 0.1 mT/nm was found suitable to realize entangling dynamics of CZ-class interaction on timescales of t int ∼ 50 ns with a fidelity exceeding 99.9 % conditional on coherent electron shuttling capabilities requiring sufficient ( 30 µeV) valley splitting.

M4. CNOT gate synthesis
CNOT gates are synthesized from CZ gates 11 (Fig. 6), since for electron spin qubit platforms utilizing micromagnets, the natural choice for the implementation of CNOT-like two-qubit gates is the controlled-phase (CPHASE) gate.It requires a Zeeman energy difference ∆E Z and an adiabatically switched exchange interaction J (t) between two tunnel-coupled quantum dots [37][38][39] .The actual gate operation is based on adiabatically turning on the exchange interaction J (t), which shifts the energy levels of the antiparallel spin states in such a way that they acquire additional phases.Applying an exchange pulse for a duration τ = π h/J combined with appropriately calibrated single-qubit gates 5,7,11,54 allows the implementation of a controlled-Z (CZ) gate or a CNOT gate to realize a universal gate set 11 .An important aspect for the realization of any shuttlingbased architecture in the Si/SiGe platform will likely be the distribution of the variation of the valley splitting in Si/SiGe heterostructures.A recent publication by Wuetz et al. 51 suggests that the valley splitting is dominated by alloy disorder and thus varies randomly across different quantum dot positions.Occasional small valley splittings are unfavorable for resonant EDSR-driving with fast electron movement and shuttling coherence, but can be mitigated by adjusting the shuttling path and manipulation position.Possible modifications of the heterostructure, including Ge spikes 55 , increased 51 or oscillating 56 Ge concentrations inside the quantum well, may reduce the occurrence of small valley splittings or ideally avoid them altogether.Analogously, the effect of occasional detrimental defects located in the shuttling channel can as well be mitigated by optimizing the shuttling path.In the worst case, a faulty unit cell can be omitted by mapping an algorithm to physical qubits differently.

S2. Wiring complexity and solutions
As the wiring density can be a main limiting factor for the size of processor achievable with a given integration approach, we present an estimate of the number of required signals based on an economical operating strategy.The shuttling lanes in Fig. 1c and d  The envisioned operating mode is that these shared lanes periodically move up and down by one or several unit cell sizes and that electrons can be transferred onto them from the horizontal red and blue lanes, which are controlled individually for each unit cell.Either of these individually controlled shuttling lanes is also used for single-qubit gates, while both of them are utilized for a two-qubit gate at their junction.The use of the same signals for the vertical and horizontal red sections in one unit cell is enabled by the assumption that the IR zone is only used when no qubit in the horizontal red lane and no qubit in the blue lane is near the T-junction to the IR zone when the red horizontal lane is active.For the independent operation of the IR zones and to compensate disorder, we also propose local control of the first two individual clavier gates in the shuttling lane and of the SET plunger gate to maintain a sensitive operating point.In addition, one readout wire per cell needs to have a Megahertz-scale bandwidth.If the shuttling path needs to be controlled to avoid disorder or sites with low valley splitting (section S1), a few signals per unit cell applied to the screening gates need to be added, with the exact number depending on the required degree of independent control.We thus estimate that a quantum processor chip with N unit cells requires 14 N + 4 AC signals.
Analogously, DC voltages are also either shared across all unit cells or individually provided for each unit cell.For the screening gates defining the shuttling channels, inducing gates for SET reservoirs and the global top gate, three global DC voltages are sufficient.For adjusting the reservoir potential to the shuttling lanes, the voltage on the second Ohmic contact to the SET should be tunable.In addition, two SET barrier gates must be tuned.T-junctions and manipulation zones do not require additional DC voltages.Lastly, grounding of the micromagnets is optional and can be shared across all micromagnets.Hence, 3 N + 4 DC voltages are needed.
While there are no inherent scaling limitations beyond gate and shuttling errors to our architecture at the quantum layer, the wiring requirements have to be compatible with cryostat wiring, packaging and back-end-of-line (BEOL) technology.We estimate that currently available wiring solutions in cryostats of about 1,000 coaxial cables 46 are the main limiting factor and can accommodate a quantum processor chip with 9 × 8 = 72 unit cells.The highest on-chip wiring density occurs at the edge of the quantum plane and requires a few wiring layers for fan-out, which can be realized using standard BEOL technology.Assuming a unit cell size of 10 µm × 10 µm and a conservative wiring pitch of 500 nm in the on-chip wiring layers, each wiring layer can accommodate 720 lanes along the circumference of the quantum layer, whereas unit cells provide sufficient space to extend all vias across the required number of wiring layers.Thus, a few wiring layers are sufficient to route all signals to the edges of the quantum processor chip or spread them across the surface depending on the connection scheme.
For connecting the chip to a printed circuit board (PCB), high-density socket solutions are an established technology enabling as high as 6,096 connections in consumer devices 57 .Commercial land grid array (LGA) solutions that allow for chip-to-board connection are available with contact pitches as low as 0.4 mm and are validated for cryogenic operation 58 .Assuming a dense connection arrangement and neglecting additional ground connections this results in a chip size of 14 mm by 14 mm.Finally, we estimate the footprint of the connection from the PCB to the coaxial wiring in the cryostat based on current sub-miniature coaxial connectors.For example, Rosenberger WSMP® connectors can feature a centerto-center spacing of 2.15 mm while maintaining the signal integrity of a coaxial connector for frequencies up to 100 GHz 59 .This results in a PCB area of ∼ 50 cm 2 for 1000 connectors, including some overhead for screws etc. Flex-cable solutions can enable an even higher density 60 .DC wiring using flexconnectors will have a negligible footprint compared to the high frequency connections.

S3. Scaling perspective using cryoelectronic control circuits
The proposed layout is well suited for implementing surface codes for quantum error correction, and the predicted fidelities are in the range of what is needed to achieve a reasonable logical qubit performance and overhead.Individual logical qubits are thus within reach for qubit numbers that are reachable with conventional control and packaging and approaches as outlined above.For large scale quantum computing with many error corrected qubits, however, such solutions are less appealing.Here, integrated control solutions offer an attractive pathway.The SpinBus architecture features good prospects in this respect because the purely capacitive impedance of control electrodes, low operating frequency and robust coherence of spin qubits facilitate the use of cryogenic CMOS control circuits.The variable unit cell size can be adjusted to the required size of dedicated control circuits for each unit cell, so that direct wiring, e.g., via flip chip bonding, can eliminate the wiring fan out problem.First estimates of the size of control circuits for spin qubits lead to values in a compatible range 20 .Next to the size of control circuits, their power dissipation will be a concern in the light of limited cooling power at low temperature.For DC bias, a consumption at level of a few nW per channel has already been shown 61 .Furthermore, thermally isolating flip-chip solutions may allow the operation of electronics at a higher temperature than the qubits 62,63 , making cooling powers potentially at the levels of Watts accessible.While it remains to be seen if the dynamic qubit and shuttling control signals can be generated within the resulting power budget, a possible approach is to select from externally generated pulses using simple cryo-CMOS switches and tuning the qubit response to these fixed pulses using DC gate voltages 64,65 .For readout, heterojunctionbipolar-transistors (HBTs) allow single-shot readout in less than 10 µs at powers below 800 nW 36 , which likely can be reduced with optimized sensor designs 66,67 .

Fig. 1 |
Fig. 1 | Layout and operation of the QuBus device as building block for the SpinBus architecture.a, 3D visualization of the QuBus device consisting of two lateral screening gates defining a 1D electron channel and periodically connected clavier gates.The four gate sets connected to different control signals V i are color coded.b, Schematic of the Si/SiGe heterostructure providing the quantum well (QW).Linecuts of the traveling potential generated by the gate stack are depicted for four different phases ϕ (t).The occupied potential minimum is indicated by a red circle.The gate stack is depicted above the potential linecuts.c, The quantum processor chip consists of unit cells tiled like a brick wall.One unit cell is highlighted, the heterostructure is visualized transparently in most areas and local electronic components are shown symbolically.Unit cells are connected via the green colored shuttling lanes controlled by a signal set shared across unit cells.Red and blue colored shuttling lanes are controlled individually in each unit cell.d, A unit cell consists of three T-junctions for 2D connectivity, an initialization and readout zone, and a manipulation zone.We expect a spatial extent of unit cells in the order of 10 µm.

Fig. 2 |
Fig. 2 | Layout and operation of the T-Junction.a, 3D visualization of the T-junction consisting of two perpendicularly joined QuBus elements.Straight shuttling (red path) and corner shuttling (blue path) are shown.b, 2D potentials for different points in time during corner shuttling.White dashed lines indicate the positions and lengths of the linecuts in Extended Data Fig. 1a.Arrows indicate the shuttling direction.c, The orbital splitting during straight shuttling is always sufficiently large.d, During corner shuttling, the confinement dips more significantly, but still remains above 0.6 meV near the target range and can be optimized further.

Fig. 3 |
Fig. 3 | Layout and operation of the initialization and readout (IR) zone.a, 3D visualization of the IR zone consisting of a QuBus element adjacent to an SET, and a micromagnet.Two gates adjacent to four sets of clavier gates are two individually controlled.b, Cross-section including the gate layout showing the schematic double quantum dot potential and simulated magnetic field gradient along the shuttling channel.Red and blue circles represent the positions of two electrons in a double quantum dot configuration.c, Potential linecuts while initializing a qubit using PSB (blue arrows represent the electrons' spin states).The color-coded bars correspond to the gates from panels a and b, and their vertical positions indicate the applied voltage V i .Tunnelling is indicated by dashed black arrows and solid black arrows mark the translation of quantum dots.Step I: loading of a S(2,0) state from the SET into the first quantum dot.Step II: moving a second quantum dot close to the first quantum dot.Step III: detuned double quantum dot.Step IV: applying a detuning sweep to transfer S(2,0) to |↑↓ followed by a shuttling pulse to inject the qubit into the shuttling channel.

Fig. 4 |
Fig. 4 | Layout and operation of the manipulation zone.a, 3D visualization of the manipulation zone consisting of two joined QuBus elements and two micromagnets.Shown is an exemplary two-qubit operation.b, Cross-section including the gate layout showing the required magnetic field gradients for single-and two-qubit gates along the manipulation zone.The green circle shows the position of the qubit during the single-qubit gate operation and is driven periodically in the region of a large perpendicular magnetic field gradient |∂ x B ⊥ |.The two orange circles indicate the positions of the qubits during the two-qubit gate operations.Both are pushed together at the location of a large parallel magnetic field gradient |∂ x B |. c, Potential linecuts showing the smooth formation of a tunnel-coupled double quantum dot potential appropriate for two-qubit operations as the two translated quantum dots approach the center of the manipulation zone.The color-coded bars correspond to the gates from panels a and b, and their vertical positions indicate the applied voltage V i .

Fig. 5 |
Fig. 5 | Exemplary surface code implementation in the SpinBus architecture.a, Mapping of data and ancilla qubits to unit cells.Each diagonal line segment represents a required qubit interaction.b, Shuttling paths for an ancilla qubit in order to implement an X stabilizer.Associated data qubits are designated with a, b, c, d.Arrows mark the shuttling paths to all involved manipulation zones, whereas the numbers indicate the order of operations.

Fig. 6 |
Fig.6| CNOT gate synthesis A CNOT gate is synthesized by a CZ gate, including Hadamard-like operations to account for necessary single-qubit operations (e.g., ẑ rotations).

. 1 |. 2 |Extended Data Fig. 3 |
Potential linecuts and shuttling phases during T-junction operation.a, Linecuts of the potential for different times during corner shuttling.Colors correspond to the frames in panel Fig. 2b.Successive linecuts are shifted for clarity.b, Time evolution of shuttling phases during corner shuttling for the initial perpendicular (red) and target longitudinal (green) shuttling element.Time evolution of the shuttling phase ϕ(t) and interdot-detuning during initialization.Dashed lines indicate the points in time of the potential linecuts in Fig. 3c.Time evolution of shuttling phases during a two-qubit operation.Included is a wait time of τ wait = 50 ns for the actual two-qubit gate.Dashed lines indicate the points in time of the potential linecuts in Fig. 4c.
are color-coded accordingly to indicate which shuttling lanes are controlled globally or at the individual unit cell level.The vertical shuttling lanes colored green are intended for the connection of unit cells and are controlled at a global level, so that four shared AC signals can suffice.

Table 1 |
Dimensions of the micromagnets for the IR zone and manipulation zone, respectively, and associated magnetic field gradients.IR: initialization and readout.SQT: single-qubit gates.TQG: two-qubit gates.