Sub-volt high-speed silicon MOSCAP microring modulator driven by high-mobility conductive oxide

Silicon microring modulator plays a critical role in energy-efficient optical interconnect and optical computing owing to its ultra-compact footprint and capability for on-chip wavelength-division multiplexing. However, existing silicon microring modulators usually require more than 2 V of driving voltage (Vpp), which is limited by both material properties and device structures. Here, we present a metal-oxide-semiconductor capacitor microring modulator through heterogeneous integration between silicon photonics and titanium-doped indium oxide, which is a high-mobility transparent conductive oxide (TCO) with a strong plasma dispersion effect. The device is co-fabricated by Intel’s photonics fab and our in-house TCO patterning processes, which exhibits a high modulation efficiency of 117 pm/V and consequently can be driven by a very low Vpp of 0.8 V. At a 11 GHz modulation bandwidth where the modulator is limited by the RC bandwidth, we obtained 25 Gb/s clear eye diagrams with energy efficiency of 53 fJ/bit.


Introduction
Optical microring resonators have emerged as a key building block of photonic integrated circuits (PICs) that can function as versatile optical devices including modulators, wavelength filters and multiplexers, in comb lasers, weight banks for neuromorphic computing, and optical sensors [1][2][3] .They are playing increasingly critical roles in optical communication, optical interconnects, optical computing, and biomedical sensing due to their ultracompact footprint and capability for on-chip wavelength-division multiplexing (WDM) 4 .Although optical microring resonators have been implemented on various platforms such as thin-film LiNbO3 5 , silicon nitride 6 , and plasmonics 7 , active silicon microring modulators (Si-MRMs) that can perform high-speed electro-optic (E-O) modulation as the photonic engine for future PICs remains as the climax of research [8][9][10] .Silicon photonics provides a mature, cost-effective platform to integrate Si-MRMs with lasers, photodetectors, passive optical devices, and even microelectronic circuits through standard foundry fabrication, which is still the only feasible solution to build large-scale PICs with both active and passive devices for complex systems 11,12 .
Existing Si-MRMs available in the foundry process are based on reversed PN junctions, which can achieve ultra-high modulation bandwidth but usually require more than 2 V of driving voltage (Vpp) [13][14][15][16] .Such high Vpp is induced by the relatively weak plasma dispersion effect of silicon and the small capacitance per unit length of the reversed PN-junction, which is usually less than 2 fF/μm 17,18 .The high Vpp makes it unfeasible to drive Si-MRMs directly by CMOS logic circuits.For example, today's 5nm CMOS has a core supply of 0.65 V and input/output supply of 1 V 19 .Therefore, high voltage-swing CMOS transmitter (TX) circuits that consume hundreds of milliwatts of power must be used to drive the Si-MRMs.For instance, the 106 Gb/s 2.5 Vpp Si-MRM driver using 28nm CMOS process consumes 1.33 pJ/bit energy with Pulse-amplitude modulation 4-level (PAM-4) while the Si-MRM itself usually consumes less than 100 fJ/bit energy 20 .As a comparison, MOSCAP-driven Si-MRMs can achieve a much larger capacitance density using ultra-thin high dielectric constant insulators such as HfO2.In addition, MOSCAP devices allow heterogeneous integration of more E-O efficient gate materials with Si waveguide such as III-V compound semiconductors and graphene [21][22][23][24][25][26][27][28] .In the past two decades, high-speed MOSCAP Si-MRMs, including heterogeneously integrated functional materials, have been demonstrated (Supplementary Information I) 7,10,[29][30][31][32][33] .Nevertheless, a high-speed Si-MRM with sub-volt Vpp and large E-O modulation efficiency has not been reported.
In this article, we demonstrate a highly efficient MOSCAP Si-MRM heterogeneously integrated with titaniumdoped indium oxide (ITiO), a TCO with high carrier mobility.The focus of this study is to achieve sub-volt Vpp modulation with a high E-O bandwidth, which requires optimization of the quality factor (Q-factor) and the E-O efficiency of the MRM.A higher Q-factor allows for narrower resonant spectra, enabling lower Vpp.However, it also leads to a longer photon lifetime, which imposes a limitation on the modulation bandwidth.Therefore, enhancing the E-O efficiency of the MRM through other mechanisms using more efficient gate material and higher capacitance density becomes crucial.The ITiO-gated MOSCAP Si-MRM in this work achieved a high E-O efficiency of 117 pm/V with a Vπ•L of 0.12 V•cm by narrowing the microring waveguide width to 300 nm, which effectively improved the overlapping factor between the accumulated carriers and the optical mode profile 34 .The utilization of high mobility ITiO reduces the optical waveguide absorption, enabling a moderate Q-factor of 4600 for sub-volt Vpp modulation while still supporting a photon lifetime-limited bandwidth up to 50 GHz.Additionally, the high mobility ITiO, along with optimized doping on the Si microring waveguide and metal electrode patterning, improved the RC bandwidth significantly compared with all previous work 35,36

Device Design
Fig. 1 illustrates the design of the ITiO-gated MOSCAP Si-MRM, including a 3D schematic diagram and a crosssectional view of the active region.The device comprises a 300 nm thick Si rib waveguide with a 100 nm slab thickness.A waveguide width of 300 nm is selected to enhance the E-O efficiency, while a radius of 8 μm is chosen to reduce the bending loss (Supplementary Information II).The Si doping profile of p (1 × 10 17 cm −3 ), p+ (3 × 10 18 cm −3 ), and p++ (1 × 10 20 cm −3 ) are designed to reduce the series resistance without compromising the optical absorption in the Si waveguide.The entire device has a background Si p-doping, and the p+ region covers the top of the ring waveguide and part of the Si slab.The p++ region is placed 600 nm away from the ring waveguide to maintain the Q-factor.Such a doping design allows the passive Si microring resonator to achieve a high Q-factor of 20,000 near the critical coupling condition.The active E-O modulation region, which represents approximately 62.5% of the microring circumference (L = 31.4μm), consists of a 10 nm thick HfO2 insulator layer and a 14 nm ITiO layer on the top.The Ni/Au electrodes traverse the bus waveguide via the top SiO2 waveguide cladding, forming ohmic contacts with the ITiO gate and the Si substrate of the MOSCAP.shifting the resonant wavelength (Δλres).Our previous studies have discussed that phase modulation with moderate index change is majorly determined by the total charge variation, allowing us to simplify the simulation model to a uniform distribution with 1 nm thick accumulation layers, aligning well with experimental results 38,39 .Therefore, Fig. 2(b) also provides a zoomed-in view of the optical mode profile at the HfO2/ITiO interfaces, showcasing examples at 0 V and -1 V biases with a 1 nm thick uniform accumulation layer.Fig. 2(c) shows the simulated transmission spectra under different gate biases.Our simulation assumes a dielectric constant of 12 for HfO2 and carrier mobility of 62 cm 2 /(V⋅s) with a concentration of 1.2×10 20 cm -3 for ITiO, chosen to align with the experimental material properties (Supplementary Information III, IV).Using such parameters, the ITiO-gated MOSCAP Si-MRM achieves a high Q-factor of 5000 at 0V with an E-O efficiency of 125 pm/V in the accumulation mode.The simulation results also demonstrate that the ITiO-gated MOSCAP Si-MRM can achieve a 7.6 dB extinction ratio (ER) with 3 dB insertion loss (IL) using only 0.8 Vpp, highlighting the potential for efficient modulation.Despite the high etching selectivity between SiO2 and Si, some Si waveguide was still inadvertently etched during the process.As a result, the width of the Si microring waveguide was slightly narrower than the designed value, measuring at 290 nm, as depicted in Fig. 3(b).After the entire fabrication process, Fig. 3(c

DC Characterization
The ITiO-gated MOSCAP Si-MRM was designed to operate at O-band.The normalized transmission spectra with various gate voltages are shown in Fig. 4(a).The device was designed near critical coupling, resulting in a deep resonant dip to enable a modulation condition with an ER exceeding 6 dB and an IL of 3 dB.Applying a negative bias to the ITiO gate causes the accumulated carriers in both the Si waveguide and ITiO gate, resulting in Δλres.Simultaneously, such accumulated charges also increase optical absorption and decrease the Q-factor.
The measured Q-factors and Δλres are plotted in Fig. 4(b).The ITiO-gated MOSCAP Si-MRM exhibits a Q-factor of approximately 4600 at 0 V, supporting an optical bandwidth of 50 GHz.For gate biases ranging from 0 V to -1.5 V, the ITiO-gated MOSCAP Si-MRM operates in the depletion mode due to the non-ideal flat-band voltage (VFB), achieving an E-O efficiency of 87 pm/V.Once the negative bias exceeds -1.5 V, the MOSCAP transitions into the accumulation mode, and Δλres becomes more linear, leading to a higher E-O efficiency of 117 pm/V, corresponding to a very low Vπ•L of 0.12 V•cm.Therefore, the ITiO-gated MOSCAP Si-MRM operates in the accumulation mode to achieve a low driving voltage (Vpp).Additionally, it is worth noting that the experimental Qfactor (4600) and E-O efficiency (117 pm/V) obtained were only slightly lower than the simulated values of Qfactor (5000) and E-O efficiency (125 pm/V) with acceptable error margin of 8%.The modulation wavelength (λMOD) was fine-tuned by a tunable laser to ensure an IL of 3 dB at -1.5 V.The optical transmission for different gate biases at λMOD is shown in Fig. 4(c).An ER of 6 dB and an IL of 3 dB can be achieved with a bias voltage of -1.9 V and a voltage swing of 0.8 Vpp (-1.5 V ~ -2.3 V).The observed ER, though slightly lower than the expected value, can be attributed to the slightly lower experimental Q-factor and E-O efficiency.

High-Speed Characterization
The E-O response (S21) of the ITiO-gated MOSCAP Si-MRM was measured under the condition of 3 dB IL at -1.5 V.By varying the frequency of the input sine wave driving signal, the corresponding output RF power was measured by a microwave spectrum analyzer (MSA).Fig. 5(a) shows an example of the output signal on the MSA at 10 GHz.Since the output signals were amplified by a 42 GHz photodetector with a built-in transimpedance amplifier, the output RF power was normalized to the RF power at a low frequency of 500 MHz.
The measured and normalized data were plotted in Fig. 5  For the E-O modulation measurement, the ITiO-gated MOSCAP Si-MRM was biased at the IL of 3 dB at -1.5 V and driven by 0.8 Vpp NRZ pseudorandom binary sequence (PRBS) signals.PRBS9 was used for data rates lower than 10Gb/s, and PRBS15 was employed for higher data rates.Since the capacitance changes with the applied gate bias as indicated in the C-V characteristics (Supplementary Information IV), the capacitance (after eliminating the parasitic capacitance) was found to be 333 fF at -1.9 V, which corresponds to the center of the 0.8 V voltage swing (-1.5 V to -2.3 V).Considering the modulation energy consumption (CV 2 /4), the estimated energy consumption is 53 fJ/bit.Fig. 6(a) presents the obtained optical eye diagrams at different data rates using a digital communication analyzer (DCA).It is evident from the diagrams that the eye remains open even at the data rate of 25 Gb/s.To push for even higher data rates, the S21 data from Fig. 5

Device Optimization
Fig. 5(b) demonstrated that the ITiO-gated MOSCAP Si-MRM achieved an E-O bandwidth of 11 GHz, which is limited by the RC bandwidth since the photon lifetime-limited bandwidth supports up to 50 GHz with a Q-factor of 4600.The device's high overall capacitance of 500 fF (Supplementary Information IV) hinders the bandwidth improvement.Although higher doping concentration of the TCO and Si materials can lower the resistance, it will introduce greater optical absorption loss that can suppress the Q-factor with the price of higher driving voltages.
To maintain the E-O efficiency, it is necessary to reduce the overall capacitance.In the current device, the MOSCAP is formed by covering the top and two sidewalls of the waveguide with ITiO, as well as the 500 nm width of the Si slab.By calculation, the outer sidewall of the ring contributes over 50% of the total modulation, while the top of the waveguide and the slab act more like parasitic capacitance with minimal contribution to E-O modulation (Supplementary Information V).This insight analysis suggests that the total capacitance can be significantly reduced by covering only the outer sidewall of the ring, as illustrated in Fig. 7(a).In parallel, the thickness of HfO2 is reduced from 10 nm to 6 nm, enhancing the capacitance density and improving E-O efficiency.Furthermore, employing a higher mobility TCO, such as hydrogen-doped indium oxide (IHO) 41 , not only improves the Q-factor by reducing the optical loss but also decreases the series resistance.IHO has reported a high mobility of 150 cm 2 /(V⋅s) with a concentration of 1.5 × 10 20 cm -3 .Assuming the active E-O modulation region occupies 70% of the microring, this structure allows the modulator to achieve a Q-factor of 6000 at 0V.When the device is biased at -1.5 V, the Q-factor slightly reduces to 5600 with an E-O efficiency of 148 pm/V, as depicted in Fig. 7(b).Hence it can achieve a 6 dB ER with a 3 dB IL using only 0.5 Vpp.Moreover, with this improved structure and the material properties, the total capacitance can be reduced from 500 fF to 218 fF, and the total series resistance will be 18 Ω, effectively supporting an RC bandwidth up to 40.6 GHz.The simulated E-O bandwidth extends to 52 GHz, as shown in Fig. 7(c).In addition, the energy efficiency can be improved to 13.6 fJ/bit.

Discussion
This work successfully demonstrated the integration between silicon photonics and high-mobility TCO material to create a highly efficient ITiO-gated MOSCAP Si-MRM.The device was co-fabricated by Intel's photonics fab and TCO patterning processes at Oregon State University.It exhibited an exceptional E-O efficiency of 117 pm/V, along with a Vπ•L of 0.12 V•cm.With an E-O bandwidth of 11 GHz, it achieved a 25 Gb/s open eye at a sub-volt Vpp of 0.8 V with an energy efficiency of 53 fJ/bit.With further optimization of the device structure, it has the potential to achieve a 0.5 Vpp while increasing the E-O bandwidth to 52 GHz, enabling data encoding at 100 Gb/s for the next generation of high-speed optical communication with an energy efficiency of 13.6 fJ/bit.In conclusion, the highly efficient ITiO-gated MOSCAP Si-MRM presented in this work has a significant impact on energyefficient optical communication and computation.Its sub-volt driving voltage offers the feasibility of direct CMOS driving without any voltage amplifier, which can potentially reduce the transmitter side power consumption by an order of magnitude.It will also bridge the gap of the driving voltage between neuromorphic computing and photonic modulators, enabling low-energy photonic computing for artificial intelligence.

Fabrication
The passive Si microring resonator was fabricated on a SOI wafer using Intel's photonics fab.The Si microring has a narrow waveguide width of 300 nm and a waveguide height of 300 nm while leaving a 100 nm thick Si slab to ensure good optical mode confinement in the Si waveguide and proper electrical conduction.To create the MOSCAP on the microring, the top SiO2 cladding in the active region of the microring was selectively patterned using regular photolithography, followed by RIE, as shown in Fig. 3(a).Next, a 10 nm HfO2 insulator layer was deposited on the entire SOI substrate by atomic layer deposition (ALD) using tertrakis (eythylmetylamido)-Hf (TEMA) and H2O at 300⁰C.Subsequently, a 14 nm layer ITiO was RF-sputtered onto the HfO2 layer at a high substrate heating temperature of 500°C, which covered the entire wafer with ITiO.The ITiO layer in the active region was patterned using a two-step process.Electron beam lithography (EBL) with RIE was employed to accurately define the desired ITiO pattern within the active region.Subsequently, regular photolithography with wet etching (ITO etchant) was used to remove any residual ITiO.After these two steps, the ITiO layer only covered approximately 62.5% of the microring circumference.Prior to the metal deposition, the HfO2 layer in the Si contact region was patterned using EBL and removed by RIE.The Ni/Au electrical contacts were patterned on the ITiO gate and the Si substrate using EBL, followed by thermal evaporation and lift-off.These contacts were patterned approximately 1.2 μm away from the microring waveguide.Finally, the Ni/Au coplanar ground-signal-ground (GSG) electrode pads were patterned using regular photolithography followed by thermal evaporation and lift-off and were connected to the electrical contacts patterned in the previous step.

Eye Diagrams Testing
Fig. 8(a) illustrates the testing setup utilized for measuring optical eye diagrams.A PRBS electrical signal was generated using a 92 GSa/s AWG (Keysight M8196A), and it was combined with a DC bias through a 50-GHz bias tee (Keysight 11612B), ensuring optimal modulation of the electrical signal.Subsequently, this combined signal was applied to the device via an Infinity 40-GHz high-speed GSG probe.Simultaneously, a tunable laser (TL) (Santec TSL-570) was employed to generate the optical input, and the optical signals were coupled in and out through waveguide grating couplers.The modulated optical signal was then amplified by an O-Band Praseodymium-Doped Fiber Amplifier (PDFA) (Thorlabs PDFA100) before being detected by a 65 GHz optical module (Keysight N1030A) plugged to a DCA (Keysight N1000A).Finally, the DCA enables the acquisition of the optical eye diagram.

E-O Response Testing
The E-O response shown in Fig. 5(b) was characterized using the experimental setup depicted in Fig. 8(b).The single-frequency sine wave generated by the AWG was combined with a DC voltage using the bias tee before being utilized to drive the ITiO-gated MOSCAP Si-MRM.The device was modulated by the input singlefrequency sine wave, resulting in an output-modulated optical signal detected by a 42 GHz photodetector with a built-in transimpedance amplifier (Thorlabs RXM42AF).Subsequently, the detected signal was further analyzed using a 26 GHz MSA (HP8562A).To examine the frequency-dependent behavior of the E-O response, the input frequency of the sine wave was scanned, and the corresponding changes in the output power displayed on the MSA were observed.By systematically measuring the output power at different input frequencies, the S21 response of the ITiO-gated MOSCAP Si-MRM was characterized.

II. Optimizing Radius for ITiO-Gated MOSCAP Si-MRM
The ITiO-gated MOSCAP Si-MRM is designed to achieve a Q-factor ranging from 5000 to 6000 that ensures sufficient optical bandwidth while minimizing the driving voltage.Once the ITiO is deposited on the Si ring waveguide, it introduces optical absorption losses that can decrease the Q-factor.To maintain the Q-factor after ITiO deposition, it is crucial to ensure that the loss from the Si ring waveguide is negligible compared to the optical absorption from ITiO.In other words, the Q-factor of the passive Si microring resonator should be significantly higher than 5000, for instance, around 20000.To determine the appropriate radius for the design,

Fig. 1 :
Fig. 1: 3D schematic diagram of an ITiO-gated MOSCAP Si-MRM.The dashed line box shows the crosssectional view in the active region of the ITiO-gated MOSCAP Si-MRM.

Fig. 2 (
Fig. 2(a) shows the simulated carrier density distribution in the cross-sectional waveguide of the ITiO-gated MOSCAP Si-MRM in the active region.When a negative bias is applied, holes and electrons accumulate at the Si/HfO2 and HfO2/ITiO interfaces, respectively.Accumulated electrons within the ITiO layer is less than 1nm thick, which is significantly thinner than the hole accumulation layer in the Si waveguide due to the different Debye lengths caused by the varying carrier concentration and dielectric constant 37 .Fig. 2(b) presents the optical mode profile of the transverse-electric (TE) mode in the ITiO-gated MOSCAP Si-MRM.Due to the bending ring waveguide, the optical mode profile shifts toward the outer sidewall of the waveguide.Upon a negative bias, the optical mode interacts with the accumulation charges in both ITiO and Si, enabling E-O modulation and blue-

Fig. 2 :
Fig. 2: (a) Simulated carrier distribution in the cross-sectional waveguide of the ITiO-gated MOSCAP Si-MRM at a bias of -2.3 V. Negative bias on ITiO gate results in hole accumulation at the Si/HfO2 interface and electron accumulation at the HfO2/ITiO interface.Note: the color bars representing carrier concentrations for Si and ITiO ) shows a top view of the fabricated ITiO-gated MOSCAP Si-MRM.Additionally, Fig. 3(d) provides a zoomed-in SEM image highlighting the ITiO region, represented by a false purple color.

Fig. 3 :
Fig. 3: (a) SEM image of the passive Si microring resonator fabricated by Intel's photonics fab, showing the etched SiO2 top cladding in the active region after RIE.(b) Top-view SEM image highlighting the narrow Si microring waveguide.(c) Optical image of the fabricated ITiO-gated MOSCAP Si-MRM with high-speed Ni/Au electrodes.(d) SEM image of the fabricated ITiO-gated MOSCAP Si-MRM with false colors.

Fig 4 .
Fig 4. (a) Normalized transmission spectra of the ITiO-gated MOSCAP Si-MRM with different gate biases.(b) Measured Q-factor (blue) and Δλres (orange) as a function of the gate bias.(c) Transmission at λMOD (1317.54nm) with respect to the gate voltage.It biases at -1.9 V with 0.8 Vpp (-1.5 V to -2.3 V) to achieve an ER of 6 dB with an IL of 3 dB.
(b), with the fitting curve represented by an orange dashed line.The E-O response exhibits the peaking effect 40 , enhancing the 3 dB bandwidth to 11 GHz.It provides the potential for supporting the ITiO-gated MOSCAP Si-MRM in achieving non-return-to-zero (NRZ) modulation at data rates exceeding 20 Gb/s.

Fig. 5 :
Fig. 5: (a) Output signal on the MSA at 10 GHz.(b) Normalized E-O response (S21) of the ITiO-gated MOSCAP Si-MRM in the frequency range of 500 MHz to 25 GHz.Note: A tunable laser was fine-tuned to the input wavelength to achieve an IL of 3 dB at -1.5 V.
(b) was utilized as the input into the arbitrary waveform generator (AWG) to pre-emphasize the signals to enhance the quality of received signals at the DCA.Additionally, the ITiO-gated MOSCAP Si-MRM was driven with a higher voltage.Fig. 6(b) shows the optical eye diagrams obtained through this approach, incorporating the pre-emphasis signals and a driving voltage of 1.75 Vpp.Compared to Fig. 6(a), it becomes apparent that the open eye at 25 Gb/s is even clearer, and the eyes are successfully opened up to 35 Gb/s.

Fig. 6 :
Fig. 6: Measured NRZ modulation eye diagrams of the ITiO-gated MOSCAP Si-MRM with different data rates.(a) driving voltage of 0.8 Vpp without any pre-emphasis signal.(b) driving voltage of 1.75 Vpp with the pre-emphasis signal.

Fig. 7 :
Fig. 7: (a) The cross-sectional view in the active region of the MRM with TCO only covering the outer sidewall of the ring.(b) Static simulation of the shifted spectra under -1.5 V and -2.0 V. (c) Simulated E-O response (S21) of the MRM with 52 GHz bandwidth.

Fig. S1 presents
Fig.S1presents the simulated loss of the bent passive Si waveguide at various radii.The geometry and doping profiles of the Si waveguide remain consistent with the design illustrated in Fig.1.Since the waveguide is designed to be 300 nm wide, it exhibits significant bending losses at small radii.As the radius increases, the loss decreases accordingly.It is observed that when the radius exceeds 8 μm, the loss of the passive Si microring becomes sufficiently low to support a Q-factor greater than 20000.Based on the simulation results, the radius of 8 µm is chosen for the ITiO-gated MOSCAP Si-MRM design.It ensures that the passive Si microring resonator maintains a high Q-factor, even after the deposition of ITiO, enabling the desired performance.
. As a result, the ITiO-gated MOSCAP Si-MRM can be driven by 0.8 Vpp with 11 GHz E-O bandwidth, demonstrating a clear eye diagram at 25 Gb/s with energy efficiency of 53 fJ/bit and 35 Gb/s open eyes with a Vpp of 1.75 V after de-embedding the link.Through further optimization of the device structure to eliminate parasitic capacitance and reduce resistance, we expect to achieve even lower driving voltage of 0.5 Vpp, resulting in a low energy consumption of 13.6 fJ/bit with a high E-O bandwidth of 52 GHz.Such a MOSCAP Si-MRM driven by a high mobility TCO gate would exhibit the potential for high-speed E-O modulation with sub-volt driving voltages, thereby paving the way for future advancements in energy-efficient optical communication and computation systems.
This work ~ Didn't mention it in the article.Measured from spectra or calculated based on other parameters in the articles.-Not available in the article