In operando cryo-STEM of pulse-induced charge density wave switching in TaS2

The charge density wave material 1T-TaS2 exhibits a pulse-induced insulator-to-metal transition, which shows promise for next-generation electronics such as memristive memory and neuromorphic hardware. However, the rational design of TaS2 devices is hindered by a poor understanding of the switching mechanism, the pulse-induced phase, and the influence of material defects. Here, we operate a 2-terminal TaS2 device within a scanning transmission electron microscope at cryogenic temperature, and directly visualize the changing charge density wave structure with nanoscale spatial resolution and down to 300 μs temporal resolution. We show that the pulse-induced transition is driven by Joule heating, and that the pulse-induced state corresponds to the nearly commensurate and incommensurate charge density wave phases, depending on the applied voltage amplitude. With our in operando cryogenic electron microscopy experiments, we directly correlate the charge density wave structure with the device resistance, and show that dislocations significantly impact device performance. This work resolves fundamental questions of resistive switching in TaS2 devices, critical for engineering reliable and scalable TaS2 electronics.


Introduction:
1T-TaS2 is a layered, two-dimensional (2D) quantum material which undergoes an insulator-tometal transition induced by voltage pulses (Fig. 1a,b) [1][2][3][4] .The switching is fast, energy efficient, and reversible, making TaS2 attractive for device applications 5,6 .Moreover, the layered structure of TaS2 may enable atomically-thin memristive or neuromorphic devices, providing ultimate scalability inaccessible to 3D crystals 7 .Nevertheless, knowledge of the switching mechanism in TaS2 is limited.Prior works indicate that the electrical switching is associated with the CDW structure (Fig. 1c) [1][2][3][4][8][9][10][11][12] . At lo-temperature (< 200 K), TaS2 exhibits the commensurate (C) CDW phase, which is insulating [12][13][14] .At higher temperature, several metallic CDW phases exist [12][13][14] , as well as non-thermal CDW phases accessible with optical excitation 15,16 .Direct characterization of the CDW structure during device operation is limited.In operando scanning tunneling microscopy studies have visualized the CDW structure before and after switching 11,17 , but scanning probe studies do not possess the time-resolution to capture the switching process, and are strictly surface sensitive.TaS2 switching has also been studied with in operando optical measurements 8 , but such measurements lack nanoscale spatial resolution, and only indirectly probe the CDW phase.Hence, our understanding of the bias-induced phase(s) is still unclear, and more importantly, the switching mechanism remains unknown.Most studies argue that the transition is field-induced (nonthermal), although there are competing proposals for the microscopic mechanism [1][2][3][4][5][6]8 . More ecently, several groups have claimed that Joule heating is partially or wholly responsible for switching based on finite element simulations 9,10 , as well as IR thermal imaging of a bulk crystal under constant bias 18 .A concrete understanding of the switching mechanism is critical for the development of TaS2 electronics. To this end in operando measurements are needed to correlate the CDW structure, flake temperature, and electrical resistance of a nanoscale device.
Here, we operate a 2-terminal TaS2 device within a scanning transmission electron microscope (STEM) at cryogenic temperature.Through time-resolved electron diffraction and 4D-STEM imaging, we quantify the CDW order parameter during electric biasing and, via strain analysis, we measure the local sample temperature.By directly correlating the CDW structure, flake temperature, and device resistance during switching, we unequivocally show that Joule heating drives the switching process, both for steady-state bias and short voltage pulses.Accordingly, the bias-induced phases correspond to thermal CDW states.We also show coupling between the CDW order parameter and the device resistance, and we demonstrate how local microstructural features (dislocations) influence device operation.These findings are crucial for the engineering and optimization of TaS2 devices for beyond-silicon technology.

Results and Discussion:
The studied device is shown in Fig. 1d and 1e with optical and STEM imaging, respectively.A bulk 1T-TaS2 crystal was exfoliated in an Argon glove box onto a SiO2 / Si substrate, and graphite electrodes were placed on the TaS2 flake (channel length = 7 μm).The finished device was transferred to an in situ TEM chip, and placed over a through-hole drilled in an amorphous SiNx membrane.The TEM chip has Pt electrodes for in situ electric biasing, as well as a Pt coil that allows local sample heating and thermometry from ~100 -1000 K 19,20 .We use electron diffraction to characterize the CDW state.The TaS2 CDW follows the Star-of-David distortion, wherein 13 Ta atoms bunch together (Fig. 1b).In the insulating low-temperature C phase, these stars form a long-range lattice commensurate with the atomic structure 13,14 .As shown in Fig. 1c, electron diffraction of the C phase yields sharp 1 st and 2 nd order CDW satellite peaks.The C phase CDW wavevector has an angle of φc = 13.9°relative to the Bragg wavevector a* and a magnitude of kc = 0.2773a*.Above ~200 K, defects in CDW known as discommensurations form and organize into a hexagonal network with a CDW domain size of order ~10 nm 13,14 .This is the metallic nearly commensurate (NC) phase, which suppresses the 1 st order CDW peak intensity, and slightly adjusts the CDW wavevector, with φ ~ 11 -13° and k ~ 0.280a* -0.285a*.Thomson et al showed that the values of φ and k determine the domain size of the NC phase, DNC, according to where a is the atomic lattice parameter, and Δφ and Δk are the differences in φ and k relative to their commensurate values 14 .Hence, DNC provides an appropriate order parameter to differentiate the C and NC phases, with DNC = ∞ for the C phase.Above ~325 K, TaS2 transitions to the incommensurate (IC) phase, with φ ~ 0° and k ~ 0.285a*, and Equation 1 is no longer applicable.
We first study the CDW behavior as a function of temperature.Figure 1f shows the flake resistance upon heating at 0.4 K / s; the C to NC and NC to IC transitions are clearly observed.In total, the resistance drops by a factor of 8. Using a direct detection camera 21 , we collect temperatureresolved selected area electron diffraction data simultaneous with the resistance measurements (Supplementary Video 1).From the diffraction data, we quantify the CDW structure based on the 2 nd order CDW spots (Supplementary Note 1 and Supplementary Figure 1).The CDW angle φ and magnitude k are plotted in Fig. 1f, as well as the calculated DNC.In the low-temperature C phase, DNC ~ 500 nm.The large error bars in the C phase reflect the nature of Equation 1; small errors in φ and k are magnified in the propagated DNC error as Δφ and Δk → 0. Upon entering the NC phase at ~ 200 K, DNC quickly falls to ~12 nm, and then gradually decreases to 8 nm before the flake enters the IC phase.By plotting the derivates dDNC / dT and dR / dT (inset), we see that the structural CDW transition precedes the resistive transition by ~10 K.This finding was only possible given our in operando multimodal experimental approach.As we show later, this result is relevant to device operation.
Next, we study bias-induced CDW switching using triangular voltage ramps with durations of 20 s (Fig. 2a inset), with diffraction patterns collected at a rate of 100 Hz.These slow ramps effectively probe the steady-state CDW response to an applied electric field.Measurements are performed at ~110 K, starting in the C phase.Applying triangular voltage ramps with maximum voltages ranging from 0.1 to 0.7 V yields triangular current vs time curves, perfectly reflecting the input voltage profile and indicating no CDW switching (Fig. 2a).For this voltage range, there are minimal changes in the CDW structure, as seen in the domain size DNC data (Fig. 2b and Supplementary Video 2).In contrast, for voltages above 0.8 V, there is a sudden increase in current, indicating resistive switching.Concurrently, DNC rapidly falls, indicating the C to NC transition, quickly followed by the NC to IC phase transition (Fig. 2b, insets, Supplementary Figure 2, and Supplementary Video 3).As the applied voltage decreases on the second half of the voltage ramp, the flake recovers to the NC phase, and then slowly progresses towards the C phase over the next several minutes.For this device, the steady-state switching threshold is ~ 0.8 V.While the measured I vs V behavior is consistent with data in the literature [1][2][3][4] , this experiment constitutes the first in operando study to directly quantify the CDW order parameter during switching, and to identify the NC and IC phases as the bias-induced states.We now demonstrate that the bias-induced switching is driven by Joule heating.To measure the local flake temperature during bias, we extract the in-plane flake strain ε from the diffraction data (Fig. 2c, Supplementary Note 2).For the sub-threshold voltage pulses of ≤ 0.7 V, the strain versus time profiles rise and fall with the applied voltage ramp, with larger voltages leading to increased strains.For the 0.8 V pulse, there is a sudden increase in strain at the bias-induced CDW transition.Next, we convert the strain data to temperature using the effective thermal coefficient of expansion α for this device (Supplemental Note 2) 22,23 .Figure 2d plots the maximum flake temperature during each voltage ramp based on the strain data shown in Fig. 2c.For the 0.8 V curve, we plot the temperature immediately prior to the CDW transition.The data clearly shows that with biasing at 0.8 V, the flake temperature surpasses 200 K, which is the Tc for the C to NC phase transition (Fig. 1).Red arrows mark Tflake ~ 200 K in Figs.2c and 2d.Thus, our data clearly shows that at the threshold voltage of 0.8 V, Joule heating is sufficient to raise the flake temperature to 200 K and thermally trigger the C to NC transition.Supporting this claim, the temperature versus voltage data is well fit by ΔT ~ P = V 2 / R, where P is the power generated from Joule heating, V is the maximum applied voltage, and R is the flake resistance prior to switching.Joule heating also explains the rapid rise in strain (temperature) after switching at 0.8 V: as the CDW transition begins and the resistance drops, the power generated increases by 1 / R, which further increases the flake temperature and accelerates the transition.This positive feedback loop leads to sudden and complete CDW switching, and, consequently, a spike in the flake temperature and strain.Additionally, there is an inherent lattice expansion at the C to NC transition 22,24 , which contributes to the strain jump at the CDW transition.This effect also results in a remnant positive strain after the voltage ramp is complete.Because the CDW structure does not fully relax to the C phase within the measurement time-frame, the strain remains finite due to the CDW-lattice coupling (Fig. 2c, 0.8 V curve).
To provide an independent confirmation of Joule heating, we plot the membrane temperature during the voltage ramps, as measured with the Pt coil on the TEM chip (Fig. 2e).The membrane temperature shows the same qualitative behavior as the flake strain and temperature measurements (Fig. 2c and 2d), supporting the presence of Joule heating.For the 0.8 V ramp immediately prior to the CDW transition, the membrane temperature is ~130 K. Using a simple thermal transport model, we find that a membrane temperature of 130 K is consistent with a flake temperature of 200 K (Supplementary Note 3).We also highlight that after the CDW transition, the membrane temperature shows a temperature spike of > 100 K, which supports the positive feedback loop between Joule heating and the insulator-to-metal transition.
It follows from the Joule heating hypothesis that the time needed for switching ts should scale inversely with the applied voltage 25,26 .Specifically, a model from Fangohr et al 27 predicts ts ~ sinh 2 (V -2 ) for a nanodevice on a 2D membrane.To evaluate this behavior, we measure the timeresolved resistance during switching using the biasing setup shown in Fig. 3a.We pass square voltage pulses (durations from 3 ms down to 100 μs) through a 1 kΩ resistor in series with the flake, and we plot the voltage drop across the flake divided by the total applied voltage, Vflake / Vtotal.This ratio scales with the flake resistance; hence, a drop in Vflake / Vtotal indicates bias-induced switching (Fig. 3b).There is no switching for a 3 ms 1.4 V pulse, but all pulses > 1.4 V initiate switching, with progressively shorter switching times for larger voltage amplitudes.In operando diffraction measurements show switching from the C to the NC phase (Fig. 3c and Supplementary Video 4).Moreover, the time-resolved diffraction shows that an increase in flake strain (temperature) precedes the CDW transition, as expected from Joule heating (Supplementary Figure 4).The Fig. 3b inset plots ts as a function of Vtotal, and the ts ~ sinh 2 (V -2 ) model provides an excellent fit to the data.This result further confirms the Joule heating-induced switching mechanism.Conversely, for a non-thermal voltage induced mechanism, one would expect rapid (~ps) switching for all voltages above the threshold value 5,6 , in clear contrast with our results.The sinh 2 (V -2 ) fit also suggests that Joule heating can induce switching on the ns timescale, given a sufficiently large voltage pulse.Indeed, many literature reports of pulse-induced switching can reasonably be accounted for via Joule heating [1][2][3][4] .The diffraction data for this pulse is shown in Supplementary Video 4, and further analysis is provided in Supplementary Figure 4.
We next study coupling between the CDW order parameter and the device resistance through a series of short voltage pulses which are relevant for device operation.We apply pulses with Vtotal starting at 2.0 V and increasing by 0.4 V up to 9.6 V, all with a 3 μs pulse duration, performed at 110 K. Figure 4a shows the measured Vflake / Vtotal for a representative set of pulses.Note that the RC time constant for this device is τ ~ 460 ns (likely due to poor impedance matching throughout the in situ TEM set up), which places an upper limit on device operation speed.Partial switching is observed for Vtotal ≥ 3.2 V, and full switching is observed for Vtotal ≥ 5 V (Supplementary Video 5 for Vtotal = 9.6 V).This behavior is consistent with Joule heating and the ts ~ sinh 2 (V -2 ) model, which predicts ts = 1.1 μs for Vtotal = 5.2 V.The pulse-dependent evolution of the CDW structure and device resistance is shown in Fig. 4b.Several interesting trends are present in the data.First, as the pulse amplitude increases, the pulseinduced DNC decreases, as does the device resistance.Thus, higher voltage pulses produce smaller CDW domains (thus a higher density of discommensurations), which in turn reduce the flake resistance.This behavior is captured in Fig. 4c, which plots the DNC and the flake resistance immediately after pulsing.This finding is consistent with Joule heating, with higher voltage pulses producing larger temperature changes.Comparing the DNC vs Vtotal and resistance vs Vtotal curves in Fig. 4c, we see that the structural CDW transition proceeds the electronic resistance transition.This trend is consistent with our earlier finding, that with heating through the C to NC transition, the DNC transition precedes the insulator-to-metal transition (Fig. 1f inset).Secondly, we find that after switching the device recovery is not complete, i.e. the switching is not fully reversible back to the C phase.This is evident in Fig. 4b; both the pre-pulse DNC and the device resistance steadily decrease after successive pulsing.We note that after the full pulsing experiment, the CDW structure and resistance were fully reset via heating to the IC phase and then cooling to 110 K.
The partial irreversibility of pulse-induced switching suggests CDW pinning on local microstructural features.Indeed, there are many TaS2 biasing experiments which suggest increased CDW pinning in thin flakes 3,4,8 , although direct confirmation is lacking.To test this hypothesis, we performed real-space analysis using 4D-STEM imaging.With this method, the electron beam is focused to a nanoscale probe, rastered across the sample surface, and a full diffraction pattern is captured at each spatial coordinate 28 .In turn, the DNC can be mapped in real space with a spatial resolution of ~15 nm.For these measurements we study a separate flake, imaged optically in the Fig. 5a inset.While the flake is a high-quality single crystal, we observe the presence of basal dislocations [29][30][31] , which are revealed with a virtual-STEM image based on Bragg diffraction contrast (see the dark lines in Fig. 5a).We find that all exfoliated TaS2 flakes (and many exfoliated 2D materials in general) exhibit similar dislocation structures.Figure 5b maps DNC as a function of constant applied bias.Initially, the DNC is mostly > 50 nm, indicating a spatially homogenous C phase, and the device is in high resistance state (resistance = 2.11 kΩ).With application of 0.5 V, the CDW remains in the C phase, and the device resistance remains high (1.99 kΩ).At 0.6 V, the device switches; the CDW map shows DNC ≤ 10 nm, and the resistance drops to 464 Ω.Note that this behavior is similar to our results in Fig. 2, albeit with a slightly lower threshold voltage, and the NC phase is more stable (for this flake, 0.8 V causes a transition to the IC phase).After releasing the applied bias, the sample resistance increases to 1.8 kΩ, and the CDW map mostly shows DNC > 50 nm.However, the NC phase is found to locally persist at the basal dislocations, DNC ~ 30 nm adjacent to the line defects.This data suggests that after pulsing, discommensurations of the NC phase are pinned to dislocations, preventing complete recovery to the C phase.This real-space analysis provides a microscopic understanding of CDW pinning in TaS2 devices.

Conclusion:
By operating a 2-terminal TaS2 device within the STEM at cryogenic temperature, we demonstrate that bias-induced switching is driven by Joule heating and a rapid thermal transition from the C to the NC and IC phases.In our device, this mechanism is operative for both steady-state biasing and μs voltage pulses.Our data also indicates that Joule heating can drive switching on the ns timescale.Based on this knowledge, we suggest engineering heat management of TaS2 devices, e.g. the thermal conductivity of the substrate and the electrode geometry, in order to efficiently reach Tc with minimal losses.While most of reports of TaS2 switching are consistent with Joule heating, we note recent claims of picosecond switching, with a switching energy seemingly below the heat needed for Joule heating 25,26 .Hence, it may be that under certain conditions, purely fieldinduced switching is possible.Our finding that dislocations can pin the CDW structure and prevent complete recovery is relevant to the long-term reliability of TaS2 devices under continuous operation.Devices could also be engineered with optimized dislocation structures to help stabilize the NC phase after switching, which could prolong the lifetime of the pulse-induced low-resistance state.Dislocation engineering may also enable faster switching as well as multi-level resistance states.Lastly, our use of in operando biasing and cryogenic cooling, along with novel 4D-STEM imaging of the CDW order parameter, offers a promising route to understand device performance for other quantum materials 32 .

Figure 1 |
Figure 1 | TaS2 structure and temperature dependent CDW behavior.Atomic structure of 1T-TaS2 in cross-section (a) and plan-view (b).In b, the local CDW distortion is shown, which forms a Star-of-David structure.c.Illustration of the C, NC, and IC CDW phases, which exhibit different orderings of the stars.Associated electron diffraction patterns are shown.For the C phase diffraction pattern, the Bragg vector a* is shown, as well as two first order CDW Q vectors (solid line) and one 2 nd order CDW vector (dotted line).The studied device imaged optically (d) and with STEM high angle annular dark field imaging (e).In the center of the STEM image is a throughhole in the SiNx membrane, which allows for electron diffraction measurements.f.Temperature dependence of the TaS2 resistance, CDW angle φ, CDW wavevector magnitude k, and the domain size DNC.The shaded regions represent the standard error.The inset shows the temperature derivatives of the resistance and DNC.For the inset, the x-axis units are temperature (K).The temperature-dependent diffraction data is shown in Supplementary Video 1.

Figure 2 |
Figure 2 | Steady-state biasing and CDW switching.A. Current vs time during triangular voltage ramps with the maximum voltage ranging from 0.1 V to 1.2 V.The maximum voltage is reached at 10 s.Inset: example voltage profile, the x-axis is time (s).The color legend in a applies to b, c, and e as well.B. The measured CDW domain size DNC during the voltage ramps.The insets show diffraction snapshots acquired during the 0.8 V ramp.The full diffraction datasets for 0.7 V and 0.8 V are shown in Supplementary Videos 2 and 3. C. Flake strain during the voltage ramps.D. Maximum flake temperature for voltage ramps from 0.1 to 0.8 V, calculated from the strain shown in c.For the 0.8 V datapoint, we show the temperature immediately prior to the C to NC transition.T0 is 110 K, ε is the strain, α is the effective coefficient of thermal expansion, and R is the flake resistance.E. Measured temperature of the SiNx membrane during voltage ramps.The thermometer consists of a Pt coil encompassing the flake, pictured in the inset.Scale bar is 50 μm.

Figure 3 |
Figure 3 | Time-dependent resistive switching.a.Our biasing setup, where Vsrc is the voltage source used to generate square voltage pulses, and Vtotal and Vflake are measured with an oscilloscope.b.The measured ratio of Vflake / Vtotal for Vtotal ranging from 1.4 up to 3.6 V. We define the switching time ts when Vflake / Vtotal drops below 0.55, as shown with the horizontal dotted line.The inset plots ts versus Vtotal, along with a fit for Joule heating on a 2D membrane provided in ref. 27.c.In operando diffraction snapshots from the 1.4 V pulse.The voltage pulse is applied at a time of 0 ms, although there is an uncertainty of ~0.3 ms in the diffraction pattern timestamps.The diffraction data for this pulse is shown in Supplementary Video 4, and further analysis is provided in Supplementary Figure4.

Figure 4 |
Figure 4 | Pulse induced CDW and resistive switching.a. Vtotal / Vflake during electric pulsing.Twenty consecutive pulses were performed in total, starting at 2.0 V and increasing by 0.4 V up to 9.6 V, with roughly 5 mins recovery time in between pulses.A representative set is shown here.b. Time-resolved CDW domain size DNC and device resistance during pulsing.The scale bar shows 1 second.The measurement time resolutions are 300 μs for the CDW analysis and 12 ms for the device resistance.The diffraction data for the 9.6 V pulse is shown in Supplementary Video 5. c.Comparison of the CDW domain size DNC (black) and the flake resistance (red) immediately after pulsing.

Figure 5 |
Figure 5 | Real-space CDW imaging during bias.a. Virtual STEM image which sums all of the Bragg peak intensities.The dark lines are basal dislocations.The inset is an optical image of this flake.b.Maps of the CDW DNC as a function of applied bias.The insets show cropped diffraction patterns, extracted from local regions of 3 x 3 pixels.For the post-bias dataset, the top diffraction pattern is extracted from a dislocation, and the bottom diffraction pattern is extracted from a nondefective region.