Cryogenic multiplexing using selective area grown nanowires

Bottom-up grown nanomaterials play an integral role in the development of quantum technologies but are often challenging to characterise on large scales. Here, we harness selective area growth of semiconductor nanowires to demonstrate large-scale integrated circuits and characterisation of large numbers of quantum devices. The circuit consisted of 512 quantum devices embedded within multiplexer/demultiplexer pairs, incorporating thousands of interconnected selective area growth nanowires operating under deep cryogenic conditions. Multiplexers enable a range of new strategies in quantum device research and scaling by increasing the device count while limiting the number of connections between room-temperature control electronics and the cryogenic samples. As an example of this potential we perform a statistical characterization of large arrays of identical quantum dots thus establishing the feasibility of applying cross-bar gating strategies for efficient scaling of future selective area growth quantum circuits. More broadly, the ability to systematically characterise large numbers of devices provides new levels of statistical certainty to materials/device development.

Quantum electronics is rapidly maturing towards large scale integrated (LSI) circuits incorporating a multitude of interacting quantum devices.There is therefore an onus on potential quantum materials candidates to exhibit both high-precision reproducibility and scalability potential.
Semiconductor nanowires (NWs) constitute an important platform for quantum electronics, since the electronic confinement intrinsic to the structure simplifies fabrication of complex devices [1][2][3][4] , the flexibility of contact materials enables hybridization with important quantum materials such as superconductors 1,3,[5][6][7][8][9] , and an increased capacity for strain relaxation over bulk materials enables exploration of exotic heterostructures 2,6,8,10 .Conventional NWs grown perpendicular to the substrate have been highly successful for high-performance electronics, simple complementary circuits, and in fundamental mesoscopic physics [1][2][3][4][5][6][7][8][9][10][11] .However, the difficulty in fabricating individual vertical devices, and the insufficient precision and yield of techniques for transferring NWs to the planar geometry compatible with standard semiconductor processing [12][13][14] has thus far inhibited development of LSI NW circuits.A promising alternative is the bottom-up growth of in-plane semiconductor NWs directly on a suitable device substrate using selective area growth 15-18 (SAG).In SAG, the positions and dimensions of NWs are controlled by lithographically defining openings in a dielectric mask, enabling the controlled growth of large-scale networks and NW arrays 16,19,20 .While proof-of-principle single NW devices, e.g., field effect transistors (FETs) 21,22 , Hall crosses 23 , quantum interferometers 20,24 , hybrid superconducting devices 24,25 , and quantum dots 26 have been reported, scalability towards integrated quantum circuits -a central motivation behind the development of SAG and similar bottom-up grown planar nanostructures 27,28 -has not been addressed.
Here we make the first demonstration of LSI circuits based on SAG.Starting from large arrays of thousands of SAG NWs we fabricate multiplexer (MUX) circuits which operate at the deep cryogenic conditions relevant for quantum electronics.Cryogenic multiplexers are key ingredients towards scaling of quantum electronics [29][30][31][32] as the number of addressable devices scales exponentially -rather than linearly -with the number of connecting control lines.This is crucial for reducing heat load from wiring between the cryogenic sample and roomtemperature, and integrated MUX circuits allow highly dense packing of devices utilizing chip-area conventionally required for bonding and routing.Our setup allows us to address and measure 512 individual SAG quantum devices using only 37 control lines.Our architecture also includes de-multiplexers (d-MUX) connected back-to-back with the corresponding MUX, enabling us to unambiguously confirm the functionality of the circuit, to identify faulty operation among the thousands of NWFETs, and self-correct against most failure modes.
Introducing on-chip multiplexing to bottom-up grown nanostructures enables new strategies in quantum electronics research, such as automated searches through large ensembles of devices for rare or exotic phenomena, and systematic, statistically significant exploration of the correlation between device performance and e.g., materials properties or device geometry.To demonstrate the potential of the latter we perform a statistical characterization of device reproducibility within a large array of nominally identical SAG NW quantum dots (QDs).QD arrays are promising candidates for implementing quantum computation and simulation [33][34][35] , and quantifying device-to-device reproducibility -enabled by the MUX circuit -is crucial for the successful development of crossbar gate architectures which constitute an important strategy for limiting gate counts in realistic large scale implementations 36,37 .We find that all QDs of the array can be concurrently tuned to Coulomb Blockade using only three shared crossbar gates further confirming the potential SAG as a scalable platform for quantum devices,

MATERIAL AND ELECTRICAL PROPERTIES
Our circuits are based on [0 1 1] oriented InAs SAG NWs grown using molecular beam epitaxy (MBE) on GaAs (3 1 1)A substrates.See Methods and Supplementary Section S1 for details. Figure 1a shows a crosssectional high-angle annular dark field scanning transmission electron microscope (HAADF STEM) micrograph of a single NW, and Fig. 1b shows a combined schematic and atomic force microscopy (AFM) micrograph of a NW section.The conducting InAs channel sits atop an insulating GaAs substrate and GaAs(Sb) buffer 20 .The NWs are terminated with {1 1 1}A facets as a consequence of the (3 1 1)A substrate symmetry, producing the asymmetric cross-section.Detailed structural analysis is presented in Supplementary Section S2.Figures 1c  and d illustrate the capacity for scale-up inherent to SAG, through an AFM micrograph and dark-field optical microscope micrograph of representative sections of a 512 × 16 array of nominally identical 10 µm-long NWs.The inset to Fig. 1d shows a photograph of a cleaved 5 × 5 mm piece of the growth wafer containing ∼ 18000 SAG NWs, 9216 of which were used for device fabrica-tion; the diffraction from the large arrays is visible.
The Fig. 2a inset shows a scanning electron microscope (SEM) micrograph of a typical device along with a schematic cross section.The device includes 4 SAG NWs connected in parallel by Ti/Au ohmic contacts and a 1 µm gated segment (see Methods for fabrication details).Two gates are seen: one which acts on the exposed InAs NWs (blue), thereby controlling the conductivity, and one which is screened by the metal contact, and thus has no effect on the underlying NW (grey).This gate is, however, important for the MUX operation as discussed below.Figure 2a shows the conductance, G, as a function of gate voltage, V G , measured at a temperature of T = 20 mK for 6 different devices with varying numbers of NWs, M = 1, 4, 16, 32, 64 after subtraction of a constant series resistance R S (see Methods).The devices act as normally-on, n-type FETs with identical threshold voltages and the dashed lines show a common fit to the relation G = KM (V G − V TH ) with fixed parameters K = 0.12 mS/V and V TH = −0.4V. Except for M = 64 where G is somewhat lower than expected, G is proportional to M as expected for equally contributing NWs and the linear scaling with V G is typical for NW FETs.The deviation for M = 64 may be due to a high sensitivity to the estimate of R S when the device resistance is low (Methods).Importantly, Fig. 2a shows that SAG devices manufactured in parallel exhibit consistent G vs V G , with reproducible, M -independent V TH , enabling the use of large-M FETs as building blocks in LSI SAG circuits.

SAG MULTIPLEXERS
We utilize the V TH reproducibility to operate the circuit shown in Fig. 2b.SAG FETs are connected in a hierarchical MUX structure, with each level consisting of devices fabricated on different rows of the SAG NW array in Fig. 1d.Each gate spans the respective row, and the positions of the gated segment alternate such that for each NW FET, one gate (blue) tunes the carrier density of the NWs while the other is screened (grey).Input signals are thus directed through the MUX as illustrated in the schematic in Fig. 2c.With this design, each additional level doubles the number of outputs such that a n level MUX has 2 n outputs and requires 2n gates for operation.
Figure 3a shows an optical micrographs of an 8-level MUX circuit connected back-to-back to a corresponding 8-level d-MUX.The circuit has a footprint of ∼ 0.6 × 1.1 mm and incorporates 8192 individual SAG NWs in the form of 1996 interconnected FETs.Combining the 32 gate lines with two separate source-drain pairs enables individual addressing of any of 512 devices under test (DUT) located in the gap between the MUX/d-MUX units.Where the DUT themselves consist of FETs with a single common gate, 37 control lines thereby enable experiments on 512 devices.In our case, the DUT in Fig. 3a consist of SAG devices with different functionalities and properties.For example, the SEM micrograph in Fig. 3b shows DUT devices #70 -77.Oddnumbered devices #71,73,75,77 are SAG NWFETs with a contact separation of 100 nm and a common top gate.The even-numbered channels consist of continuous metal paths covering the NW.These allow confirmation of the MUX/d-MUX function irrespective of the DUT performance and also provide for reference measurements the MUX and d-MUX series resistance.
Before discussing DUT properties, we analyze the functionality of the MUX/d-MUX circuit.Figure 3c shows the conductance of the circuit for each of the 65536 combinations of the first 256 MUX and d-MUX channels.The measurement was performed with positive voltage on the DUT gates, which were therefore all conducting.Indeed, high conductance is observed along the main diagonal, (α), which corresponds to both MUX and d-MUX addressing the same DUT channel.This confirms that none of the 1996 SAG NWFETs of the MUX/d-MUX pair fail conduct which would lead to regions of no conductance along the diagonal.In the case of negative V G on the DUT level, every second pixel of the diagonal has G = 0 (Supplementary Section S5).In the ideal case, the diagonal would be the only non-zero values of the conductance matrix.However, finite off-diagonal conductivity also appears following a repeating pattern every 4, 64, and 128 channels in Fig. 3c and d (β, γ, δ).Since the FETs are conducting at V G = 0 V, finite current at these combinations of MUX and d-MUX channels corresponds to rows of NW FETs failing to respond to the gates.This was likely due to a break in gate-lines or a failing bond wire which can occur for large, complex circuits.Figure 3e and f schematically illustrates the correlation between the patterns of the matrix and FETs failing to pinch off turn off at various positions in the circuit.For example, a non-responsive gate, on the second d-MUX level from the DUT layer (blue cross in Fig. 3e) would allow transport for (MUX,d-MUX) combinations (2,0), (3,1), (6,4), and (7,5) as indicated by blue in Fig. 3f.Comparing to the measurement in Fig. 3c and Fig. 3d the periodically repeating off-diagonal pattern can be assigned to failures of one of the gates in the MUX levels marked with the corresponding labels in Fig. 3a.The additional feature appearing at d-MUX channel 192 ( * ) results from the combination of faulty FETs at channels 64 and 128 (Supplementary Section S7 and S8 provides a further analysis of the faults of the circuit).
Importantly, the MUX/d-MUX configuration allows for identifying and in most cases self-corrects for mal- functioning elements of the SAG circuit; the double redundancy makes the measurement tolerant towards nonsymmetrical errors, as, e.g., a non-functioning gate on the MUX side will be intrinsically corrected for by the function of the corresponding d-MUX gate.While errors appearing symmetrically in the MUX and d-MUX side of the circuit cannot be corrected for, they can be identified in the conductance matrix and the corresponding DUT can be excluded from experiments/analysis.This is schematically illustrated in Fig. 3e and f: if the MUX/d-MUX FETs fail to pinch-off at the symmetric red/purple positions, addressing levels 0,1,2,3 would also mix signals from levels 4,5,6,7, respectively.Such a situation is readily identified by the symmetric off-diagonal non vanishing elements in the conductance matrix (purple and red in Fig. 3f).We note that FETs failing to pinchoff would pass unnoticed in single-ended MUX layouts 32 where DUT share a common ground.The opposite case, where MUX FETs fail to open would result in periodic non-conductive elements in the diagonal of the matrix.Other examples of MUX/d-MUX circuits are discussed in Supplementary Section S6, showing that even with the amount of failures typical for research-level devices, the self-correcting nature of MUX/d-MUX configuration generally protects against a reduction in the available number of DUT.
As a final comment on MUX operation, we note that bandwidth is a key issue for control electronics.In our experiments, bandwidth was limited by the cryogenic setup, being optimized for low electron temperature, including ∼ 5 kHz low-pass filtering of each line.The MUX operation was uninhibited up to these frequencies (Supplementary Section S9), and we expect much higher bandwidth to be possible similar to other InAs NW electronics op- erating at GHz 11,38,39 .

MULTIPLEXING OF QUANTUM DOT ARRAYS
Eliminating the device-count road block by the MUX/d-MUX circuit enables fundamentally new experimental approaches in quantum electronics.For example, adding statistical significance to the characterization and optimization of device performance and material properties is crucial for efforts towards up-scaling of quantum circuits.As an example, we demonstrate here the use of the circuit for establishing the statistical reproducibility within large ensembles of lithographically identical devices.An array of 50 lithographically identical SAG quantum dot devices were embedded in the DUT layer as shown in Fig. 4a.Potentials (V T , V M , V B ) applied to three shared gates (top, middle, bottom) simultaneously tune the electrostatics of all 50 devices.This crossbar approach is an important strategy for limiting the gate-count in up-scaling of QD arrays, however, successful operation requires significant reproducible between devices 36,37 .Here we benchmark the consistency in the SAG NW QD array by comparing the statistical distributions of QD parameters among devices labeled Dev1-Dev20.First, however, since InAs SAG QDs have thus far not been demonstrated, we establish the characteristics of a single device (Dev1).
Figure 4c shows G vs. V T and V B for fixed V M = 1 V. Pinch-off is at ∼ −150 mV for both V T and V B , and hor-izontal/vertical structures are attributed to resonances below each gate modulating the transmission 5 .With both gates near pinch-off, electrons are ideally confined to a NW segment below the middle gate, thus defining a QD.Indeed, fixing V T and V B at the position of the red dot in Fig. 4c, diamond shaped regions of low conductance associated with Coulomb blockade (CB) are observed in the map of the differential conductance, dI/dV SD , vs. source bias V SD and V M , as shown in Fig. 4b.The V SD -height of the diamonds provides an estimate of the QD addition energy, being the sum of the electrostatic charging energy E C and the single-particle level spacing ∆E.As discussed in Supplementary Section S10 the QDs have ∆E E C and from Fig. 4b we estimate E C ∼ 210 ± 15µeV.The capacitance between the QD and the middle plunger gate is estimated as C G = e/∆V M = 0.4 fF where ∆V M = 0.46 mV is the average value CB peaks spacings in the range of Fig. 4b.This C G value agrees with the result (0.37fF) of simple capacitance estimate based on the gate layout (Supplementary Section S10) and thus support that in this particular gate-configuration, the QD confinement is defined by gates as intended.
To investigate the sensitivity to the tuning, G(V M ) was measured at 11×11 equally spaced (V T , V B ) points, spanning the white square in Fig. 4c.CB peaks were identified at 108 of the 121 gate-tunings and Fig. 4d shows the corresponding map of ∆V M .No systematic trend is observed and the distribution of ∆V M shown in Fig. 4e (top), is symmetric with a mean ∆V M = 464 µV and standard deviation σ = ±27 µV, again consistent with a QD defined between the top and bottom gates.
The choice of range for the cross-bar gate-tunings in Fig. 4b,d was based on the gate characterization specific for Dev1 (Fig. 4c).We now use the MUX circuit to gather statics for the different devices in order to probe the consistency across the array while keeping these same tuning parameters.Values of ∆V M were extracted from G(V M ) traces measured for all devices and all gate-points.All devices were operational and exhibited coulomb blockade and from the resulting 2420 gate-traces, 17924 CB peaks were identified and fitted.Examples of measured data and peak analysis are presented in Supplementary Section S12 and S13.The distributions of ∆V M for all devices are included in Supplementary Section S14 and examples for Dev2-5 are shown in Fig. 4e.A comparison of the distributions and their mean values, ∆V M , among the devices of the array, is shown in Fig. 4f.Except for Dev7, the distribution means fall within one σ of the overall common mean.The spread between devices could be affected by structural variations between nanowires due to SAG processing or to variation in post growth device processing.The spread within each devices could be related to changes in the effective confinement potential with gate tunings and may be different between devices due to random impurity in the vicinity of the devices.
Finally, Fig. 4g shows the joint distribution of all ∆V M and Fig. 4h illustrates the number of devices displaying CB for all measured combinations of V T , V B .In 27 out of the 121 point in cross-bar gate space, all 20 devices simultaneously exhibiting CB.The circles mark the 7 tunings where all devices fulfill the stricter criterion of showing CB and having ∆V M within ±2σ of the joint mean peak spacing.Figure 4f-h constitute a key result of the current study, establishing both a level of device to device reproducibility supporting the potential of SAG for as a scalable platform for quantum electronics.Further, the statistical bench-marking of the QD devices explicitly demonstrates a key example of the new possibilities enabled by the integration of MUX/d-MUX circuits.

CONCLUSIONS AND OUTLOOK
In conclusion, we successfully fabricated and operated cryogenic multiplexers/de-muliplexer circuits based on InAs NWs grown bottom-up by selective area growth.The circuit removes the limitations on device count in conventional cryogenic electronics thus enabling new experimental strategies such as searches through large ensembles of devices for rare or exotic phenomena, establishing the correlation between device performance and materials properties or device geometry, and allows establishing the statistical reproducibility among devices -a prerequisite for further scaling quantum of circuits.This capacity was demonstrated by statistically characterizing an ensemble of SAG quantum dots.In general, the methods developed here enable optimization of quantum materials and devices based on automated acquisition of statistically significant datasets rather than proof-of-principle examples.This direction will be empowered by the ongoing developments of advanced data evaluation 40 and machine learning [41][42][43] for unsupervised and optimized acquisition and tuning of large ensembles of quantum devices with many tuning parameters [44][45][46] .The circuit may be expanded further by replacing the single lines in the current design by a multi-channel bus 47 to enable, e.g., integration of charge sensors, multi-terminal devices, complex gate-architectures, and/or the operating the MUX as a multi-channel DAC 48 .

METHODS
For SAG fabrication and synthesis, a 10 nm SiO 2 mask layer was first deposited on epi-ready GaAs (3 1 1)A substrates by plasma enhanced chemical vapour deposition.0.15 × 10 µm rectangular openings were defined in the oxide along the [0 1 1] direction by e-beam lithography (EBL) and dry etching.The openings were arranged in 512 × 16 arrays with a pitch of 2 µm and 20 µm along the [0 1 1] and [2 3 3], respectively (Fig. 1d).GaAs(Sb)/InAs double layer NWs were selectively grown in the openings where the GaAs(Sb) buffer was introduced to improve the crystal surface for the subsequent InAs transport channel 20 .Synthesis details and struc-tural analysis are provided in Supplementary Sections S1 and S2.For device fabrication, Ti/Au ohmic contacts to the SAG NWs were defined on the growth substrate by standard EBL, metal evaporation, and liftoff.Subsequently, a 15 nm HfO 2 gate dielectric was deposited by atomic layer deposition and top-gates were defined by electron beam lithography, metal evaporation, and liftoff.The QD devices in Fig. 4 have a contact separation of 900 nm, top/middle/bottom cross-bar gates are 300/200/300 nm wide and have a 150 nm spacing.Electrical measurements were carried out in a dilution refrigerator with a base temperature of 20 mK.The conductance, G = I/V SD , where I is the drain current generated by source voltage V SD , was measured as a function of the gate potential, V G , using standard lock-in techniques.The series resistance R S for data presented in Fig. 2 was estimated by fitting the G(V G ) traces with the standard expression 49 where L is the gate length, C is gate capacitance simulated as described in Supplementary Section S3 and S4, and µ FE is the electron mobility.When sweeping V M in the QD measurements, the barrier gates were compensated for a slight capacitive cross coupling (Supplementary Section S10).

S1. DETAILS OF SELECTIVE AREA GROWTH
The details of the selective area growth (SAG) using MBE are provided here.After preparing the substrate for SAG, the sample is introduced to the MBE system.The sample was degassed in the loadlock for 4 hours at 200 • C and then transferred to a second chamber connecting the loadlock to the main chamber.Here, the sample was further degassed at a heating station for 1 hour at 400 • C.After transfer to the MBE growth chamber, the substrate was thermally annealed by increasing the substrate temperature to T sub = 400 • C with a ramp rate of 20 • C/min and then further to T sub = 610 • C with a ramp rate of 10 • C/min under a constant As 4 beam equivalent over-pressure of 1.4 × 10 −5 mbar.RHEED was used to monitor the removal of the native oxide at this temperature for approximately 13 minutes (this time varies slightly from sample to sample), the last minute of which the intensity of the specular RHEED spot does not increase 1 .Subsequently, T sub was reduced to the GaAs(Sb) buffer growth temperature of T sub,GaAs(Sb) = 600 • C. For the buffer growth, a As/Ga ratio of 9 and Sb/Ga ratio of 3 was used.This ensures that the growth rate is dependent on the Ga flux and the growth is performed with a Ga growth rate of 0.1 ML/s for 30 min.The substrate temperature was further reduced to T sub,InAs = 500 • C and stabilized during 10 min for InAs growth.An As/In ratio of 9 and an In growth rate of 0.06 ML/s was used and InAs was grown for 18 min.The choice of a lower substrate temperature and a slower growth rate is employed to minimize temperature assisted Ga diffusion into the InAs channel 2 .The substrate temperature was monitored before, shortly at the beginning and after the growth using a pyrometer and the variation in T sub was maximally 2 • C.This uncertainty is attributed to the variation in temperature read-out caused by radiation from different regions of the substrate.

S2. CRYSTAL STRUCTURE, STRAIN AND COMPOSITION
Figure S1 shows the morphology, strain and crystal structure of the NWs comparable to NWs investigated in this study.A uniform morphology is visible for 4 InAs/GaAs(Sb) NWs oriented along the [0 1 1] direction on a GaAs(3 1 1)A substrate in Fig S1a .The InAs channel exhibits {1 1 1}A facets.It should be noted that the cross-sectional shape is specific to the choice of substrate, in-plane orientation, mask dimensions such as the width and pitch, as well as the growth parameters listed in the previous section.
Figure S1b shows the crystal structure of all 4 NWs, along with the corresponding geometric phase analysis (GPA) of the dilatation and rotation maps.Figure S1b (column 2) shows stacking faults (highlighted as white dashed lines) originating at the GaAs(Sb)/InAs interface and propagating towards the InAs channel.It can be observed the dilatation maps in Fig. S1b (column 3, 4) that the main relaxation occurs through creation of an array of dislocations at the GaAs(Sb)/InAs interface.The rotational maps in Fig. S1b (column 5, 6) show rotation in the crystal planes which comes along as an elastic relaxation mechanism.
Electron Energy Loss Spectroscopy (EELS) of the NWs is used to obtain the elemental composition of the NW.In particular, relative elemental quantification of the In vs Ga ratio in atomic % is shown in Fig. S2a and b respectively.Ga diffusion towards the InAs channel of 8-10 % is observed along the [0 0 1] direction.The diffusion region is highlighted in Fig. S2a between the white dashed lines and is better visible in Fig. S2b.Such preferential diffusion has been reported in GaAs(Sb)/InGaAs/InAs NWs grown on GaAs(0 0 1) substrates 2 .It has been proposed that Ga diffusion arises as a thermally activated strain minimization mechanism during growth of lattice-mismatched InAs and GaAs.It should be noted that an In rich region only exists at the outermost layers of the conduction channel whereas the region in between is diluted with the diffused Ga.This can be circumvented by further reducing the substrate temperature during InAs growth, but is not attempted because it comes at the cost of abating the selectivity of the sample.Figure S3 shows measurements of the conductance vs. gate potential for 5 NW FETs similar to those discussed in Fig. 2 of the main manuscript.Here, only a single NW is measured (M = 1) and 5 consecutive wires of the SAG array were chosen.The channel length was 1 µm and measurements were performed at 100 K.In each case the conductance, G(V G ), was fitted to the model of Ref. 3 where R S , µ, V TH and C are the contact/series resistance, mobility, threshold voltage and gate-NW capacitance respectively.We take C = 5.3fF corresponding to the value extracted from the simulation described in Section S4.The resulting mobility and threshold voltage for each device is stated in the figure.The mobility is between 56 and 140 cm 2 /Vs and V TH is between -0.63 V and -0.93 V consistent with the discussion in the main text of un-gated FETs not being in pinch-off.The values are relatively low for InAs which we attribute to the stacking faults and dislocations associated with the unbuffered growth of InAs on non-lattice matched GaAs 4 .

S4. MODELLING GATE CAPACITANCE OF NWFETS
Gate capacitance for NWFET devices is estimated using the ANSYS ® Electronics Desktop 2021 R2 software.Model NWFET devices are rendered based on measurements from AFM, SEM, and cross-section TEM for lengths 50 nm, 300 nm, 800 nm, 3 µm, and 6 µm of the semiconductor NW segment.An example model is shown in Fig. S4a.The Maxwell3D module of the software models electrostatics using finite element analysis and solves Maxwell's equations in a finite region of space.From the resulting values shown in Fig. S4b 3c for MUX/d-MUX channels #300 to #398 for V G = 1 V and V G = −1 V, respectively.Odd channels addresses NW SAG FETS at the DUT level while even channels are shorted.The shorted channels are unaffected by V G while the FETs have G = 0 2e 2 /h at negative V G .For the conductance matrix in Fig. 3c of the main manuscript, this corresponds to every second pixel along the diagonal showing no conductance as discussed in the main manuscript.

S6. ADDITIONAL MULTIPLEXER CIRCUITS
Other multiplexer circuits were created in the scope of the research presented here.Fig. S6 shows stitched optical microscope micrographs and the correpsonding conductance matrices of three additional MUX/d-MUX circuits fabricated on another chip from the same nanowire growth as the one shown in the main text.All three designs are fully functional and have 16, 64, and 128 outputs respectively.A broken gate line (inset in Fig. S6a) is responsible for the off-diagonal features in the conductance matrices in agreement with simulations described in S7.

S7. CONDUCTANCE MATRIX SIMULATIONS
To verify that the patterns observed in the conductance matrices agree with the assumed gate failures a Monte Carlo simulation was constructed.The simulation takes the number of levels in the multiplexer L as an input and gate failures on both the MUX and d-MUX side can be specified.The simulation assumes that a failing gate is non-functional across the entire level.The algorithm then simulates a random walk from source to drain of 2 L × 10 walkers for all MUX and d-MUX channel combinations.If a walker encounters a FET in depletion it is discarded, if at least one walker reaches the end of the circuit, a value of 1 is assigned to the corresponding matrix element.Figure S7 shows simulated conductance matrices of the circuits shown in Fig. S6 (Fig. S7 a-c) and main text Fig. 3 (Fig. S7 d).For the simulations in Fig. S7a-c it was specified that the gate highlighted in the inset of Fig. S6a is broken and for the simulation in Fig. S7d it was specified that gates are broken in levels 0 and 6 in the MUX side and on level 7 in the d-MUX side.However, it must be noted that identical matrices can result from different combinations of broken gates.

S8. EXAMPLES OF CONDUCTANCE MATRICES OF MULTIPLEXERS CONTAINING MULTIPLE FAULTY FET GATES
In Fig. 3e,f of the main manuscript, the consequences for the conductance matrix of individual FETs or FET rows failing to pinch-off at various locations of the MUX/d-MUX circuit were discussed.When multiple FETs or FET rows fail at the same time, their consequences for the conductance matrix do not just add but are coupled.As an example, the purple arrow in Fig. 3c of the main manuscript, appears for multiplexer channel 0 and demultiplexer 192.Since 192 is not a power of 2, such a feature cannot be related to the failing of a FET row.Rather, 192=128+64 and is a consequence of the combined faults located at row 6 (64 = 2 6 ) and 7 (128 = 2 7 ) (the FETs closest to the DUT layers is nr.0).To illustrate such coupling explicitly, Fig. S8a-e shows the consequences of errors at layer 1 (periodicity 2) and 2 (periodicity 4) and their combination (periodicity 2,4 and 6).Here, the colored crosses on the schematic circuit indicate a FET failing to pinch-off (i.e.always open), and the resulting non-vanishing elements of the conductance matrix are shown below.In these schematics, the DUT layer is considered fully conducting.If faults occur on opposing branches or on opposing sides of the multiplexer circuit, the compound errors result in a more intricate pattern as shown in Fig. S8g-l.

S9. MEASUREMENT BANDWIDTH
All measurements were conducted in a dilution cryostat optimised for low electron temperature by including 5-stage RC and 21-stage pi-filters on each measurement line.The rejection of high-frequency radiation assists in obtaining a low electron temperature but naturally limits the measurable bandwidth to a few kHz.While this prevented us from benchmarking our InAs transistors at frequencies up to ∼ 100 GHz as previously demonstrated, [5][6][7] we show in Fig. S9 that MPX elements consisting of both one and 128 SAG NWs were capable of operating at frequencies up to the cut-off set by the cryostat filtering.To do this, a sinusoidal signal, V ac sin(ωt) was applied to the gate of the selected MPX element, offset with a dc voltage V dc such that the transistor was operating in a linear region of drain current I d vs V dc (Fig. S9a).This ensured high-fidelity transduction (Fig. S9a, inset).Fig. S9b shows the amplitude of the resulting sinusoidal I d component plotted as a function of frequency f = ω/2π, normalised to the amplitude at 100 Hz.Shown also is the frequency response of two cryostat lines shorted on another sample board loaded during the same cooldown.The frequency responses fall along three paths, correlated with the three different break-out boxes and looms that the lines were grouped in.This indicates that the observed 3-8 kHz low-pass cut-off is set by the cryostat filtering and wiring, with the multiplexer operating without degradation until this point.
To demonstrate the multiplexer switching capabilities within these limits, Fig. S9c shows the MPX drain current as a function of time in response to a 1 kHz, 3 V square wave applied to the gate of a single transistor in the MPX, centered around V g = 0 (Fig. S9d).The transistor switches from fully open to fully closed, with the output stable after the filter-defined ∼ 0.1 ms rise time.While this represents the upper limit of operation speed in our current set-up, future experiments are planned to measure the bandwidth of SAG devices without these limitations.

S10. QD CAPACITANCES AND GATE CROSS-COUPLING
Figure S10a shows a zoom of a single NW with the three gates used for tuning QD in the main text and panel b schematically shows the couplings taken into account.The capacitance 0.37 fF from the middle gate to the NW QD was estimated by a simple parallel plate capacitor taking typical values ε Hf O = 18, oxide thickness of 15 nm, nanowire width of 180 nm, and a gate width of 200 nm.As seen in Fig. 4c of the main text there is negligible coupling between the gates V T and V B . Figure S10c shows a typical measurement of the conductance vs. V M and V B illustrating the ratio of couplings between the two gates to the QD formed in the middle segment and resonances attributed to QDs below the barrier gates.The couplings were characterized for an number of devices and the average values were used for compensation when acquiring the bias spectroscopy in Fig. 4b of the main text and for measuring G(V M ) for the QD ensemble: V T/B = V 0 T/B + C T/B,M V M where V T , V B = 140, 40mV set the overall tuning (e.g.red mark in Fig. 4c the main manuscript) and the second term compensates for capacitive couplings C T,M = −0.032and C B,M = −0.022 between the middle and top(bottom) gates.Figure S10d shows a high-resolution bias spectroscopy.An example of a discrete excited state is indicated with ∆E ∼ 0.1E C .This behavior is typical for all the acquired bias spectroscopy, and evolution of the addition energy with magnetic field was also consistent with an excited state spectrum with typical spacings of 10/20% of E C .S11. SOURCE-DRAIN BIAS SPECTROSCOPY ON OTHER QD DEVICES Fig. S11a-s shows the source-drain bias spectra of the remaining 19 devices used for the analysis.All bias spectra were taken sequentially at the V T , V B settings as used in Fig. 4c of the main text over the same V SD and V M range.All devices exhibit Coulomb blockade physics.However, these data were taken before the results of main text Fig. 4h were compiled, and therefore not all devices were in deep Coulomb blockade at this particular gate configuration, which was chosen to optimise the behaviour of Dev1.Manually performing the analysis in main text Fig. 4h required contributions from half of the authors and took many days to complete; combining multiplexing with rapid machine-assisted analysis is the next step in simultaneously optimising device behaviour in quantum dot arrays.

FIG. 1 .
FIG. 1. a Cross-sectional HAADF STEM micrograph of a SAG NW, showing the InAs conducting channel atop the GaAs substrate and GaAs(Sb) MBE-grown buffer.The NW exhibits an asymmetric triangular shape imposed by the (3 1 1) substrate symmetry.The shape is not important for the present study which could equally well have been based on NWs grown on, e.g., (1 1 1) or (1 0 0) substrates with higher symmetry.b Combined schematic/3D atomic force microscope (AFM) micrograph of a 2 µm section of a single NW.c AFM micrograph of two SAG NWs.d Optical dark-field microscope image of a section of an InAs SAG NW array.Each NW is ∼ 150 nm wide and 10 µm long and individual NWs are spaced by 20 × 2 µm.Inset: Photograph of an as-grown sample.The large NW arrays are visible in green due to diffraction of light.

FIG. 2 .
FIG. 2. a Conductance, G, as function of gate voltage VG for NWFETs based on 1, 4, 8, 16, 32, and 64 SAG NWs in parallel.Inset shows an SEM micrograph of a NWFET based on 4 SAG NWs, Ti/Au Ohmic contacts in gold, Ti/Au gate in blue.The gate in dark gray is screened by the underlying ohmic contact as illustrated by the cross-section schematic.b SEM micrograph of NWFETs arranged in a MUX circuit.Gates are screened in alternating elements as indicated by the blue/gray false coloring.c A schematic representation of the circuit in b.

FIG. 3 .
FIG. 3. a Optical microscope image of MUX/d-MUX circuit based on InAs SAG NW arrays.Devices under test (DUT) are labeled α and labels β, γ, δ indicate FET gates failing to deplete and related to corresponding off-diagonal signals in panel c.For the device shown 500 of the 512 lines were connected at the DUT level.The number of DUT was doubled from 2 8 = 256 by using two source/drain pairs.b SEM micrograph of the DUT area indicated in panel a, showing 8 devices connected to the MUX and d-MUX channels.Every second channel is shorted for use as a reference to obtain the series resistance of the adjacent channel.c Conductance matrix of all 65536 combinations of source and drain channels of the first 256 connections of the circuit.The color of each pixel corresponds to the measured conductance of the specific channel combination.The uninterrupted diagonal feature shows that that all of the DUT are addressable and conducting.d Expanded view of the conductance matrix within the blue square in c. e Schematic three-level MUX/d-MUX.The colored crosses mark a FET failing to deplete and panel f shows the corresponding signatures on the conductance matrix.When operated at the diagonal, the circuit is immune to such errors except symmetric pairs such as the red/purple.This case can, however, be identified in the conductance matrix as regions with symmetric off-diagonal finite conductance, and accounted for in subsequent measurements.
FIG. 4. a SEM micrograph of an array of NW QD devices.Contacts (gold) are spaced by 900 nm, top/middle/bottom cross-bar gates (blue) are 300/200/300 nm wide and have a 150 nm spacing.The gates are shared between 50 devices of which 20 were analysed in detail.Each device is paired with a shorted line for reference.b Source-drain bias spectrum (differential conductance dI/dV vs V sd and VM) of Dev1 showing Coulomb diamonds.When sweeping VM the barrier gates were compensated for a slight capacitive cross coupling (Supplementary Section S10).VT and VB starting values correspond to the red point in c. c Conductance G vs VT and VB for Dev1.d Map showing ∆VM of Dev1 for various VT and VB combinations within the white square in c.Crossed points have no identifiable Coulomb peaks.e Histograms of ∆VM for Dev1-Dev4 and Dev20 in the same VT and VB range.f Distribution of ∆VM for Dev1-Dev20.The red dots indicate ∆VM of each device and red dashed line shows ∆VM across all devices.g Histogram showing overall distribution of ∆VM for all devices.Red dashed line indicate the average value and corresponds to the line in f. h Number of devices with observable Coulomb peaks at each combination of VT and VB.White circles show points where all 20 devices have ∆VM within 2σ of the common average.
FIG. S1. a A cross-sectional view of 4 InAs/GaAs(Sb) NWs roughly from the middle of an array of 50 NWs oriented along the [0 1 1] direction on a GaAs(3 1 1)A substrate.b (column 1) High-angle annular dark field scanning tunneling micrographs (HAADF-STEM) show the GaAs(Sb) and InAs regions of the NWs.The morphology of all 4 NWs is uniform and the InAs channel exhibits {1 1 1}A facets.b (column 2) Stacking faults originating at the GaAs(Sb)/InAs interface are highlighted with white dashed lines.b (column 3, 4) Dilatation maps of all NWs show an array of dislocations at the GaAs(Sb)/InAs interface, and arrows point to stacking faults.b (column 5, 6) The rotational maps indicate rotation of the crystal planes between the GaAs(Sb) buffer and the InAs channel.Scale bars correspond to 20 nm in all dilatation and rotation maps.
FIG. S4. a 3D model of a NWFET device with a 3 µm long InAs channel rendered in ANSYS software based on AFM, SEM, and TEM measurements.Ti/Au contacts in yellow, Ti/Au topgate in blue b Capacitance values calculated by the model for different InAs channel lengths and linear fit to the results.
FIG. S5. a (b) Conductance of the MUX/d-MUX circuit when both MUX and d-MUX addresses the same channels #300 to #398 with VG = +1 V (VG = −1 V).Odd channels addresses NW FETS at the DUT level while even channels are shorted.
FIG. S6. a-c stitched optical microscope micrographs of three MUX/d-MUX circuits with 16, 64, and 128 outputs respectively.Red arrows indicate the level responsible for the off diagonal features in d-f.d-f the corresponding conductance matrices.
FIG. S7. a-c Simulated conductance matrices for the circuits shown in Fig. S6.The gate identified in the inset in Fig. S6 is assumed to be broken.d Simulated conductance matrix for the circuit in main text Fig. 3. Gate failures chosen to match the observed matrix pattern.
FIG. S8.Examples of conductance matrices for a 16x16 multiplexer/demultiplexer circuit containing FET rows failing to pinch-off at various locations in the circuit.The examples illustrates the non-obvious consequences of multiple faults combined (panels e,f and k,l).
FIG. S9.(a) Drain current I d at fixed dc source-drain voltage V sd = 0.1 V in response to gate voltage Vg with no ac component.Inset: Id modulation vs time (black) in response to Vg = −0.7 + 0.04sin(20πt) V (red), i.e., an ac voltage at 10 Hz with amplitude Vac = 0.04 V, offset by V dc = −0.7 V to span the red section of the trace in the main panel.(b) Amplitude of the ac-component of I d normalised to the amplitude at 100 Hz as a function of the frequency for two shorted cryostat lines (black), two transistors with 128 SAG NWs (red), and five transistors consisting of a single SAG NW (blue).The cut-off frequency is set by the cryostat wiring.(c) Id response of a single SAG NW to a (d) 3 V, 1 kHz square wave applied to the gate.
FIG. S10. a SEM of a single QD device of the array.b Illustratino of the gate cross-couplings.c Measurement device conductance vs. VM and VB.The fine structure which is nearly independent of VV corresponds to the CB peaks of the QD in the middle segment, while vertical structures corresponds to resonances below the barrier gate.The slopes yields the ratio of gate-couplings as indicated.d Typical bias spectrum with indication of excited state.
FIG. S11.a-s Source-drain bias spectroscopy of other devices used for the QD analysis in main text.t Mean CB peak spacing VM, mean charging energy EC, and mean leverarm α extracted for each device with at least one full well-defined Coulomb diamond in the measurements in a-s.
FigureS12ashows examples of G(V M) normalized 0 to 1 for all devices with V T = −50 mV, V B = −50 mV to −200 mV, equivalent to the rightmost column of main text Fig.4h.The data and fit for Dev1 with V T = −50 mV, V B = −50 mV is shown in Fig.S12b.