Laterally gated ferroelectric field effect transistor (LG-FeFET) using α-In2Se3 for stacked in-memory computing array

In-memory computing is an attractive alternative for handling data-intensive tasks as it employs parallel processing without the need for data transfer. Nevertheless, it necessitates a high-density memory array to effectively manage large data volumes. Here, we present a stacked ferroelectric memory array comprised of laterally gated ferroelectric field-effect transistors (LG-FeFETs). The interlocking effect of the α-In2Se3 is utilized to regulate the channel conductance. Our study examined the distinctive characteristics of the LG-FeFET, such as a notably wide memory window, effective ferroelectric switching, long retention time (over 3 × 104 seconds), and high endurance (over 105 cycles). This device is also well-suited for implementing vertically stacked structures because decreasing its height can help mitigate the challenges associated with the integration process. We devised a 3D stacked structure using the LG-FeFET and verified its feasibility by performing multiply-accumulate (MAC) operations in a two-tier stacked memory configuration.

1.It is not very convincing regarding the need of stack height reduction and the use of vdW materials.The reviewer agrees that is a critical issue for nowadays 3D memory, for example vertical NAND.However, what the authors propose in this work is a sequential 3D process, as shown in Fig. 5.With layer by layer processing, it is less obvious why the stack height with a vertical metal electrode could be a serious issue.Besides, this work is far from the vdW vision that has a stack height of 100s of nm.The authors are challenged to provide a better argument for lateral FeFET given that the lateral FeFET will likely have a larger footprint.
2. The comparison between the lateral and vertical gate is not very convincing.The reason why a much less window is observed in vertical gate than the lateral gate is unclear.The authors have spent much efforts explaining that the lateral electric field is much efficient in switching the polarization.But how that is translated to a larger window?What (the design parameters of the device) controls the lateral FeFET memory window?The authors mentioned in Fig. 3e, the gate voltage is converted to electric field.How that conversion is done?For the vertical FeFET, the insertion of SiO2 layer does not necessary reduce the memory window, which could actually increase the window as the required switching voltage increases.Fig. 3g and h are very handwaving, without much physical ground.
3. How reproducible are the reported characteristics of the device?The authors are required to show the multi cycle sweep on multiple devices.4. For the retention measurement, it is unclear why there is no direct transistor state retention measurement, but rather the PFM.The authors need to show the transistor measurement results.
5. A big issue with this work is the lack of experimental details regarding the electrical measurements.Are all the measurements done in DC?What is the switching time of the device?How about the gate leakage current?What are the write pulses for the synaptic demonstration and endurance measurement?6.How to make sense of the Fig. 5d is unclear.Whether a linear result is obtained for MAC is unclear.The middle panel for Fig. 5d should be W1F.
7. The authors need to discuss about the scalability of the lateral FeFET.
Reviewer #3 (Remarks to the Author): This paper investigates the laterally gated FeFET using alpha-In2Se3 as the ferroelectric, the interlocking of IP and OOP, the memory characteristics of the device and finally its application for inmemory computing.The work is original, interesting, scientifically sound and I recommend if for publication.Here are my comments: 1) Could you briefly elaborate on the size effect of the interlocking effect, i.e. what happens when the vertical and lateral size of the ferroelectric (FE) layer change?E.g. one would expect that the effect of the lateral gate is stronger for thinner and laterally shorter FE layers.
2) If this is the case, does this pose a limitation for the future device size and architectures?Because, it is well known that the thicker the FE layer, the larger the memory window (e.g.check [R1] on this).However, if there is a maximum thickness above which the lateral gate cannot switch the polarization and/or the interlocking is not efficient, this might be a problem.
3) On the other hand, the FE layer is relatively thick (60-70nm) as compared to the sizes of highly scaled memory devices in the semiconductor industry.Can this be further scaled down?What is the prospect?4) What are the main ferroelectric properties of the FE layer (e.g.coercive field, polarization etc)?Could you please provide this in the main text?5) Fig. 4(i) shows the cycling endurance.What amplitude/pulse duration was applied?Please provide in the main text.In general, how does the device behave under pulsed operation?What is the switching time?
6) The memory window, larger than 9V, as well as the retention and the endurance of this device are remarkable.However, it would be quite useful for the ferroelectrics/memory community to have a comparison with state-of-the art FeFETs, which are currently mainly made of Hafnium-(Zirconium)-Oxide. I suggest to provide a brief comparison in the main text, e.g., in terms of the main device and material properties summarized in [R1].In the main article: "…The aforementioned LG-FET process was repeated to fabricate the second-tier device.To achieve consistency between the first and second tiers, we employed a process of selecting exfoliated flakes based on their color classification.Furthermore, we confirmed the thickness of these flakes using AFM measurements.This approach ensured uniformity in our samples." Comment 2: The authors utilized the interlocking property of α-In2Se3 to design the LG-FeFET, but it's possible that the orientation of the flake was randomly transferred, resulting in a random in-plane directional orientation of the gate.Could the authors provide experimental or theoretical information regarding the dependence on the orientation of α-In2Se3?
Author response 2: Thank you for your valuable comments.To investigate the impact of the in-plane directional orientation of α-In2Se3, we utilized a multiple lateral gated FeFET device, as depicted below.While the orientation of each gate with respect to the channel may be random, the gates adequately encompass a broad range of directions surrounding the channel.The Id-Vg transfer curves displayed below exhibit the presence of an interlocking effect across all gates, with the device characteristics showing minimal dependence on the gate orientation.We have included the relevant information in Supplementary Figure S6 and the main article.
"Supplementary Figure S6 a) Optical microscopy image of the device which has eight gates around the channel region.b) Id-Vg transfer curves for the gates, which are swept from −5 V to 10 V.All curves show counterclockwise hysteresis and hardly depends on the direction of the gates.c) Memory windows for the various gate directions.The memory windows are extracted at the 1nA drain current." In the main article: "…the interlocked polarization in the LG-FeFET.In this device, the interlocking effect shows minimal dependence on the orientation of the flake.Specifically, the relationship between the flake orientation and the memory window can be observed in Supplementary Fig. S6." Comment 3: The authors demonstrated in Figure 3e that the in-plane directional electric field is more effective than the out-of-plane directional electric field, likely due to the longer distance between the gate electrode and the channel.If the length of the ferroelectric layer between the channel and the gate electrode is varied, it may impact the memory window.Can the authors provide information on how the length between the channel and the gate electrode affects the memory window?
Author response 3: We appreciate your insightful feedback.We conducted an investigation on the memory window, exploring various distances between the channel area and the gate electrode.Our results indicate that with increasing distance, the memory window diminishes due to a decrease in the applied e-field across the ferroelectric layer.It is worth noting that despite the distance (30 μm) being considerably greater than the thickness of the ferroelectric layer (60~70 nm), the memory window achieved through the lateral gate remains larger compared to that obtained through the vertical gate.The relevant details have been included in Supplementary Fig. S8 and  In the main article: "…the difference in memory windows between the two cases became even more pronounced.We also observed that as the thickness of the ferroelectric material and the distance between the channel and the gate electrode increased, the memory window decreased.Interestingly, even at a distance of 30 μm, the memory window obtained through the lateral gate remained superior to that achieved through the vertical gate.Supplementary Fig. S8 provides relevant data on the impact of the ferroelectric layer's thickness and length on memory windows." Comment 4: In Figure 4d, the authors showed that the lateral gate had a larger dynamic range than the vertical gate when using incremental step pulses.It would be beneficial if the authors provided a detailed description of the measuring method in the Methods section or another appropriate section.

Author response 4:
We conducted an optimization of the incremental step pulse program/erase (ISPP/ISPE) for both the vertical and lateral gates.For ISPP, the condition was set to start at 2.3 V and stop at 4.0 V, with an increment of 13 mV.Similarly, for ISPE, the condition was set to start at -3 V and stop at -4 V, with an increment of 8 mV.The pulse rates for both operations were maintained at 1 kHz.After each program/erase pulse, the states were verified at a gate voltage of 0.7 V. We have included these details in the main article.
In the main article: "…both vertical and lateral gates.The incremental step pulse program/erase (ISPP/ISPE) conditions were individually optimized for both the vertical and lateral gates.For ISPP, the condition was set to start at 2.3 V and stop at 4.0 V, with an increment of 13 mV.Similarly, for ISPE, the condition was set to start at -3 V and stop at -4 V, with an increment of 8 mV.The pulse rates for both operations were maintained at 1 kHz.After each program/erase pulse, the states were verified at a gate voltage of 0.7 V. We have included these details in the main article." In the main article: "Fortunately, the 3D structure employing the LG-FeFET can alleviate the level of difficulty by relocating the gate electrode regardless of whether they are stacked in a sequential or alternative manner, which reduces the overall height." Comment 2: The comparison between the lateral and vertical gate is not very convincing.The reason why a much less window is observed in vertical gate than the lateral gate is unclear.The authors have spent much efforts explaining that the lateral electric field is much efficient in switching the polarization.But how that is translated to a larger window?What (the design parameters of the device) controls the lateral FeFET memory window?The authors mentioned in Fig. 3e, the gate voltage is converted to electric field.How that conversion is done?For the vertical FeFET, the insertion of SiO2 layer does not necessary reduce the memory window, which could actually increase the window as the required switching voltage increases.Fig. 3g and h are very handwaving, without much physical ground.

Author response 2:
We appreciate your feedback.The rotational capacity of dipoles in the direction of the in-plane (IP) electric field is better, as the energy required to induce electric polarization rotation is lower compared to the out-of-plane (OOP) electric field [R1].The more the dipole rotates, the greater the overall remnant polarization, thereby creating a wider memory window when subjected to the in-plane electric field.
The ferroelectric memory window is influenced not only by material parameters like remnant polarization (Pr) and coercive voltage (Vc), but also by structural parameters such as interlayer dielectric thickness, gate electrode position, interlayer thickness, and ferroelectric material thickness.Our investigation focused on the impact of ferroelectric material thickness and gate electrode position.We observed that as the ferroelectric material thickness increases and the distance between the channel and the gate electrode decreases, the memory window tends to widen.These values can be optimized by carefully designing the parameters.We have included this relevant information in Supplementary Figs.S7/S8 and the main article.
In the main article: "…the difference in memory windows between the two cases became even more pronounced.We observed that as the ferroelectric material thickness increases and the distance between the channel and the gate electrode decreases, the memory window tends to widen.Even at a distance of 30 μm, the memory window obtained through the lateral gate remained superior to that achieved through the vertical gate.We have included the relevant information in Supplementary Figs.S7 and S8." "Supplementary Figure S7 a The electric field across the ferroelectric layer was calculated by dividing the voltage dropped in each layer by their thickness (for the vertical gate) or length (for the lateral gate).We have added the relevant information to the main article.
In the main article: "…without structural effects.The electric field across the ferroelectric layer was calculated by dividing the voltage dropped in each layer by their thickness (for the vertical gate) or length (for the lateral gate)." In this study, it was verified that the presence of an interlayer (SiO2) in the LG-FeFET device leads to a broader memory window compared to the configuration without an interlayer, as depicted in Fig. S10.While the reviewer mentioned that the interlayer (SiO2) would increase gate voltage, it actually serves the purpose of preventing carrier injection from the metal gate, thereby preserving the remnant polarization.In the case of a directly contacted vertical gate, the injected screen charges into the ferroelectric layer compensate for the polarization charges by inducing a depolarization field.This is because α-In2Se3 is a semiconducting ferroelectric material with a bandgap of 1.3 eV.
The energy diagrams presented in Figs.3g and 3h are conceptual representations based on both the Landau-Devonshire theory and first-principles DFT calculations [R1,R2].We have revised the caption of Fig. 3.
In the caption of Fig. 3: "… The energy diagrams based on the Landau-Devonshire theory and first-principle density functional theory calculation, with respect to (g) the OOP and (h) the IP directional electric fields 34,60 ." Comment 3: How reproducible are the reported characteristics of the device?The authors are required to show the multi cycle sweep on multiple devices.
Author response 3: The reproducibility was confirmed using a total of eight distinct LG-FeFET devices.Across all devices, a consistent counterclockwise hysteresis was observed in the Id-Vg transfer characteristic curves throughout 100 double-sweep cycles.However, slight variations in the characteristic curves were present due to fabrication process discrepancies and variations in the flakes.We have included additional details regarding this information in Supplementary Fig. S3 and the main article.
"Supplementary Figure S3 a In the main article: "… the applied in-plane directional electric field successfully reverses the directions of polarization in α-In2Se3 layers.The reproducibility of the ferroelectric operation was confirmed using a total of eight distinct LG-FeFET devices.Across all devices, a consistent counterclockwise hysteresis was observed in the Id-Vg transfer characteristic curves throughout 100 double-sweep cycles (Supplementary Fig. S3)." Comment 4: For the retention measurement, it is unclear why there is no direct transistor state retention measurement, but rather the PFM.The authors need to show the transistor measurement results.
Author response 4: We appreciate your valuable feedback.To observe the behavior of out-ofplane (OOP) and in-plane (IP) polarizations, we utilized PFM measurements.This approach was necessary because the inter-coupling effect cannot be measured in an integrated transistor.The retention of an LG-FeFET device, as measured below, exhibits a shorter retention time compared to that of individual flakes predicted through PFM analysis.Several factors, including measuring conditions, neighboring layers, and defects, can account for this difference.
To enhance retention, it is crucial to carefully optimize the thickness of the ferroelectric and dielectric layers, as well as the program/erase/read pulses.However, since our primary focus in this paper was to propose the concept of the LG-FeFET, we did not extensively explore optimization studies.We have included this information in the main article.
"Supplementary Figure S11 Retention characteristics of an LG-FeFET device." In the main article: "… The OOP and IP polarization were simultaneously monitored over time to explore the intercoupling effect on the retention characteristic.The retention characteristic was evaluated using PFM, as direct measurement of the inter-coupling effect in an integrated transistor is difficult, where the inner square …" "… between polarizations.The LG-FeFET, as shown in Supplementary Fig. S11, is expected to exhibit a shorter retention time compared to that predicted on individual flakes through PFM analysis.Several factors, including measuring conditions, neighboring layers, and defects, can account for this difference.The LG-FeFET device's endurance …" Comment 5: A big issue with this work is the lack of experimental details regarding the electrical measurements.Are all the measurements done in DC?What is the switching time of the device?How about the gate leakage current?What are the write pulses for the synaptic demonstration and endurance measurement?
Author response 5: We apologize for any confusion caused.All electrical measurements were conducted while applying pulse voltage.We performed separate optimization of the incremental step pulse program/erase (ISPP/ISPE) conditions for the vertical and lateral gates.For the ISPP condition, we set the start voltage at 2.3 V and the stop voltage at 4.0 V, with an increment of 13 mV.The ISPE condition, on the other hand, had a start voltage of -3.0 V and a stop voltage of -4.0 V, with an increment of 8 mV.Both pulse rates were maintained at 1 kHz.The states were verified at a gate voltage of 0.7 V after each program/erase pulse.
In the main article: "… both vertical and lateral gates.The incremental step pulse program/erase (ISPP/ISPE) conditions were separately optimized for the vertical and lateral gates.For the ISPP condition, we set the start voltage at 2.3 V and the stop voltage at 4.0 V, with an increment of 13 mV.The ISPE condition, on the other hand, had a start voltage of -3.0 V and a stop voltage of -4.0 V, with an increment of 8 mV.Both pulse rates were maintained at 1 kHz.The states were verified at a gate voltage of 0.7 V after each program/erase pulse." During the endurance test, the program and erase pulses were applied with amplitudes of 4 V and -7 V, respectively.After each pulse, the programmed/erased states were verified under a read voltage of -0.7 V.The pulse rate for the endurance test was set at 0.1 kHz.We have included this additional information in the main article.
In the main article: "…ferroelectric material fatigue.During the endurance test, the program and erase pulses were applied with amplitudes of 4 V and -7 V, respectively.After each pulse, the programmed/erased states were verified under a read voltage of -0.7 V.The pulse rate for the endurance test was set at 0.1 kHz."Due to limitations in our measurement equipment, our investigation of high-frequency ferroelectric switching was constrained.However, the ferroelectric switching time of the α-In2Se3 ferroelectric device has been previously reported in reference [R3].According to the reference, the polarization of α-In2Se3 is known to be switched in as low as 40 ns.We have included this information in the main article.
In the main article: "…at room temperature in the ultrathin scale 34-38 .Previous studies have demonstrated the presence of ferroelectricity in a single layer (approximately 1.3 nm) of α-In2Se3 and the intercoupling effect in tri-layers (approximately 3 nm) 39, 40 .An α-In2Se3 FeFET has shown a remarkably fast ferroelectric switching time as low as 40 ns 41 ." Finally, as illustrated below, the gate leakage was negligible due to the insertion of the h-BN layer between the channel and the α-In2Se3 layers.

Reviewer #3 (Remarks to the Author):
This paper investigates the laterally gated FeFET using alpha-In2Se3 as the ferroelectric, the interlocking of IP and OOP, the memory characteristics of the device and finally its application for in-memory computing.The work is original, interesting, scientifically sound and I recommend if for publication.Here are my comments: Author response: Thank you for reviewing our paper.We appreciate your insightful comments and revised the manuscript accordingly.
Please find below our responses (in blue) to each of your specific comments (in black).Revisions to the original article are indicated in red.
Comment 1: Could you briefly elaborate on the size effect of the interlocking effect, i.e. what happens when the vertical and lateral size of the ferroelectric (FE) layer change?E.g. one would expect that the effect of the lateral gate is stronger for thinner and laterally shorter FE layers.
Author response: Thank you for your feedback.As the thickness increases and the distance between the channel and the gate electrode decreases, the memory window tends to widen.This phenomenon can be attributed to the varying strength of the applied electric field and the depolarization field.Specifically, the depolarization field weakens as the thickness increases, while the applied electric field strengthens as the length becomes shorter.We have included these pertinent findings in Supplementary Figs.In the main article: "…the difference in memory windows between the two cases became even more pronounced.We observed that as the ferroelectric material thickness increases and the distance between the channel and the gate electrode decreases, the memory window tends to widen.Even at a distance of 30 μm, the memory window obtained through the lateral gate remained superior to that achieved through the vertical gate.We have included the relevant information in Supplementary Figs.S7 and S8." Comment 2: If this is the case, does this pose a limitation for the future device size and architectures?Because, it is well known that the thicker the FE layer, the larger the memory window (e.g.check [R1] on this).However, if there is a maximum thickness above which the lateral gate cannot switch the polarization and/or the interlocking is not efficient, this might be a problem.

Author response 2:
We appreciate your insightful remarks.According to the reviewer's feedback, the α-In2Se3 in the LG-FeFET might have an optimum thickness similar to the case of hafnium-based ferroelectric materials [R1,R2].Nonetheless, the ferroelectric switching behavior resulting from the inter-coupling effect of α-In2Se3 has been verified across a broad range, spanning from 2.3 nm (bilayer) to 130 nm (bulk), as evident in previous research [R1-R7] and our own investigation.This is because the spontaneous polarization of α-In2Se3 is triggered by its atomic configuration, not the crystal phase which causes polarization in hafnium-based ferroelectric materials.
In the main article: "…at room temperature in the ultrathin scale 34-38 .Previous studies have demonstrated the presence of ferroelectricity in a single layer (approximately 1.3 nm) of α-In2Se3 and the intercoupling effect in tri-layers (approximately 3 nm) 39,40 .An α-In2Se3 FeFET has shown a remarkably fast ferroelectric switching time as low as 40 ns 41 ." Comment 3: On the other hand, the FE layer is relatively thick (60-70nm) as compared to the sizes of highly scaled memory devices in the semiconductor industry.Can this be further scaled down?What is the prospect?
Author response 3: Scaling down the thickness of the ferroelectric α-In2Se3 layer is indeed viable, as indicated by prior research, where it has been demonstrated that α-In2Se3 displays ferroelectric properties even in a single layer (approximately 1.3 nm) and the intercoupling effect becomes evident in tri-layers (approximately 3 nm) [R3,R7].
Of course, when designing a FeFET device with a thin ferroelectric film, two crucial factors should be taken into account: i) the thickness of the ferroelectric layer and ii) the interface between the ferroelectric layer and the electrode/channel region.This is because such factors can lead to the potential challenges associated with depolarization field.Nonetheless, recent advancements and increased focus on thin-film growth technology for vdW ferroelectric materials would facilitate the application of vdW ferroelectric films toward industrial semiconductor devices.
Comment 4: What are the main ferroelectric properties of the FE layer (e.g.coercive field, polarization etc)?Could you please provide this in the main text?
Author response 4: Obtaining such properties of α-In2Se3 using an MFM capacitor is challenging due to its distinctive semiconducting property (with an energy bandgap of approximately 1.3 eV).Previous research has reported the coercive voltages (Vc) of α-In2Se3 within the range of 1.7 V to 5.5 V through PFM analysis [R4, R5, R8-R11], and our own investigations also revealed a similar value of 1.76 V, as illustrated in supplementary Fig. S3.
As of now, there is no established methodology to extract the remnant polarization charges (Pr) from the LG-FeFET device for α-In2Se3 with semiconducting properties.To accurately determine Pr, it needs to be further divided into in-plane and out-of-plane components.Additionally, it is essential to separate the contribution of carriers in α-In2Se3 from the Pr values for a proper understanding of the polarization behavior.Thus, further comprehensive and indepth studies are required.
We have added the relevant information to the main article.
In the main article: "… The local phase loop and the amplitude are in supplementary Fig. S3.Obtaining ferroelectric properties of α-In2Se3 using an MFM capacitor is challenging due to its distinctive semiconducting properties (with an energy bandgap of approximately 1.3 eV).Here, we revealed a coercive voltage (Vc) of 1.76 V through the PFM analysis.Secondly, …" Comment 5: Fig. 4(i) shows the cycling endurance.What amplitude/pulse duration was applied?Please provide in the main text.In general, how does the device behave under pulsed operation?What is the switching time?
Author response 5: During the endurance test, the amplitudes of the program and erase pulses are 4 V and −7 V, respectively, with a frequency of 0.1 kHz.Following each pulse, the programmed/erased states are confirmed using a read voltage of −0.7 V.
Generally, 0 V is applied to the source/drain, while a program/erase pulse is applied to the gate.Following a program/erase operation, a read operation is typically performed to confirm the states.Our investigation of high-frequency ferroelectric switching was constrained by the capabilities of our measurement equipment.Nonetheless, previous research in [R12] reported the fast-switching of the α-In2Se3 FeFET, where its polarization could be switched within as little as 40 ns.We have included this valuable information in the main article.
In the main article: "…ferroelectric material fatigue.During the endurance test, the program and erase pulses were applied with amplitudes of 4 V and −7 V, respectively.After each pulse, the programmed/erased states were verified under a read voltage of −0.7 V.The pulse rate for the endurance test was set at 0.1 kHz." "…at room temperature in the ultrathin scale 34-38 .Previous studies have demonstrated the presence of ferroelectricity in a single layer (approximately 1.3 nm) of α-In2Se3 and the intercoupling effect in tri-layers (approximately 3 nm) 39,40 .An α-In2Se3 FeFET has shown a remarkably fast ferroelectric switching time as low as 40 ns 41 ." Comment 6: The memory window, larger than 9V, as well as the retention and the endurance of this device are remarkable.However, it would be quite useful for the ferroelectrics/memory community to have a comparison with state-of-the art FeFETs, which are currently mainly made of Hafnium-(Zirconium)-Oxide. I suggest to provide a brief comparison in the main text, e.g., in terms of the main device and material properties summarized in [R1].
Author response 6: Thank you for your comments.Before comparing the properties of the LG-FeFET using α-In2Se3 with hafnium-oxide-based FeFET devices, we note that these properties can be varied by physical dimension and measurement conditions.
We added a brief comparison table between the HZO-based FeFET and LG-FeFET in Supplementary Table 2 as below.Most of all, the LG-FeFET is distinguished from HZO-based FeFET in the direction of the applied electric field.The LG-FeFET exhibits a larger memory window (approximately 10 V) compared to HZO FeFETs (smaller than 5 V).The endurance of LG-FeFET was confirmed over 10 5 cycles which is comparable with HZO FeFETs, but the retention is shorter than that of HZO-based FeFETs.Due to the unique semiconducting properties of α-In2Se3 (Eg ≈ 1.3 eV), the coercive field (Ec) and the remnant polarization (Pr) cannot be directly compared.
In the Supplementary: "Supplementary Table 2. Comparison of the properties between an HZO-based FeFET and α-In2Se3 based LG-FeFET" In the main article: "… the programmed (low conductance) and erased (high conductance) states.We briefly compared the features of LG-FeFET and HZO-based FeFET in Supplementary Table 2.The LG-FeFET exhibits a larger memory window (approximately 10 V) compared to HZO-based FeFETs (< 5 V) 64 .The endurance of LG-FeFET is comparable with HZO FeFETs, but the retention is shorter than that of HZO FeFETs.Due to the unique semiconducting properties of α-In2Se3 (Eg ≈ 1.3 eV), the coercive field (Ec) and the remnant polarization (Pr) cannot be directly compared."
the main article."Supplementary Figure S8 a) Optical microscopy image of the LG-FeFET device which has three gates.b) Id-Vg characteristic curves for the vertical and lateral gates and c) the extracted memory windows.The lateral gates are positioned at distances of 10 μm, 20 μm, and 30 μm away from the channel area, respectively.All curves show counterclockwise hysteresis." ) and b) are the images of LG-FeFET devices.Each set shares the channel (MoS2) and dielectric (h-BN) materials to minimize the variations caused by the TMD flakes.c) and d) represent the Id-Vg transfer curves of set-01 and set-02, respectively.e) illustrates the memory windows for various thicknesses.""Supplementary Figure S8 a) Optical microscopy image of the LG-FeFET device which has three different gate lengths.b) Id-Vg transfer curves of the vertical and lateral gates and c) the memory windows.The lateral gates are positioned at distances of 10μm, 20μm, and 30μm away from the channel area, respectively.All curves show counterclockwise hysteresis." ) Id-Vg transfer curves and b) memory windows for eight different LG-FeFET devices throughout 100 double-sweep cycles." S7 & S8, and the main article."Supplementary Figure S7 a) and b) are the images of LG-FeFET devices.Each set shares the channel (MoS2) and dielectric (h-BN) materials to minimize the variations caused by the TMD flakes.c) and d) represent the Id-Vg transfer curves of set-01 and set-02, respectively.e) illustrates the memory windows for various thicknesses.""Supplementary Figure S8 a) Optical microscopy image of the LG-FeFET device which has three different gate lengths.b) Id-Vg transfer curves of the vertical and lateral gates and c) the memory windows.The lateral gates are positioned at distances of 10 μm, 20 μm, and 30 μm away from the channel area, respectively.All curves show counterclockwise hysteresis."