Simultaneously ultrafast and robust two-dimensional flash memory devices based on phase-engineered edge contacts

As the prevailing non-volatile memory (NVM), flash memory offers mass data storage at high integration density and low cost. However, due to the ‘speed-retention-endurance’ dilemma, their typical speed is limited to ~microseconds to milliseconds for program and erase operations, restricting their application in scenarios with high-speed data throughput. Here, by adopting metallic 1T-LixMoS2 as edge contact, we show that ultrafast (10–100 ns) and robust (endurance>106 cycles, retention>10 years) memory operation can be simultaneously achieved in a two-dimensional van der Waals heterostructure flash memory with 2H-MoS2 as semiconductor channel. We attribute the superior performance to the gate tunable Schottky barrier at the edge contact, which can facilitate hot carrier injection to the semiconductor channel and subsequent tunneling when compared to a conventional top contact with high density of defects at the metal interface. Our results suggest that contact engineering can become a strategy to further improve the performance of 2D flash memory devices and meet the increasing demands of high speed and reliable data storage.


Supplementary Note 7. Speed estimation of an ideal flash memory
Based on the Wentzel-Kramers-Brillouin (WKB) approximation, we calculated the theoretical relationship between operation voltage and speed at different conditions with reference to the method of Ref. 2 The relationship between the operation time and pulse voltage with changing tunneling barrier from 1.0 eV to 3.0 eV are plotted in Supplementary Figure 13a and b, from which we know that the tunneling barrier height dramatically influences the operation speed for flash memory.Larger electric stress also makes it easier to achieve fast operation speed.Based on the calculation and the operation performance of our ultrafast memory cell, the relation between carrier density and pulse width under different operation voltage is simulated in Supplementary Figure 13b, d

Supplementary Note 8. Estimation of gate coupling ratio
The gate coupling ratio describes the capacitance couple between control gate and float gate, and is important to efficient charge tunneling in device.To obtain the reliable GCR of present flash memory cells, we adopted two different approaches based on capacitance estimation or measured subthreshold swing (SS) in transistor via FG or CG, both of which reach similar GCR value~0.9 in our experiment.

Capacitance approach:
Supplementary Figure 14.Estimation of GCR from capacitive coupling area.a, Structure of the memory.b, Illustration of capacitance coupling in the memory, in which  hBN and  SiO2 are the capacitance of MoS2/hBN/FLG and FG/SiO2/p ++ -Si capacitors, respectively.
Using the area of floating gate and transistor channel, GCR can be directly estimated if the thickness of dielectric layer is known.Supplementary Figure 14 illustrates the capacitance coupling in present device configuration.Based on the total capacitance  total from serial connection of SiO2 and hBN dielectric layer: The GCR is written as: Where  hBN and  SiO2 are capacitance of MoS2/hBN/FLG, FG/SiO2/p ++ -Si capacitors, respectively, Q is the charge stored in the series capacitor circuit.Using  =  0 / , equation ( 2) is further transformed into: where   and   are the permittivity of hBN and SiO2, respectively,   and   are the overlap area of MoS2/hBN/FLG, FG/SiO2/p ++ -Si capacitors, respectively,   and   are the thickness of hBN flake and SiO2 layer, respectively.Notably, the float gate is extended by metal contact and has larger area than the transistor channel and FLG, which makes   <<   (see Supplementary Table 1).Thus, our flash memory cells tend to have GCR factors near unity.
Subthreshold swing approach: The SS value in transistor reflects the coupling between transistor channel and gate modulation, and is influenced by the gate capacitance and the present of interface defects.With a commen transistor channel, GCR value can be estimated by comparing the observed SS under FG and CG regulation.
Experimentally, the values of the (SS) were calculated in the thermionic regimes of the transfer curves according to: where  ds is the channel current measured in the thermionic regime,  G is the applied gate bias.
When there is no Fowler-Nordheim tunneling taking place, the voltage applied on the control gate is portionly coupled to the floating gate, so the gate coupling ratio can be estimated from the subthreshold swing in floating-gate transfer curves and control gate transfer curves from Equation ( 5): where  FG and  CG are subthreshold swings in floating-gate transfer curves and control gate transfer curves, respectively,   and  CG are the applied floating gate voltage and control voltage, respectively,  ds is the channel current measured when Vds is fixed at 0.1 V. Supplementary Figure 15 shows the transfer curves of different flash memory devices under regulation of floating gate and control gate.The maximum FG sweeping voltage of each device are chosen at small value to avoid tunneling occurring, and the  FG and  CG are extracted at a consistent current range of each device.
The calculated gate coupling ratios were presented in the Supplementary Table 1.The estimation based on capacitance or subthreshold swing approach yield similar values ~0.9.

2 Supplementary Figure 12 .
set value.A slope ~1 indicate the quality of applied waveform.Gate modulated tunneling current in MoS2/hBN/graphene vdW heterostructure.(a) Optical image and the corresponding structure diagram for gate modulated tunneling current test.Tunneling current shows no dependence on the bias direction to control gate (b), and the corresponding band alignment (c) indicates that charge tunneling is from MoS2 side. b

Figure 11 ,
Figure 11, our result show the completely programing (erasing) could be achieved by a 10 ns (100 ns) pulse with the pulse amplitude of 15 V, which is in line with the experimental.

Figure 15 .
Estimation of GCR from subthreshold swing approach for four different devices.a, b, c, d: PMBG1#, PMBG2#, PMBG5# and MBG1#, respectively.Identical gate modulation and peak SS value is obtained from the transfer curves measured when varying VFG or VCG, indicating high GCR for all devices.