Wafer-scale solution-processed 2D material analog resistive memory array for memory-based computing

Realization of high-density and reliable resistive random access memories based on two-dimensional semiconductors is crucial toward their development in next-generation information storage and neuromorphic computing. Here, wafer-scale integration of solution-processed two-dimensional MoS2 memristor arrays are reported. The MoS2 memristors achieve excellent endurance, long memory retention, low device variations, and high analog on/off ratio with linear conductance update characteristics. The two-dimensional nanosheets appear to enable a unique way to modulate switching characteristics through the inter-flake sulfur vacancies diffusion, which can be controlled by the flake size distribution. Furthermore, the MNIST handwritten digits recognition shows that the MoS2 memristors can operate with a high accuracy of >98.02%, which demonstrates its feasibility for future analog memory applications. Finally, a monolithic three-dimensional memory cube has been demonstrated by stacking the two-dimensional MoS2 layers, paving the way for the implementation of two memristor into high-density neuromorphic computing system.

As for C-AFM measurement, the MoS2 nanosheets were drop cast onto clean Pt-coated Si wafer. Figure S7a shows the set-up for the C-AFM, in which the C-AFM tip coated with Pt was grounded while positive bias was applied to the Pt coating on Si wafer. The current is detected as a function of the applied bias. As shown in Figure Figure   S13e, and the calculated diffusion barrier is 4.35 eV, which is much higher than that in nanoflake of 0.75 eV.
Therefore, we suggest the epitaxial MoS2 single crystal is not suitable for memristor device due to ultrahigh diffusion barrier of VS. Our predictions are consistent with the reported experimental results. 2 The calculated diffusion barrier of 0.75 eV for VS is slightly higher than that our previously predicted value of 0.61 eV in polycrystalline monolayer MoS2. In which, the VS diffusion accompanied with the glide of (4|6) dislocation, and taken place in interlayer polycrystalline monolayer MoS2. 3  an Ohmic conduction behavior with a slope close to 1, which is caused by the formation of conductive filaments. 4 The log I-V plot of HRS in the low voltage region (<0.2 V) obeys the Ohmic conduction behavior and gradually changes to a square dependence (|I|∝|V| 2 ). This behavior is qualitatively interpreted to follow the shallow trapassociated space-charge-limited conduction (SCLC) theory, expressed by I(V)=aV+bV 2 . At low voltage, corresponding to Ohm's law, only a few electrons can be generated due to thermal excitation and get excited to the conduction band from the valance band or the impurity level in this voltage range. When the applied voltage increases, the conduction becomes space-charge-limited and follows a square dependence. Once the conductive filament forms, a transition from HRS to LRS occurs and the log I-V plot follows the ohmic conduction behavior. To select one cell, different WL voltages are used for SET and RESET (Fig. S26b). For example, for SET, a small voltage is applied on WL to turn on the selection transistor, while BL voltage is applied to set the state. For RESET, a large voltage is applied on WL to turn on the selection transistor while compensating the voltage drop on the RRAM cell. Meanwhile, SL voltage is applied to reverse the current to reset the RS state in a typical bipolar RRAM. For the implementation of in-memory matrix multiplication, kernel elements are stored within the RRAMs as conductance levels. Information is stored in the time period of the voltage pulses applied at BL. Since input pulses are applied to all the RRAMs in the array simultaneously, VDD is applied at the WL of all transistors.

Supplementary
Signal outputs are collected at SL (Fig. S26c).

Note II: Details on the CNN simulations
To test the usability of the solution-processed MoS2 array for neural networks, we simulated a 3-layer CNN with 1 convolution layer and 2 fully connected layers for the classification of MNIST handwritten digit database. 5 Details of the layers and the filter sizes is given in the The unique aspects for our CNN implementation, which includes conductance discretization based on variability and our floating-point mapping techniques, effectively combat device variability to reduce the system output error. We have previously implemented similar algorithm for oxide-based RRAM, 6,7 and in this work, we successfully demonstrate system output error reduction with 2D materials in a memory array simulation. The system evaluation is based on variations captured through multi-devices characterizations, rather than single device data ( Supplementary Fig. S22).
We discretize the RRAM conductance curve into a finite number of states determined based on the observed device variability. The kernel elements are mapped onto those discrete states and stored within the RRAMs for processing. We show in our previous works that the conductance discretization based on variability and our mapping techniques effectively combat device variability to reduce the system output error. Also, we employ pulse width modulation to execute computations within the RRAMs to reduce the power and area consumed by the periphery. In our current implementation, we divide the RRAM conductance into 16 discrete states and use a 3-bit input image/ 4-bit kernel resolution to execute the CNN within RRAMs. The high-accuracy computations that we perform here using low resolution reduce system power/area compared to other works. A detailed description of our methodology, along with its performance analysis, has been provided in our previous works. 6,7 In our execution, we modeled the RRAM behavior based on the conductance curves of 20 devices over multiple cycles. We derived the variance/mean of the measured data and used this to run our simulations. We modeled the current variation at each discrete state as a gaussian function about the mean and derived the conductance at random from this function at every iteration. Thus, the simulations performed in our work account for device irregularities such as limited conductance range and variability to provide an accurate estimate of the output errors. The sample conductance curves of 20 RRAMs (cell size 5×5 µm 2 ) used in this work, along with their discretization into 9 states, is provided in the Figure S22. For system analysis, a hysteron-based compact model, developed by Lehtonen et.al., 8 has been calibrated to our MoS2 RRAM in Figure S23.
CNN performance depends on the non-linearity, conductance range, and variability exhibited by the RRAM devices. Figure S22 illustrates that our RRAM devices demonstrate a 2× linear conductance change over 90 reset pulses. Hence, we determined the memory window and the confidence intervals for the conductance spread of devices fabricated with different suspensions using the bootstrap method in R. We documented the results in Figure S24. The figure delineates that the memory window increases progressively with nanosheet size. While the conductance spread does not follow a pattern, it is <10% of the mean for all nanosheet sizes considered. Thus, our CNN simulations, which we performed with a σ/µ of 0.35 on devices fabricated with nanosheet size of 0.48 µm, account for the worst-case scenario. Furthermore, as explained previously, our in-memory compute methodology accounts for device variability issues, thereby preventing accuracy degradation. Hence, the CNN classification accuracy would remain unaltered for different nanosheet sizes.