An application-specific image processing array based on WSe2 transistors with electrically switchable logic functions

With the rapid development of artificial intelligence, parallel image processing is becoming an increasingly important ability of computing hardware. To meet the requirements of various image processing tasks, the basic pixel processing unit contains multiple functional logic gates and a multiplexer, which leads to notable circuit redundancy. The pixel processing unit retains a large optimizing space to solve the area redundancy issues in parallel computing. Here, we demonstrate a pixel processing unit based on a single WSe2 transistor that has multiple logic functions (AND and XNOR) that are electrically switchable. We further integrate these pixel processing units into a low transistor-consumption image processing array, where both image intersection and image comparison tasks can be performed. Owing to the same image processing power, the consumption of transistors in our image processing unit is less than 16% of traditional circuits.


Supplementary Note 1: Preparation of channel films.
WSe2 shows a strong thickness-dependent polarity. This is determined by its band structure and carrier concentration under different thicknesses. It has been shown that two-dimensional (2D) material WSe2 has a better hole transport at about 10 layers 1 . The realization of the two functions of our array depends on the switching between bipolar and N-type of channel WSe2. Therefore, to achieve the function of our array, we must select WSe2 films in this thickness range as our device channel.
However, it is difficult to obtain large-area and flat WSe2 film simply by mechanical stripping. We adopted the method of mechanical stripping and etching thinning to obtain a large-area film. The method shown in Supplementary Figure 1 was adopted to prepare the channel array. Firstly we used PDMS to peel WSe2 onto Si/SiO2 substrate, then observed it under an optical microscope and selected the flat WSe2 material. Following this, we used Ar/CF4 plasma etching of WSe2 to about 6-10 nm thickness, which enables the device to have good bipolar electrical characteristics 1,2 . Finally, the channel array pattern is exposed by electron beam lithography (EBL), then used Ar/CF4 plasma etching again to get the channel array.
In the above process, experiments were also designed to monitor the progress of etching the film to ensure that the film thickness was suitable. We first selected a flat WSe2 film and obtained its initial thickness by atomic force microscope (AFM) scanning. The thickness of the selected film is then measured again after every 10 seconds of etching until 40 nm. After that, due to the thin WSe2 thickness, we measured the thickness every 5 s after etching until the thickness was about 10 nm (12 nm). The Here we show our device fabrication process in detail. The entire array of electrodes requires three exposures and a deposition process. We pre-designed the mask layout for each exposure processing and used the same markers to align the exposure pattern.
The preparation of the array was performed in the following seven steps as shown  Bottom gate electrode deposition. The electrode pattern was exposed for the first time, and Cr/Au stacking of 4/18 nm was deposited by EBE.
 ALD bottom gate dielectric. The bottom-gate dielectric was then deposited by ALD. 30 nm Al2O3 was deposited. Trimethylaluminum (TMA) and water are used as ALD precursors.
 Channel array transfer. The WSe2 channels array is etched in advance according to the electrode pattern, this process will be mentioned in section S2. We used PMMA + PVA to peel the etched material from the substrate and then affixed it to the appropriate position of the electrode under an optical microscope, and then soaked the substrate in deionized water for two hours to remove the PVA.
 S/D electrode deposition. The electrode pattern was exposed for the second time, and Cr/Au stacking of 4/18 nm was deposited by EBE.
 Seed layer deposition. Because there is no suspension bond on the surface of the 2D WSe2, it is difficult to provide the adsorption point to the precursor on the surface of the channel 3, 4 . Therefore, 2 nm Al2O3 deposited by EBE performed as the seed layer.
 ALD top gate dielectric. After the deposition of the seed layer, we deposited 30 nm Al2O3 as the top-gate dielectric by ALD.
 Top gate electrode deposition. The electrode pattern was exposed for the third time, and Cr/Au stacking of 4/18 nm was deposited by EBE. How to use 2D material film on a large scale is a big problem in the application of 2D materials. Because the CVD film has the advantage of large area and good uniformity, it is one of the most reliable methods to construct the circuit by using 2D films grown by CVD. Here, we have also demonstrated experimentally that our process has the potential for large-scale application by using the large area CVD WSe2 film.
The left part of Supplementary Figure 6 is the flow chart of the array preparation.
To facilitate subsequent exposure, we first transferred the CVD WSe2 film to our marked substrate with thermal release tape. Insets a is a photograph of the film under the original substrate, and Inset b to d show the process of patterning to metallization.
A 3×3-pixel processing array is finally successfully prepared by using the process described above, which shows that our process has good compatibility for the film of large-area CVD. As shown in the right inset, the transfer curves under different VDS are also tested. The devices exhibit strong N-type characteristics, which is due to the thin thickness of the CVD WSe2 film. In the end, the CVD WSe2 film was not used for the actual array function test, but the feasibility of large-scale expansion was proved in the process.
Supplementary Figure 6| The preparation process of the TSC array using CVD WSe 2 film. Left part: a, the optical photograph of WSe2 on unmarked sapphire substrate. b-c, transferring and patterning of large-area thin films. d, the final morphology of the TSC array. Right part: the transfer curves of the device under different VDS. The threshold voltage drifts to the right VDS from -5 V to -1 V, which is also in line with the mechanism explanation in our text.

Supplementary Note 4: Controllable switching performance of the devices.
In the course of our experiments, we found that the devices also have other practical properties. In a field-effect transistor, the on-off ratio measures the ability of the gate pressure to control the conduction channel. This value can be adjusted by an applied electric field. We apply an input voltage VCG to the Si substrate as a control gate and then scan the back gate VBG using the same test method in Fig. 2.
The transfer curves under different VCG biases are shown in Supplementary   Figure 7. In the process of scanning, the off-state current of the transfer curve showed two trends. When the VCG is less than -4 V, the off-state current decreases with the increase of the VCG; when the VCG is greater than -4 V, the off-state current increases.
As shown in the figure, the presence of VCG causes the off-state current of the transistor device to vary by several orders of magnitude, which is enough to improve the logic performance of the device. We hypothesize that this regulation is related to the existence of the buried metal electrode. When there is no buried gate electrode, the VCG has uniform control over the whole channel. Due to the existence of the buried metal gate, the control of the channel by VCG is shielded. The electric field introduced by the VCG can only be applied near the source and drain. So we speculate that the reason for this phenomenon is that the introduction of VCG changes the Schottky barrier between the source/drain metal and the channel. We have drawn an IDS-VBG/VCG map where the switching ratio reaches a maximum of over 10 5 when VCG = -4 V. We do not go into depth here because the on/off ratio is sufficient for us to test when the VCG is 0 V.

Supplementary Figure 7| Switching on/off ratio that can be modulated by V CG . The
VCG is applied on Si substrate and under the buried gate as a control gate. The IDS-VBG curves show good bipolarity of the WSe2 channel. We applied different VCG, and the off-state current increased from -4V to 2V, decreased from -10V to -5V. The current colour map was drawn to see the on/off ratio more clearly. The highest on/off ratio can be seen at VCG = -4V. Table 1.

Supplementary Note 5: Computing method of transistor consumption in
In Table 1, we set out the calculation method of transistor consumption of various emerging logic circuits. Here, we first give the gate circuit diagrams of logic NAND, NOR, and XOR-based on silicon NMOS logic as shown in Supplementary Figure 8, and using the number of transistors they need as the transistor consumption baseline of various logic gates (9 for XOR, 3 for NAND, 3 for NOR). We use the following formula to evaluate the complexity of each work in Table 1, (1) where TXOR, TNAND, TNOR indicates the number of transistors required to implement logic XOR, NAND, and NOR, respectively. PG represents the number of planar gates in a single transistor.
For all the reported works based on depletion-load NMOS 5, 6, 7, 8 , the transistor number is 9 for XOR, 3 for NAND, 3 for NOR (the transistor consumption is 1). It's should be noted that some of these works have not adopted the optimal circuits design, the transistor consumptions are larger than the baseline. But once they use the optimal circuits the transistor consumption will decrease to the baseline value.
The reconfigurable logic uses the same circuits to implement different logic functions, which can reduce the transistor consumption of the logic circuit. As shown in the top column of Supplementary Figure 9, one approach is to use an additional gate to control the polarity of the transistor. References 9-10 use the changes in polarity to achieve the reconfiguration of the logic function (4 transistors for NAND&NOR, 5 for XOR) 9,10 . Reference 11 realized a simpler reconfigurable logic gate by redesigning the circuit 11 , logic AND (NAND) and OR (NOR) can be switched with only two transistors (2 transistors for NAND&NOR). In this approach, each device has two gates in the same plane, and the planar gate number of the transistor should be considered in the transistor consumption computing process. Therefore, the transistor consumption is In Fig. 3, we extracted the test data of the first pixel in the array to demonstrate the switchable logic function of the TSC pixel processing array. It can be seen that the logic function of a single device is switched from AND to XNOR as the Op-Instruction voltage changes. In image data processing, the pixels of the image are parallelly processed by the TSC transistor array, so the output value of the devices must be uniform.
To evaluate the device homogeneity and reliability of the logic behaviour, we present raw test data for the logical output current of 9 pixels in our array as a supplement to The Flattened data in Fig. 4 is restored here. Input data, truth tables, and actual output can be compared more intuitively. The processing and colour bars of the data here are the same as in Fig. 4.