## Abstract

Superconducting computing promises enhanced computational power in both classical and quantum approaches. Yet, scalable and fast superconducting memories are not implemented. Here, we propose a fully superconducting memory cell based on the hysteretic phase-slip transition existing in long aluminum nanowire Josephson junctions. Embraced by a superconducting ring, the memory cell codifies the logic state in the direction of the circulating persistent current, as commonly defined in flux-based superconducting memories. But, unlike the latter, the hysteresis here is a consequence of the phase-slip occurring in the long weak link and associated to the topological transition of its superconducting gap. This disentangles our memory scheme from the large-inductance constraint, thus enabling its miniaturization. Moreover, the strong activation energy for phase-slip nucleation provides a robust topological protection against stochastic phase-slips and magnetic-flux noise. These properties make the Josephson phase-slip memory a promising solution for advanced superconducting classical logic architectures or flux qubits.

## Introduction

A Josephson junction (JJ) consists of a localized discontinuity (weak link) in the order parameter of two superconducting electrodes^{1}, where the dissipationless current ruled by the Cooper pairs transport is controlled by the macroscopic quantum phase difference (*φ*) across the junction. Weak links are typically realized in the form of a thin insulator, a semiconductor or metallic wire, or a narrow superconducting constriction^{1,2}. The junction current-phase relation (CPR) strongly depends on the structural attributes of the constriction, i.e., on how its effective length (*L*, i.e., the distance between the superconducting leads), width (*w*), and thickness (*t*) compare with the superconducting coherence length (ξ_{w})^{2}. In a fully superconducting one-dimensional JJ (*w*, *t* ≪ ξ_{w}) the CPR evolves from the single-valued distorted sinusoidal characteristic, typical of the short-junction limit (*L* ≪ ξ_{w} Fig. 1a) and of non-superconducting weak links, to the multi-valued function obtained in the long regime (*L* ≫ ξ_{w}, Fig. 1b)^{2}. In the latter scenario, multiple (odd) solutions are available to the system at fixed *φ*, and the steady state will depend on the history of *φ*. In the specific example of Fig. 1b, three solutions are possible for the Josephson current (*I*_{s}) at *φ* close to *π*. Two of them are energetically stable, they correspond to two local minima in the Josephson energy^{3} and are topologically discriminated by the parity of the winding number of the superconducting phase along the wire^{4,5} which reflects into two opposite directions of *I*_{S}(*φ*)^{6}, as indicated in Fig. 1b by the even (red) and odd (blue) branches of *I*_{s}. In order to switch between these two stable branches, a 2*π* slippage of the superconducting phase along the weak link is required. The slippage passes through the third backward solution in the CPR, a metastable state which corresponds to a saddle point in the Josephson energy separating the two stable minima and forming the barrier of a double-well potential. In analogy with the physics of topological insulators, this intermediate metastable state is gapless, and is associated with the formation of a phase-slip center in the middle of the junction^{3,7}. The large superconducting condensation energy lost in this gapless center is at the origin of the strong phase-slip energy barrier separating the two topological branches. We take advantage of this topologically protected double-well potential to implement a robust and permanent superconducting memory: The Josephson phase-slip memory (PSM). Differing from similar quantum phase-slip memories^{8}, the geometry of the PSM has been conceived for deterministic control of the state via an external magnetic field, while stochastic quantum or thermally-activated phase slips are exponentially suppressed. As described below, these events are negligible thanks to the low resistance of the nanowire *R*_{N} < *R*_{q}*L*/ξ_{w}, where *R*_{q} = *h*/*e*^{2} = 6.5 kΩ^{9}.

## Results

### Implementation of the memory cell

The design of a proof-of-concept PSM requires an architecture enabling the tuning of the superconducting phase and the definition of an efficient readout scheme. To finely control *φ*, the JJ is inserted in a superconducting loop, where an external magnetic field gives rise to a total flux (Φ) piercing the ring area. Stemming from fluxoid quantization^{10}, the superconducting phase difference across the weak link is given by *φ* = 2*π*Φ/Φ_{0} (where Φ_{0} ≃ 2.067 × 10^{−15} Wb is the flux quantum) while the phase drop along the loop is negligible (see “Methods” section for details). The phase difference, together with the topological index, determines the amplitude of the superconducting gap in the local density of states (DOS) of the wire^{9}, which can be probed by a metallic electrode tunnel-coupled to the middle of the junction, thereby implementing a superconducting quantum interference proximity transistor (SQUIPT)^{11}, as sketched on top of Fig. 1c. As a result, at fixed Φ the amplitude of the tunneling current (*I*) flowing through the probing electrode will depend on the even/odd parity of the topological index of the junction codifying the logic [0] and [1] states of the PSM cell (Fig. 1d). Encoding the memory state in the parity of the winding number is a common feature to all flux-based superconducting memories, including, e.g., nano-SQUIDs^{12,13} flux qubits^{14} or kinetic-inductance memories^{15} from which it shares the low dissipation and high operation speeds. But, differing from the latter approaches, the dynamics of the memory cell here is entirely dominated by the physics of the weak link. The readout in the SQUIPT is based on tunneling spectroscopy of the weak link and the hysteresis in the magnetic flux is not a consequence of an unbalance between the ring and junction inductance but is an intrinsic property of the CPR.

The scanning electron micrograph (SEM) of a representative PSM cell is shown in Fig. 1e together with a top-down and cross-section scheme in Fig. 1f. Realized through a suspended-mask lithography technique (see “Methods” for fabrication details), the weak link consists of a one-dimensional Al nanowire (green, *t* = 20 nm and *w* = 90 nm) with a length *L* ~ 400 nm, embedded in a micron-sized 70-nm-thick Al ring (yellow). In addition, a 15-nm-thick normal metal electrode (red, Al_{0.98}Mn_{0.02}) is tunnel-coupled to the center of the wire (with a normal-state tunnel resistance *R*_{t1} ≃ 65 kΩ). To measure the tunneling current, a second Al lead (green) is tunnel-coupled to the normal metal electrode (with a normal-state resistance *R*_{t2} ≃ 90 kΩ)^{16}. Based on the device structural parameters, we estimate the ratio *L*/ξ_{w,0} ≃ 6, where ξ_{w,0} ≃ 65 nm is the zero-temperature coherence length^{17}, thereby providing the frame of the long-junction regime^{2,9} (see “Methods” for details). Within these geometrical constrains and thanks to the low resistivity of Al (*ρ* < *R*_{q}ξ_{w}), both quantum and thermally-activated phase slips are negligibly small, with rates < 10^{−289} Hz (see “Methods” for more details on the estimate). Notably, the PSM is completely made of aluminum compounds thus ensuring high-quality tunnel barriers and full compatibility of all fabrication steps for industrial scaling.

### Magneto-electric response

To test the PSM transport properties and assess the operation parameters of the memory cell, we first performed a preliminary magneto-electric characterization at bath temperature *T* = 25 mK. Figure 2a shows the current vs voltage characteristics (*I*(*V*)) of a typical device measured at Φ = 0 (black curve) and Φ = Φ_{0}/2 (orange curve). At zero magnetic flux, the quasiparticle tunnel current is suppressed for ∣*V*∣ ≲ 400 *μ*V due to the presence of two S-I-N tunnel junctions in series and is consistent with the Al gap of ≃200 *μ*eV for both the readout lead (Δ_{Al}) and the weak link (Δ_{w}(Φ = 0)). The latter can be modulated by the external magnetic flux^{11,16}, showing a reduction of about 50% at Φ = Φ_{0}/2 (orange line), Δ_{w}(Φ = Φ_{0}/2) ≃ 100 *μ*eV (see also Supplementary Fig. 1 for more details).

Differently from short-junction SQUIPTs^{16,18}, the *I*(Φ) characteristic is not only Φ_{0}-periodic, but it is also strongly hysteretic in Φ. This is highlighted in Fig. 2b, where the tunnel current measured at *V* = 300 *μ*V as a function of increasing (purple trace) and decreasing (green trace) magnetic flux is shown. The forward trace exhibits periodic maxima followed by sudden jumps corresponding to the nucleation of a phase-slip center in the superconducting nanowire^{2,7,9}. Accordingly, the backward trace evolves in a totally specular fashion. The evolution of *I*(Φ) on the bias voltage is shown in Fig. 2c. The hysteresis loop drawn by the back and forth *I*(Φ) exhibits a reduction of its width (*δ*Φ) by increasing *V*, as quantified also in Fig. 2d. This trend can be ascribed to a local overheating in the weak link induced by the quasiparticle current flowing through the probing junction which enlarges ξ_{w}(*T*)^{1} thereby deviating the CPR towards the single-valued non-hysteretic form^{2,9}. The relative separation between the two *I*(Φ) branches can be quantified by a parameter (*ζ*) defined as the ratio between the current drop at the phase-slip transition and the current at the hysteresis crossing point, *ζ* = *δ**I*/*I*(Φ = *n*Φ_{0}/2), where n is an integer odd number. A large *ζ* improves the visibility of the PSM logic states. Similarly to *δ*Φ, the increase of *V* induces a monotonic reduction of *ζ*, as shown in Fig. 2e.

### Memory operation with DC readout

The typical operation cycle of the PSM memory cell is sketched in Fig. 3a. A bias flux (Φ_{B}) is required to access the multi-valued state enclosed within the hysteretic domain (\({{{\Phi }}}_{{{{{{{{\rm{B}}}}}}}}\_\min }=({{{\Phi }}}_{0}-\delta {{\Phi }})/2,{{{\Phi }}}_{{{{{{{{\rm{B}}}}}}}}\_\max }=({{{\Phi }}}_{0}+\delta {{\Phi }})/2\)). Writing (erasing) operations are performed by lowering (increasing) the total flux below (above) the hysteretic domain by means of short pulses. As a consequence, the parity of the topological index switches between odd and even and the tunneling current between low and high current state. Figure 3b shows a real-time writing/erasing operation in the continuous-read mode, i.e., with a fixed a bias voltage *V* = 300 *μ*V. The bias flux is set at 0.54Φ_{0}, just above the crossing point of the hysteresis to avoid degeneracy in the current amplitude (Fig. 2c). The memory is then initialized in the [0] state corresponding to a current *I* ≃ 43 pA. By applying a negative flux pulse down to Φ_{W} = 0.33Φ_{0}, the PSM logic state suddenly transits to [1] as detected by the current jump to *I* ≃ 90 pA. Conversely, the logic state [0] is recovered via a positive erasing flux pulse up to Φ_{E} = 0.75Φ_{0}. The device unequivocally shows the typical behavior of a memory cell upon many erasing/writing cycles. From the real-time characteristic is also possible to quantify the energy required for the writing/erasing operations. This can be estimated from the energy difference of the system in the two flux configurations that can be simplified in \(E({{{\Phi }}}_{{B}_{{{max}}},{B}_{{{min}}}})-E({{{\Phi }}}_{0})\simeq \frac{{{{\Phi }}}_{0}}{2{{{{{{{{\mathcal{L}}}}}}}}}_{{{{{{\mathrm{K}}}}}}}}\frac{\delta {{\Phi }}}{2}\), where \({{{{{{{{\mathcal{L}}}}}}}}}_{{{K}}}\) is the kinetic inductance of the JJ^{8}. In our experimental configuration, the estimated energy is ~0.1 eV, which is consistent with the predictions for the energy of the topological barrier \(U \sim {{{\Delta }}}_{{{{{w}}}}}\frac{\hslash }{{e}^{2}{R}_{{{N}}}}\frac{L}{{\xi }_{{{w}}}}\)^{9}. Notably, differing from conventional flux-based superconducting memories, the inductance of the PSM ring is not relevant for the device which can be made negligibly small without any loss of hysteresis or functionality. This allows the miniaturization of the PSM that could be further operated with a flux generated by supercurrents directly injected in a small portion of the superconducting ring^{19}, therefore eliminating the requirement of an external magnetic field but with the disadvantage of an additional feed line integrated in the device.

The ability of a memory cell to retain the data even when the power is temporarily turned off is called non-volatility, which, even if not essential for RAM memory, is an adding value for energy saving and data storage. The PSM requires two power sources: one to generate the bias flux Φ_{B} and one for the readout signal. The former was provided by an external superconducting magnet controlled by a current source, then power dependent. To overcome this limitation Φ_{B} could also be generated by a permanent dissipationless superconducting coil as well as a metallic ferromagnetic layer buried in the semiconducting substrate or by directly employing a ferromagnetic insulator as dielectric substrate^{20,21}. Alternatively, a proper phase bias might be generated with an additional ferromagnetic pi-junction^{22} inserted in the ring or through a phase-battery^{23}. The readout voltage is only required to probe the resistance state of the PSM. As demonstrated in Figure 3c, temporarily and repeated measures of both logic states do not affect the stored data with a readout dissipation as low as *P*_{[0]} ≃ 25 fW and *P*_{[1]} ≃ 40 fW for the logic state [0] and [1], respectively, and only limited by the noise of the current amplifier. This low dissipated power combined with the intrinsic cutoff time *τ*_{R} ≃ 30 ps estimated from the RC circuit of the tunnel junctions (see “Methods” section for details) yields predicted tiny energy required per bit readout *J*_{[0]} = *P*_{[0]}*τ*_{R} ≃ 4.7 *μ*eV and *J*_{[1]} = *P*_{[1]}*τ*_{R} ≃ 7.5 *μ*eV. These values were only estimated and stem from the severe bandwidth limitations of the cryogenic filters. Similar to rapid single flux quantum, the writing/erasing process is expected with a switching time of ~1 ps which is typical for small superconducting loops^{24,25,26}. The PSM speed is therefore expected to be on par with current state-of-the-art superconducting memories both in the reading and in the writing/erasing process^{24,25,27,28,29}.

### Memory robustness and operation with AC readout

The robustness of the PSM against flux fluctuations is tested by superimposing to the working biasing flux a sizable sinusoidal signal (Φ_{AC}, Fig. 4a). The PSM shows optimal stability with respect to flux oscillations, as shown in Fig. 4b for *V* = 300 *μ*V and Φ_{B} = 0.56Φ_{0}. The memory preserves the stored state and keeps the readout value of the two logic states well separated for fluctuations Φ_{AC} ≃ 0.08Φ_{0}, then ~ 50% of the hysteretic domain of the memory *δ*Φ, at least. Interestingly, thanks to the opposite sign of the magnetoconductance of PSM in the two topological states (visible for instance in Fig. 2b, c), the AC flux modulation induces an AC response in the tunneling current which acquires a *π* shift when switching between the two logic states [0] and [1]. This phase shift provides a complementary and efficient method to probe the parity of the JJ winding number, which is not affected by the position of Φ_{B} within the hysteretic domain, or by the low visibility of the DC readout signal (see also Supplementary Figs. 4 and 5 for more details). This allows operating the memory cell also in the degenerate point Φ_{B} = Φ_{0}/2, where the energies of the [0] and [1] states are equal, a basic condition to implement a phase-slip qubit^{8,14}. Therefore, the PSM provides an alternative low-frequency method for the qubit readout. With the phase-based readout, the persistency of the PSM have been tested up to almost three days, as shown in Fig. 4c. The memory is initialized to logic state [1], and the readout is performed every 4 h. No sign of signal degradation has been observed even after ~3 days of measurement confirming the vanishing phase-slip rate (~10^{−289} Hz) as estimated from our parameters^{7,9} (see “Methods” for details on the estimate). As a consequence, the memory error rate expected for quantum and thermally-activated phase slips is infinitesimally small and errors can be generated only by large magnetic-flux fluctuations (≳*δ*Φ) of the driving magnetic flux. The other source of error that might degrade the memory state is the reading current which could switch the memory via inductive coupling to the ring or by quenching the superconductivity of the weak-link, as commonly happens for superconducting kinetic inductance memories^{13}. Differing from the latter, the high resistance of the probing tunnel barrier strongly limits the reading current to ≲nA, then much smaller than the current required for switching (~mA)^{19} and the critical current of the weak-link (≳*μ*A for an Al nanowire^{30}). This makes also the error rate during readout operation negligible. High temperature can degrade the performance of PSM by increasing ξ_{w}(*T*)^{1} thereby lowering the JJ effective length and driving the nanowire junction towards the non-hysteretic single-valued CPR occurring for *L* ≲ 3.5ξ_{w}^{2,31}. In addition, thermal activation can substantially increase the phase-slip rate in the vicinity of the transition, that is at \(\phi \,\lesssim\, {\phi }_{{B}_{{{max}}}}\) and \(\phi \, \gtrsim\, {\phi }_{{B}_{{{min}}}}\)^{9}. Figure 5a shows the evolution of the hysteresis loop at several bath temperatures (*T*). The hysteresis progressively fades out by increasing *T*, but persists up to 1.1 K, which corresponds to ~85% of the nanowire critical temperature, with *δ*Φ reduced to about the 12% of the base temperature value (Fig. 5b). Consequently, also the contrast *ζ*(*T*) lowers by increasing *T*, as shown in Fig. 5c. Still, the visibility of the hysteresis loop at high temperatures demonstrates the strength of the PSM with substantial protection of the topological state even in the presence of a sizable amount of hot quasiparticles^{4}. Although the low *δ*Φ achieved at high temperature degrades the robustness of the memory with respect to flux noise, it also allows writing the memory cell with smaller fluxes for a total cost of operation down to ~10 meV.

## Discussion

In summary, we have envisioned and demonstrated an original persistent Josephson phase-slip single memory cell that takes advantage of fluxoid quantization to codify two logic states in the topological index of the system, i.e., the parity of the superconducting winding number^{5}. Differing from conventional superconducting loops^{12,13,25}, here the separation between the two topological states is provided by the large phase-slip barrier, which is unique to long superconducting JJs^{4,9}. Moreover, its operation mechanism is completely independent of the size or inductance of the superconducting loop thus allowing device miniaturization only limited by fabrication capabilities. The memory exploits conventional superconductors thereby avoiding the use of complex ferromagnetic metals typical of present superconducting memories^{24,26,27,28,29,32}. Notably, the performances of the PSM are competing with state-of-the-art superconducting memories with an extremely low energy dissipation per bit operation (~10^{−24} J and ~10^{−20} J for readout and write, respectively) and high operation speed (up to ~30 ps and ~1 ps for readout and write, respectively). Thanks to the topological protection, the PSM shows endurance, persistence, and high-temperature operation (up to ~1 K), only limited by the Al critical temperature. The use of vanadium^{18} or niobium^{33}, therefore, could extend the memory operation above liquid He temperature, and further promote miniaturization thanks to the lower coherence length of these metals with respect to Al.

In addition, our phase-based readout scheme ensures protection against magnetic flux fluctuations and provides ideal visibility in all the operation ranges. In fact, despite being intrinsically slower than conventional methods (high-speed lock-in amplifiers reach nowadays a clock frequency of ~600 MHz), the phase-based readout can be a valuable approach for the readout of phase-slip qubits. Furthermore, scalability to large arrays of PSM cells might be designed by taking advantage of the well-known architectures employed for transition-edge sensors, since both devices are based on precise resistance measurement. In particular, frequency-domain multiplexing or microwave resonators together with SQUID amplifiers^{34} could be used for the selective readout of each PSM composing the total memory.

Sneak currents can be avoided by employing strongly non-linear resistors between each single memory unit, such as superconductor/insulator/normal metal/insulator/superconductor Josephson junctions. Integrating superconducting current feed lines in the ring^{19} will allow scaling also the writing procedure with the additional cost of wiring complexity. Yet, the presence of independent write and read lines, with the former characterized by a low impedance, increases stability against perturbations of the read current and might simplify the integration of the PSM with existing superconducting logic elements including rapid single flux quantum^{24,25,26}, reciprocal quantum logic^{35}, quantum flux parametrons^{36}, Josephson field-effect transistors^{37}, and gate-controlled cryotrons^{17,38,39}. Yet, the strong topological protection and stability observed in the PSM make our approach promising in light of the implementation of phase-slip flux qubits^{8,14} and quantum memories.

## Methods

### Device fabrication details

The hybrid memory cells were realized by the shadow-mask lithography technique. The suspended resist-mask was defined by electron-beam lithography (EBL) onto a SiO_{2} wafer. All metal-to-metal clean interfaces, and metal-to-oxide barriers were realized in an ultra-high vacuum (UHV) electron-beam evaporator (EBE) with a base pressure of 10^{−11} Torr equipped with a tiltable sample holder suitable for multi-directional depositions. In order to obtain wire/ring transparent interfaces, which is crucial for the device operation, the use of the same material is strongly recommended^{16}. Therefore, the nanowire and the ring of the PSM were realized with aluminum. Furthermore, the Al film evaporation is relatively simple, and its high-quality native oxide allows the realization of good tunnel barriers through oxygen exposure at room temperature. At first, 15 nm of Al_{0.98}Mn_{0.02} were evaporated at an angle of −18° to realize the normal metal electrode. Subsequently, the sample was exposed to 60 mTorr of O_{2} for 5 min in order to form the thin insulating AlMnOx layer. Next, the sample holder was tilted to 10° for the deposition of 20 nm of Al realizing the SQUIPT nanowire (length *L* = 400 nm, width *w* = 90 nm, and thickness *t* = 20 nm) and the superconducting electrodes. Finally, a thicker layer of Al (*t*_{R} = 70 nm) was evaporated at 0° to realize the superconducting loop of circumference ~ 7.6 μm, and average width *w*_{R,ave} ≃ 600 nm.

### Magneto-electric characterization

The magneto-electric characterization of the samples was performed at cryogenic temperatures in a ^{3}He–^{4}He dilution refrigerator (Triton 200, Oxford Instruments) equipped with RC-filters of resistance ~2kΩ. The out-of-plane magnetic field was applied via a superconducting magnet driven by a low-noise current source (Series 2600, Keithley Instruments). The DC measurements were performed in a two-wire voltage-bias configuration through a low-noise voltage DC source (GS200, Yokogawa) coupled with a room-temperature current preamplifier (Model 1211, DL Instruments) (Fig. 1c). The AC characterization was performed via a combination of DC bias and low-frequency lock-in technique. A DC bias voltage (*V*) was applied to the device. A current given by the sum of a DC and AC sinusoidal modulation energized the superconducting magnet. The readout current oscillations induced by variation of Φ, and the phase of the signal (with respect to the flux oscillations) were recorded by a lock-in amplifier (SR830, Stanford Research Systems). Further details on the readout scheme can be found in the note 5 of the Supplementary Information.

### Device parameters

Based on the device structure, we estimate the zero-temperature nanowire coherence length ξ_{w,0} = \(\sqrt{\hslash D/{{{\Delta }}}_{{{{{w}}}},0}}\simeq 65\) nm, where *ℏ* is the reduced Planck constant, *D* ≃ 18 cm^{2}/s is the diffusion coefficient, and Δ_{w,0} ≃ 200 *μ*eV is the zero-temperature gap in Al. The nanowire critical temperature is *T*_{C,w} = Δ_{w,0}/1.764*k*_{B} ≃ 1.31 K, where *k*_{B} is the Boltzmann constant. At low temperature, the ratio *L*/ξ_{w,0} ≃ 6 confirming the frame of the long JJ regime for the PSM^{2}. The single-valued CPR limit (achieved for ξ_{w,short} ≳ *L*/3.5 ~ 114 nm) is reached at temperature \({T}_{{{{{{\mathrm{short}}}}}}}={T}_{{{{{{\mathrm{C}}}}}},{{w}}}(1-0.85{2}^{2}\frac{{\xi }_{{{w}},0}l}{{\xi }_{{{w}},{{{{{\mathrm{short}}}}}}}^{2}}) \sim 1.29\) K^{2}, where *l* = 3*D*/*v*_{F} ≃ 3 nm is the nanowire mean free path, and *v*_{F} = 2.03 × 10^{6} m/s is the Fermi velocity of Al.

The kinetic inductance (\({{{{{{{{\mathcal{L}}}}}}}}}_{{{K}}}\)) of a long JJ depends on the geometry and superconducting properties of the nanowire^{9}. In our case, at 25 mK it takes the value \({{{{{{{{\mathcal{L}}}}}}}}}_{{{K}}}=\frac{{R}_{{{N}}}\hslash }{\pi {{{\Delta }}}_{{{{{w}}}}}}\frac{1}{\tanh \frac{{{{\Delta }}}_{{{{{w}}}}}}{2{k}_{{{B}}}T}}\simeq 18\) pH^{40}. The nanowire normal-state resistance is given by \({R}_{{{N}}}=\frac{L}{wt\sigma }\simeq 17\ {{\Omega }}\), where *σ* = *D**N*_{f}*e*^{2} ≃ 1 × 10^{7} S/m is the Al film conductance (with *N*_{f} = 2.15 × 10^{47}/J/m^{3} the density of states at the Fermi energy of Al). Analogously, the ring total inductance (including both the geometric and kinetic contributions) takes the value \({{{{{{{{\mathcal{L}}}}}}}}}_{{{{{{\mathrm{R}}}}}}} \sim\) 1 pH^{16} (with normal-state resistance *R*_{R} ≃ 1.4 Ω). The contribution of the ring to the total inductance of the SQUIPT yields a screening parameter \(\beta ={{{{{{{{\mathcal{L}}}}}}}}}_{{{{{{\mathrm{R}}}}}}}/{{{{{{{{\mathcal{L}}}}}}}}}_{{{K}}}\,\lesssim\, 0.1\). The small *β* cannot account for the hysteretic behavior of the PSM, which stems, differently, from the long-junction regime of the Josephson nanowire. The writing/erasing time (*τ*_{W,E}) is mainly due to the time required to polarize the SQUIPT with the external flux. It is given by \({\tau }_{{{{{{\mathrm{W}}}}}},{{{{{\mathrm{E}}}}}}}={{{{{{{{\mathcal{L}}}}}}}}}_{{{{{{\mathrm{SQUIPT}}}}}}}/{R}_{{{{{{\mathrm{SQUIPT}}}}}}} \sim\) 1 ps, where \({{{{{{{{\mathcal{L}}}}}}}}}_{{{{{{\mathrm{SQUIPT}}}}}}}={{{{{{{{\mathcal{L}}}}}}}}}_{{{K}}}+{{{{{{{{\mathcal{L}}}}}}}}}_{{{{{{\mathrm{R}}}}}}}\) and *R*_{SQUIPT} = *R*_{N} + *R*_{R} are the total inductance and resistance of the SQUIPT, respectively. The readout time (*τ*_{R}) is predominantly limited by the characteristic time of the two tunnel barriers, *τ*_{R} = *τ*_{t1} + *τ*_{t2} ~ 30 ps, where *τ*_{t1} = *R*_{t1}*C*_{t1} ~ 20 ps is the characteristic time of the first tunnel junction, and *τ*_{t2} = *R*_{t2}*C*_{t2} ~ 10 ps is the time constant of the second junction. The junctions capacitances (*C*_{t1} ~ 0.3 fF and *C*_{t1} ~ 0.1 fF) are estimated from the area and the typical specific capacitance of AlOx tunnel barriers ~50 fF/μm^{2}.

### Phase-slip rates

Stochastic phase-slips are possible via quantum tunneling and thermal activation. They scale exponentially with the phase-slip barrier, the former with −*U*/Δ_{w,0} while the latter with −*U*/*k*_{B}*T*. Both of them are small for *R*_{ξ} < *R*_{q} (where *R*_{ξ} = *R*_{N}ξ_{w}/*L*), as demonstrated in the following. The quantum phase-slip rate is^{8}:

where \({{{\Omega }}}_{{{qps}}}\simeq 0.85\frac{{{{\Delta }}}_{{{{{w}}}}}}{\hslash }\frac{L}{{\xi }_{{{w}}}}\sqrt{\frac{{R}_{{{{{{\mathrm{q}}}}}}}}{{R}_{\xi }}}\simeq 75\) THz is the quantum phase-slips attempt frequency. With the parameters of our experiment, we obtain the negligibly small Γ_{qps} ~ 2 × 10^{−289} Hz. Thermally-activated phase-slips rate reads^{7}:

where \(\delta F=2.7\frac{T_{{{{{\mathrm{c}}}}}}-T}{T}U\) is the free energy difference of the potential barrier and \({{{\Omega }}}_{{{TAPS}}}\simeq 5.5\frac{{k}_{{{B}}}T}{\hslash }\frac{L}{{\xi }_{{{w}}}}\sqrt{\frac{\delta F}{{k}_{{{B}}}T}}\) is the attempt frequency. In the temperature range of the experiment *T* < < *T*_{c}, Γ_{TAPS} is expected to be even smaller than Γ_{qps}. As an example, at *T* = 100 mK the attempt frequency is Ω_{TAPS} ≃ 500 THz and Γ_{TAPS} ~ 10^{−474} Hz. From these equations is possible to see that Γ_{TAPS} is relevant only at a temperature very close to Tc.

## Data availability

The data that support the findings of this study are available from the corresponding author upon reasonable request.

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## Acknowledgements

We acknowledge M. Cuoco and P. Virtanen for fruitful discussions. N.L., E.S., and F.G. acknowledge partial financial support from the European Union’s Seventh Framework Program (FP7/2007-2013)/ERC Grant No. 615187- COMANCHE. N.L., E.S., and F.G. were partially supported by EU’s Horizon 2020 research and innovation program under Grant Agreement No. 800923 (SUPERTED). The work of F.P. was partially supported by the Tuscany Government (Grant No POR FSE 2014-2020) through the INFN-RT2 172800 project. The authors acknowledge the European Union (Grant No. 777222 ATTRACT) through the T-CONVERSE project.

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E.S. and F.G. conceived the experiment. N.L. fabricated the samples with inputs from F.P. N.L. and E.S. performed the measurements. N.L. analyzed the experimental data with inputs from E.S. and F.G. All the authors discussed the results and their implications equally at all stages and wrote the manuscript.

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Ligato, N., Strambini, E., Paolucci, F. *et al.* Preliminary demonstration of a persistent Josephson phase-slip memory cell with topological protection.
*Nat Commun* **12, **5200 (2021). https://doi.org/10.1038/s41467-021-25209-y

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