Foundry-compatible high-resolution patterning of vertically phase-separated semiconducting films for ultraflexible organic electronics

Solution processability of polymer semiconductors becomes an unfavorable factor during the fabrication of pixelated films since the underlying layer is vulnerable to subsequent solvent exposure. A foundry-compatible patterning process must meet requirements including high-throughput and high-resolution patternability, broad generality, ambient processability, environmentally benign solvents, and, minimal device performance degradation. However, known methodologies can only meet very few of these requirements. Here, a facile photolithographic approach is demonstrated for foundry-compatible high-resolution patterning of known p- and n-type semiconducting polymers. This process involves crosslinking a vertically phase-separated blend of the semiconducting polymer and a UV photocurable additive, and enables ambient processable photopatterning at resolutions as high as 0.5 μm in only three steps with environmentally benign solvents. The patterned semiconducting films can be integrated into thin-film transistors having excellent transport characteristics, low off-currents, and high thermal (up to 175 °C) and chemical (24 h immersion in chloroform) stability. Moreover, these patterned organic structures can also be integrated on 1.5 μm-thick parylene substrates to yield highly flexible (1 mm radius) and mechanically robust (5,000 bending cycles) thin-film transistors.

T o minimize electronic device feature sizes, eliminate crosstalk in circuitry, and scale-up soft matter optoelectronic device fabrication, foundry-compatible patterning of all functional layers is essential for creating multiple circuitry layers, and systems integration [1][2][3][4][5][6] . Specifically, highresolution patterning of robust semiconductor films in thin-film transistor (TFT) arrays must optimize the charge transport and on-current/off-current ratio (I on :I off ) ratio, while achieving reliable deposition by solution-processing of all additional non-TFT components, including the gate dielectric/gate contact in top-gated TFTs, and the source-drain electrodes in top-contact TFTs, as well as planarization/passivation layers in both architectures [7][8][9][10][11][12] . Several pioneering studies realized patternable photocrosslinked polymer semiconductors by appending crosslinkable moieties to the polymer backbone. Following these approaches, crosslinked patterned films of various polythiophenes with 50-100 µm features and TFT mobilities of 10 −3 -10 −1 cm 2 V −1 s −1 were demonstrated [13][14][15][16] . To further enhance pattern resolution, alternative approaches have focused on developing chemically orthogonal photoresist/protective layers to preserve the underlying semiconductor layer integrity during photolithography 1,8,17,18 . In this way high-resolution features (1-5 µm) were realized with mobilities of ca. 10 −1 cm 2 V −1 s −1 . Nevertheless, foundry-compatible patterning methodologies that are lowcost, ambient processable, environmentally benign, highly efficient and reliable, and enable high-resolution patterned features without compromising device performance have remained elusive. Thus, the existing patternable semiconductors for orthogonal photolithography are chemically and/or morphologically unstable in most solvents as well as metal etchants, and to date cannot be realistically implemented in circuitry fabrication. Moreover, the crosslinking of functionalized polymeric semiconductors typically relies on high deep-UV radiation doses in inert atmosphere, which is incompatible with efficient FAB processing.

Results
Semiconductor blend film and device fabrication. The semiconducting polymers DPP and N2200 were selected because they are among the most efficient p-and n-type semiconductors for OTFTs while SU8 and PCell are inexpensive and readily available. polymers perform the best. Details of the semiconductor blend film deposition, curing/patterning, and OTFT fabrication processes are reported in the Supporting Information. Briefly, in a typical experiment for bottom-gate top-contact (BGTC) OTFT fabrication, used for the p-type DPP-based devices, the semiconductor/PA solution (x% in weight semiconductor vs. PA, x = 25, 50, and 75; total concentration = 4 mg mL −1 ) was spin-coated on trichloro(octyl)silane-treated SiO 2 /Si substrates at 1500 rpm for 30 s in ambient with~30% relative humidity. After baking the films at 95°C for 1 min, they were exposed through a shadow mask to a 365 nm ultraviolet (UV) light (Electrodeless UV lamp, dose = 60-80 mJ cm −2 ) or by a maskless aligner for highresolution patterning, followed by annealing at 95°C for 2 min (Fig. 2b). Next, the resulting cured x% DPP/SU8 blend films were developed with CHCl 3 for 5 s, to achieve the desired patterned films with thickness of 40-70 nm, depending on the semiconductor and semiconductor/PA weight ratio. The BGTC OTFT structures were completed by thermally depositing gold source/ drain contacts with channel width/length (W/L, μm) of 1000/100 or 40/10, defined by metal mask or lift-off process, respectively (vide infra). Top-gate bottom-contact (TGBC) OTFTs were employed for n-type N2200-based devices, which were fabricated/ patterned on glass substrates with thermally evaporated Au source-drain contact (W/L = 1000/100) and completed by spincoating a 740 ± 10 nm-thick poly(methyl methacrylate) (PMMA) gate dielectric layer (C i = 3.6 nF cm −2 ), and thermally evaporating a gold gate contact. Fig. 1c Blend film morphological characterization. The film morphologies and microstructures of the semiconductor/PA films during the patterning process were investigated by AFM, ToF-SIMS, and GIWAXS. Fig. 2a and Supplementary Fig. 9 show representative AFM images of pristine DPP and 50% DPP/SU8 (DPP:SU8 = 1:1 w/w) films before photocuring (uncured), after UV irradiation (cured), after development (developed/patterned), and after 24 h immersion in CHCl 3 (soaked). The pristine DPP films (120 nm thick) exhibit uniform crystalline domain structures with an rms roughness (σ rms ) = 1.7 nm, while the 50% DPP/SU8 film (~50 nm thick) has smaller crystalline domains and a slightly rougher surface (σ rms = 2.6 nm). Negligible morphological and thickness changes are evident for 50% DPP/SU8 films after UV irradiation. After developing, the film thickness is found to contract slightly to~45 nm due to partial removal of the top DPP/SU8 portion. Impressively, negligible morphological and thickness changes are observed on 24 h immersion in CHCl 3 , retaining a σ rms = 2.9 nm. This blend film thickness and morphology evolution with curing/ developing indicate multilayer VPS in the semiconductor/polymer blends as supported by the ToF-SIMS data (Fig. 2b-d and Supplementary Fig. 10). signatures of SU8 and the DPP, respectively, and their ratio can be used to assay the distribution of the two components with film depth. 25 Thus, the ToF-SIMS depth profile for uncured 50% DPP/SU8 samples (1 etching cycle represents~1 nm, Fig. 2b) indicates formation of a multilayer structure (Fig. 2d) with a top layer having comparable SU8-DPP contents and of thickness~4 nm, a central layer greatly enriched in SU8 with thickness of~20 nm, and a lower layer primarily consisting of DPP (~10 nm), and then exclusively (another~15 nm), composed of DPP nanofibers (NFs). [20][21][22][23][24][25][26] Regarding the developed 50% DPP/SU8 sample, which is only~5 nm thinner than the undeveloped sample, it's ToF-SIMS result indicates a similar composition profile with only the film upper portion affected. However, the film bulk, and particularly the bottom pure DPP layer, remains intact. GIWAXS measurements on the DPP-based films (Fig. 2e, 28 Thus, SU8 promotes DPP aggregation in solution or during the film deposition, yielding fibers with polymer chains π-π stacked at~0.4 nm distances. This morphology is known to enhance conjugation length and carrier mobility in πpolymers. 29,30 Furthermore, a (100) reflection appears in all blends at~0.30 nm (absent in pristine DPP films), corresponding to lamellar spacings of d lam = 2.07-2.13 nm. This may reflect formation of a mixed orientation morphology in blending (Supplementary Table 2). Along the out-of-plane direction (Fig. 2f), all films exhibit a family of (n00) reflections corresponding to a lamellar stacking located at~0.32 Å −1 and corresponding to a d lam of 1.93-1.99 nm. The lamellar stacking coherence lengths (ξ) for all films are summarized in Fig. 2g and Supplementary Tables 1-4. 31 The ξ of the as-deposited DPP is 24.6 nm and falls to 16 [13][14][15]. AFM images of 25% DPP/SU8 films from different processing conditions in Supplementary Fig. 16, clearly reveal the presence of DPP nanofibers on the top surface, which are removed after developing in CHCl 3 . Regarding PA effects, the uncured 50% DPP/PCell films ( Supplementary Fig. 17) exhibit a distinctive fibrillar surface morphology (σ rms = 4.7 nm) 32,33 . The film morphology is unchanged after UV irradiation, but the film smoothens after CHCl 3 development for 5 s (σ rms = 3.1 nm) and eventually the fibrous morphology disappears after 24 h CHCl 3 immersion, yielding a fish scale morphology. By decreasing (25% DPP/PCell) or increasing (75% DPP/PCell) the semiconductor contents in the blend, similar morphological evolutions are noted ( Supplementary Fig. 18). In the case of N2200-based films (Supplementary Figs. 9 and 19), pure N2200 films exhibit a typical smooth surface with σ rms of only 0.3 nm. 34 The 50% N2200/SU8 films also exhibit a fibrillar morphology and σ rms = 2.1 nm; however, the fibrous structure decreases on UV irradiation and the film exhibits a σ rms = 0.8 nm. After development, these films also exhibit a fish scale morphology with a greatly increased σ rms = 3.5 nm again due to partial removal of the N2200/SU8 discontinuous phase 33 . Note that selective removal of SU8 or PCell from the uncured blends with the developing solvent (See Experimental Section for details) leaves 15 nm thick fibrillar DPP or N2200 films consistent with a semiconductor-rich bottom interface ( Supplementary Fig. 20), demonstrating the VPS between semiconductors and PAs 20,25,33,35,36 . Impressively, these fibrillar films, exhibiting good phase purity and connectivity, are OTFT-active (Supplementary Fig. 21).
Regarding the GIWAXS results for N2200-based films, pure N2200 films ( Supplementary Fig. 22) exhibit typical preferential π-face-on polymer crystallite orientation with a broad π-stacking peak (010) at 1.61 ± 0.0012 Å −1 (d π = 3.9 ± 0.003 Å) known for this polymer. 37 The in-plane plot shows four orders of lamellar reflection with the lowest order (100) located at 0.25 ± 0.0002 Å −1 (d lam = 2.48 ± 0.004 nm) and three orders of (001) backbone periodicity the first located at 0.46 ± 0.0011 Å −1 (d back = 1.38 ± 0.007 nm). 38 When N2200 is blended with SU8 at 50%, the outof-plane (010) and in-plane (00n) reflections are strongly suppressed vs. that of neat N2200 while the other reflections, such as the (n00) reflections, persist or even increase in intensity (Supplementary Figs. 23 and 24). However, comparing the plots proceeding from uncured to soaked blend films, the patterning process has minimal effect on the N2200 macromolecular packing and texturing. Thus, the ξ of the (100) peak for the 50% N2200/SU8 films (Fig. 2g Figs. 22 and 25). These comprehensive characterizations for various semiconductor/PA films demonstrate that blending with the PA, as well as curing and development, does not compromise semiconductor film texturing. Furthermore, all blends remain macroscopically uniform and continuous. Finally, VPS and nanofiber formation during the film deposition process is confirmed. Thus, the combined characterizations demonstrate positive morphological and structural characteristics which are critically important for high-resolution patterning of the semiconductor film and efficient charge transport in the corresponding devices as verified in the next section.
Device electrical properties and stability. Next, the performance of the DPP BGTC and N2200 TGBC OTFTs was evaluated, starting with large channel (W/L = 1000/100 μm) devices based on pristine/unpatterned DPP as well as developed/patterned x% DPP/SU8 and x% DPP/PCell films (Fig. 3a). Note that the DPPbased devices exhibit typical p-type behavior as seen in the transfer and output plots of Fig. 3b-e. The DPP OTFTs exhibit very high off-currents (in the level of 10 −7 A), large subthreshold swings (SS = 5.9 ± 0.3 V dec −1 ), and small current on/off ratios (10 2 -10 3 ), reflecting gate/parasitic leakage currents typical of high-mobility/unpatterned semiconductors 39,40 . In contrast, the patterned 50% DPP/SU8 and 50% DPP/PCell devices (semiconductor area = 1.1 × 1.3 mm 2 ) exhibit low off/gate currents (10 −10 A, instrumentation-limited), lower SS (2.2 ± 0.2 V dec −1 ), high current on/off ratios (>10 6 ) and textbook output curves. Electrical parameters were extracted using standard MOSFET equations and are summarized in Table 1. The average carrier mobility (μ) and threshold voltage (V T ) for the DPP devices are 0.4 ± 0.05 cm 2 V −1 s -1 and 20.2 ± 2.5 V, respectively. These values are comparable to previously reported pristine DPP data in cases where the mobility was realistically estimated 20,28,41,42 . The mobilities of the patterned 50% DPP/SU8 and 50% DPP/PCell OTFTs are 0.24 ± 0.04 cm 2 V −1 s −1 (V T = 18.6 ± 2.3 V) and 0.20 ± 0.03 cm 2 V −1 s −1 (V T = 29.7 ± 2.8 V), respectively, indicating minimal degradation during patterning. Varying the DPP content in the blend to lower (25%) and higher (75%) values does not significantly change the transport characteristics or field-effect mobility, which remains in the range of 0.1-0.22 cm 2 V −1 s −1 (Supplementary Figs. 26 and 27). Interestingly, the V T s for the 25% DPP/SU8 and 25% DPP/Cell OTFTs are much lower than those of the pristine DPP and other DPP-based blends. Seen from Supplementary Table 2, we believe that when the DPP concentration is lower than a critical point (perhaps percolation related), the edge-on packing contribution (62.6% for 25%DPP/SU8) is much lower than those of 50%DPP/SU8 (94.9%) and pristine DPP (99.6%). Thus, different switching behavior is observed at high Vg (shown in the transfer curves, Supplementary Fig. 27), resulting in much lower V T s. Finally, DPP and 25% DPP/SU8 OTFTs with TGBC and BGBC (bottom-gate bottom-contact) architectures were also evaluated. However, they all exhibit poor performance likely due to unfavorable charge injection from pristine Au electrodes into DPP in bottom-contact devices ( Supplementary Fig. 28).
Regarding the pristine N2200, x% N2200/SU8, and x% N2200/ PCell TGBC devices, Figs. 3f, g and Supplementary Fig. 29 show representative transfer and output curves. The patterned devices exhibit optimal I-V characteristics with lower off-currents (10 −10 A), lower gate currents (10 −8 A), lower SS (~2.0 V dec −1 ), and nearzero turn on voltages vs. the unpatterned N2200 TFTs, while the electron mobilities of 0.09 ± 0.02 cm 2 V −1 s −1 are comparable to those of literature N2200 devices. 43 To avoid the toxic chloroform solvent used above and to make this fabrication and patterning process potentially acceptable in semiconductor FABs, the green solvent THF was used as proof-of-concept for 50% N2200/SU8 films. It is found that these films exhibit satisfactory patterning and electrical performance (Supplementary Fig. 30). Note, we also attempted to fabricate DPP TFTs with THF, however, this semiconductor is not sufficiently soluble in this solvent for processing.
Next, we evaluated the chemical, thermal and bias stabilities of our patterned OTFTs vis-à-vis those based on the pristine semiconductors. As noted in the morphology and GIWAXS sections above, the DPP/SU8 films are stable upon long-term exposure to CHCl 3 . Thus, we investigated how the corresponding TFTs, fabricated on robust Si/SiO 2 gate contact/dielectric platforms respond to a similar treatment. The data in Figs. 4a-3c indicate that while the DPP TFTs are immediately damaged upon immersion in CHCl 3 , the patterned 50% DPP/SU8 devices function even after CHCl 3 immersion for 24 h, but with the transfer curve shifting negative with increasing immersion time and pinned maximum on-current and carrier mobility. The negative shift probably originates from additional charge traps due to solvent intercalation and nanoscopic morphological changes in the semiconductor during extended solvent immersion. Regarding the thermal stability, blending organic semiconductors with high glass-transition temperature (T g ) insulating polymers has proved to be an efficient way to improve film morphological and device thermal stability. 44 Considering the high SU8 T g (~200°C), we next compared the performance changes of OTFTs in ambient based on DPP and 50%DPP/SU8 films. As shown in Fig. 4d and Supplementary Fig. 31, the 50% DPP/SU8 devices retain a high µ of 0.7 ± 0.1 cm 2 V −1 s −1 upon thermal annealing up to 175°C, while the DPP ones do not function at temperatures higher than 150°C. The operational stability of representative N2200/SU8 and DPP/ SU8 OTFTs was also probed by applying a gate voltage (V GS = ±20 V) for up to 4000 s (Figs. 4e, f, Supplementary Fig. 32). The results show that TGBC 25%N2200/SU8 devices exhibit excellent bias stability with threshold voltage shift (ΔV T ) and mobility shift (Δµ) below 4 V and 0.02 cm 2 V −1 s −1 , respectively. BGTC patterned 50% DPP/SU8 devices are also tested and exhibit larger ΔV T (~16 V) and Δµ (~0.06 cm 2 V −1 s −1 ) variation than the DPP devices during the bias test (V GS = −20 V for up to 4000 s). However, note that pristine BGTC DPP TFTs exhibit a similar stress behavior [ΔV T (~12 V) and Δµ (~0.05 cm 2 V −1 s −1 )]. These data indicate that, as expected, a topgate architecture better stabilizes devices during bias stress in ambient and, more importantly, the addition of PA does not impact the device stability of either device.
High-resolution patterning and ultraflexible devices. Owing to the excellent chemical stability of the above semiconducting  polymer blends, additional BGTC device architectures were fabricated by combining patterned 50% DPP/SU8 semiconducting lines of different widths (w = 1-20 µm) with photolithographically patterned Au Source/Drain electrodes (layout in Fig. 5a). Note, 50% DPP/SU8 lines were fabricated as discussed above by photo exposure/CHCl 3 development, while Au patterning used a lift-off process involving the S1813 photoresist, the aggressive AZ ® 400 K developer (alkaline solution), and acetone. Fig. 5b-e demonstrate that metal electrodes with channel length/ width of 10/100 µm can be precisely patterned on the semiconducting lines. Representative TFT transfer plots and transport parameters of TFTs based on these channel topologies are shown in Fig. 5f and Supplementary Fig. 33. Note here that the effective channel width, W, of these devices is n × w, where n are the number of semiconducting lines in the channel area. The hole mobility of these TFTs remains 0.09 ± 0.02 cm 2 V −1 s −1 when the line width is greater than 5 µm, then gradually falls to 0.05 ± 0.01 cm 2 V −1 s −1 when the line width is 1 µm, likely due to the large effect of the line sidewalls. The V T and SS are relatively stable at 9 ± 0.8 V and 1.4 ± 0.1 V dec −1 , respectively. TFT arrays (100 dpi) were also fabricated with different channel lengths which show uniform device performance (Supplementary Fig. 34). These data demonstrate the realization of very robust semiconductor structures with large surface/volume ratios which should also be suitable for fabricating sensors/TFTs and electrochemical transistors.
Finally, to further validate materials and processing generality, ultraflexible BGTC and TGBC TFT arrays based on patterned 50% DPP/SU8 and 50% N2200/SU8 films, respectively, were fabricated on 1.5 µm-thick parylene substrates. For simplicity of integration, a 300 nm-thick parylene film was also used as the gate dielectric (see parylene dielectric properties in Supplementary Fig. 35). Optical images, device structures, and representative transfer plots of these devices are shown in Fig. 6a-c and  Supplementary Fig. 36. The ultraflexible 50% DPP/SU8 and 50% N2200/SU8 devices exhibit an average mobility of 0.03 ± 0.01 and 0.01 ± 0.005 cm 2 V −1 s −1 , respectively. Importantly, negligible mobility/V T changes are observed after peeling the devices from the rigid support and bending them 5000 times at a radius of 1 mm despite microcracks forming in areas surrounding the device (Fig. 6d and Supplementary Fig. 37). Finally, Fig. 6e shows the static switching characteristics and the gain of an ultraflexible inverter based on the p-+ n-TFTs. The wide-range switching voltage with a 40 V supply voltage is 22.2 ± 0.3 V, where the high noise margin and low noise margin are 13.2 ± 0.2 V and 15.6 ± 0.2 V, respectively. This inverter exhibits a gain of 11, rivalling or exceeding the performance of other solution-processed flexible devices. [45][46][47][48]

Discussion
We demonstrate a versatile strategy for foundry-compatible highresolution patterning of organic semiconducting films by crosslinking a vertically phase-separated blend of the semiconducting polymer and a UV photocurable additive (PA). This process is effective for both p-and n-type semiconducting polymers, can use environmentally benign solvents (e.g., THF) under ambient atmosphere, and yields ultraflexible transistor circuitry. GIWAXS, AFM, and TOF-SIMS analyses reveal formation of textured semiconductor film morphologies with a vertically multiphaseseparated channel layer preserved during the patterning process. Both PAs promote the formation of close-packed DPP or N2200 nanofiber structures at the bottom of the blend film, which is crucial to achieving functional devices even when only 25 wt% of the semiconductor is added. Equally important, PA addition influences semiconductor polymer backbone orientation, especially for blends with a >50wt % PA content. Excessive PA significantly reduces the edge-on content, thus degrading device performance. Compared with TFTs based on the pristine (unpatterned) polymer semiconductors, the present polymer blend-based patterned devices exhibit optimal transfer/output curves, higher thermal/chemical stability, respectable p-type and n-type TFT performance, and enable the fabrication of ultraflexible TFTs and complementary inverters. Note that the TFT mobilities reported here are not limited by the fabrication methodology, which should be readily applicable to current generation semiconducting polymers. [49][50][51][52] A possible limitation of the present patterning method relying on VPS is the limited charge transport along the vertical direction since the PA-rich layer is required to protect the underlying semiconducting polymer layer during photolithography. Thus the addressable patterning of high-performance vertical devices, such as organic photovoltaic devices, photodetectors and light-emitting diodes, may be more challenging. Solution-processed organic electronics, especially those enabled by printing technologies, are on the verge of large-scale industrialization. Thus, we can envision that the continuous development of high-performance semiconductors compatible with environmentally benign solvents, together with the present patterning methodology, will facilitate the industrialization of solution-processed organic electronics. 53 Synthesis of PCell. PCell was synthesized according to our previously published procedure. 19 Specifically, a suspension of 1.0 g of cellulose in 40 mL of N, N-dimethylacetamide was kept at 130°C for 2 h under stirring. After the slurry was allowed to cool to 100°C, 3.0 g of anhydrous lithium chloride was added. The cellulose was completely dissolved as the solution was cooled to room temperature under stirring. Next, the cellulose solution was put into an ice bath for 15 min, followed by adding 3.2 g of cinnamoyl chloride. The reaction mixture was heated at 80°C for 24 h before pouring into an excess volume of ethanol (100 mL). The precipitate was collected by filtration and then it was extracted with ethanol in a Soxhlet extractor for 12 h. Finally, we obtained the dried PCell with a yield of 84.3% after drying under vacuum at 50°C. Fabrication of DPP and DPP/SU8 films. Approximately 1 h before device fabrication, the DPP/chloroform and SU8/chloroform solutions were mixed in a volume ratio of 1:3, 1:1, and 3:1, for fabricating the 25%, 50%, and 75% DPP/SU8 blends, respectively. The mixed solution was spin-coated on OTS-treated SiO 2 /Si substrates at 1500 rpm for 30 s in ambient (RH~30%). After prebaking at 95°C for 1 min, the films were exposed to 365 nm UV light (F300S, Inpro Technologies, dosage = 60-80 mJ cm −2 ) through a photomask, followed by annealing at 95°C for 2 min. For high-resolution patterning, maskless aligner (Heidelberg MLA150) equipped with 375 nm laser light was used. Next, the resulting cured films were developed in chloroform for 5 s to achieve the desired patterns. After that, the films were annealed at 150°C for 30 min in a glovebox. The final film thickness is 40-70 nm depending on the DPP/SU8 ratio. DPP films were prepared by spin-coating of DPP/CHCl 3 solutions at 1500 rpm for 30 s in ambient (RH~30%), followed by thermal annealing at 150°C for 30 min in a glovebox. The film thickness of DPP film is~120 nm. Note here the use of low boiling point (<120°C) solvent is critical for complete VPS, and protecting the underlying polymer semiconductors during photolithography. Other high boiling point solvents such as chlorobenzene, dichlorobenzene, which were generally used in previous reports on semiconductor/ insulating polymer blends, are unsuccessful for efficient patterning. [20][21][22][23][24][25][26] Fabrication of DPP/PCell films. About 1 h before device fabrication, DPP/ chloroform solution and PCell/chloroform solution were mixed with a volume ratio of 1:3, 1:1, and 3:1 for fabricating the 25%, 50%, and 75% DPP/PCell blends, respectively. The mixed solution was spin-coated on OTS-treated SiO 2 /Si substrates at 1500 rpm for 30 s in ambient (RH~30%). After prebaking at 120°C for 1 min, the films were exposed to 365 nm UV light (dose = 60-80 mJ cm −2 ) through a photomask, followed by annealing at 120°C for 5 min. For high-resolution patterning, maskless aligner (Heidelberg MLA150) equipped with 375 nm laser light was used. Next, the resulting cured films were developed in chloroform for 5 s to achieve desired patterns. After that, the films were annealed at 150°C for 30 min in a glovebox. The final film thickness is 40-70 nm depending on the DPP/PCell ratio.
Deposition and patterning of gold electrodes. For OTFTs with large channel size (W/L = 1000/100 µm), gold electrode patterns (30 nm thick) were achieved by thermal evaporation underneath semiconductor blend films through a metal mask.
For OTFTs with small channel sizes (W = 20-200 µm L = 1-20 µm), a MCC Primer 80/20 layer (from MicroChem) was first spin-coated on semiconductor layer, followed by 100°C/annealing for 60 s. S1813 photoresist was then spincoated at 4000 rpm for 60 s and thermal annealed at 115°C for 60 s. After that, the resulting films were exposed to 365 nm UV light (dose = 150 mJ cm −2 ) through a photomask and developed in AZ ® 400 K/H 2 O (v/v = 1/4) developer. For highresolution patterning, maskless aligner (Heidelberg MLA150) equipped with 375 nm laser light was used. Finally, 30 nm-thick gold films were thermally evaporated on the films and the source/drain patterns were achieved by stripping in acetone.
For DPP-based devices with TGBC structures, PMMA is used as dielectric layer (see below for details).
Fabrication of TGBC N2200 and N2200/SU8 devices. About 1 h before device fabrication, N2200/chloroform solutions and SU8/chloroform solutions were mixed in volume ratios of 1:3, 1:1, and 3:1 for fabricating the 25%, 50%, and 75% N2200/SU8 blends, respectively. Cr/Au source/drain electrodes (2/23 nm thick) on glass substrates were first thermally evaporated through a metal mask. The mixed solution was spin-coated on the above substrates at 1500 rpm for 30 s in ambient (RH~30%). After prebaking at 95°C for 1 min, the films were exposed to 365 nm UV light (dose = 60-80 mJ cm −2 ) through a photomask, followed by annealing at 95°C for 2 min. For high-resolution patterning, maskless aligner (Heidelberg MLA150) equipped with 375 nm laser light was used. Next, the resulting cured films were developed with SU8 developer for 5 s to achieve the desired patterns. After that, the films were annealed at 150°C for 30 min in a glovebox. The final film thickness is 40-50 nm depending on the N2200/SU8 ratio. Pure N2200 films were also spin-coated at 1500 rpm for 30 s in ambient (RH~30%), followed by thermal annealing at 150°C for 30 min in a glovebox. The film thickness of N2200 film is~25 nm. Regarding the gate dielectric layer, a PMMA/2-butanol solution was spin-coated on the N2200 or N2200/SU8 films at 1500 rpm for 60 s in a glovebox, followed by 80°C/3 h annealing. Finally, the gate electrodes were thermally evaporated through a metal mask to obtain bottom-contact top-gate OTFTs.
Regarding the use of the green solvent tetrahydrofuran (THF), the fabrication method is identical to above procedure except that the solvent is replaced with THF and SU8 developer is diluted with IPA (SU8 developer: IPA = 7:3 in vol).
Fabrication of TGBC N2200/PCell devices. About 1 h before device fabrication, N2200/chloroform solution and PCell/chloroform solution were mixed in volume ratios of 1:3, 1:1, and 3:1 for fabricating the 25%, 50%, and 75% N2200/PCell blends, respectively. Cr/Au source/drain electrodes (2/23 nm thick) on glass substrates were first thermally evaporated through a metal mask. The mixed solution was spin-coated on above substrates at 1500 rpm for 30 s in ambient (RH~30%). After prebaking at 120°C for 1 min, the films were exposed to 365 nm UV light (dose = 60-80 mJ cm −2 ) through a photomask, followed by annealing at 120°C for 5 min. For high-resolution patterning, maskless aligner (Heidelberg MLA150) equipped with 375 nm laser light was used. Next, the resulting cured films were developed in SU8 developer for 5 s to achieve the desired patterns. After that, the films were annealed at 150°C for 30 min in a glovebox. The final film thickness is 40-50 nm depending on the N2200/SU8 ratio. PMMA dielectric and top gate electrodes were deposited by following the above procedure.
Fabrication of ultraflexible BGTC DPP/SU8 BGTC devices. A fluorinated polymer solution [Novec 1700 and 7100 (v/v = 1:7), 3 M] was spin-coated on solvent-cleaned glass substrates, serving as a delamination layer, and next a 2 µmthick parylene film was deposited with an SCS Labcoter ® 2 (PDS2010) deposition system. Next, 50 nm-thick bottom-gate electrodes were thermally evaporated though a metal mask, followed by deposition of a 300 nm-thick parylene film as the gate dielectric layer. After that, patterned 50% DPP/SU8 films and S/D electrodes (W/L = 1000/100 µm) were deposited following the procedure used for the rigid devices. Finally, the entire device arrays were delaminated from the glass/ fluorinated polymer carrier prior to electrical measurements and bendability tests.
Fabrication of ultraflexible TGBC N2200/SU8 TGBC devices. A fluorinated polymer solution [Novec 1700 and 7100 (v/v = 1:7), 3 M Company] was spincoated on solvent-cleaned glass substrates, serving as a delamination layer, next a 1.5 µm-thick parylene film was deposited with an SCS Labcoter ® 2 (PDS2010) deposition system. Cr/Au source/drain electrodes (2/23 nm-thick) on glass substrates were thermally evaporated and defined by photolithography as described above. The W/L is 1000/50 µm. After that, patterned 50% N2200/SU8 films were deposited following the procedure used for the rigid devices, followed by evaporation of a 300-nm-thick parylene film as a dielectric layer. The devices were finished by depositing 50-nm-thick top-gate Au electrodes. Finally, the entire device arrays were delaminated from the glass/fluorinated polymer carrier prior to electrical measurements and bendability tests.
Film and device characterization. Film morphologies were measured with a Bruker Dimensional Icon AFM system in the tapping mode. To acquire the bottom semiconductor morphologies, the spin-coated films (DPP/SU8, DPP/PCell, N2200/ SU8 and N2200/PCell) were immersed in SU8 developer for 5 s and then rinsed with IPA; thus SU8 or PCell can be selectively removed. Optical images were taken using a Nikon Eclipse E200 microscope and film thickness is measured by a Dektak 150 surface profilometer (Veeco Instruments, Inc.). GIWAXS measurements were performed at Beamline 8ID-E at the Advanced Photon Source (APS) at Argonne National Laboratory. Samples were irradiated with a 10.9 keV X-ray at an incidence angle 0.13°-0.15°in vacuum for two summed exposures of 2.5 s (totaling 5 s of exposure), and scattering X-rays were recorded by a Pilatus 1 M detector located 228.16 mm from the sample. The collected images were then processed by using the GIXSGUI software. The background was subtracted by fitting the curves to an exponential decay, and peaks were fitted to an intermediate Lorentzian. The peak width and positions were used to calculate the correlation length and layer spacing. The coherence length was calculated using a modified Scherrer analysis which accounts for instrument resolution using the standard shape factor (K) = 0.866 for lamellar polymer aggregates. For DPP-based films, the second order reflection (~0.62 Å −1 ) in the out-of-plane plot is chosen for calculation of coherence length as the first-reflection is obviously affected by beam signal and the 3rd/4th order reflections are relatively weak. The electrical measurements on the dielectrics, OTFTs, and inverters were performed under ambient condition using an Agilent B1500A semiconductor parameter analyzer. The carrier mobility (μ) was evaluated in the saturation region. The areal capacitance for 300 nm SiO 2 /Si is 10.5 nF cm −2 here, while the areal capacitances of the parylene dielectric is calculated to be 8.6 nF cm −2 . To test the chemical stability of 50% DPP/SU8 films, OTFTs based on DPP and patterned 50% DPP/SU8 films on 300 nm SiO 2 /Si substrates were immersed in CHCl 3 for 10 s, then the devices were annealed at 100°C for 1 min in ambient before testing to remove the remaining solvent inside the films. After that, the procedure of immersing, annealing and testing was repeated for several times until the total immersing time reached 24 h. To test the thermal stability, the DPP and 50% DPP/SU8 devices were put on a hotplate. The devices were tested when the temperature increased to the desired set point.