An electronic neuromorphic system for real-time detection of High Frequency Oscillations (HFOs) in intracranial EEG

In this work, we present a neuromorphic system that combines for the first time a neural recording headstage with a signal-to-spike conversion circuit and a multi-core spiking neural network (SNN) architecture on the same die for recording, processing, and detecting High Frequency Oscillations (HFO), which are biomarkers for the epileptogenic zone. The device was fabricated using a standard 0.18$\mu$m CMOS technology node and has a total area of 99mm$^{2}$. We demonstrate its application to HFO detection in the iEEG recorded from 9 patients with temporal lobe epilepsy who subsequently underwent epilepsy surgery. The total average power consumption of the chip during the detection task was 614.3$\mu$W. We show how the neuromorphic system can reliably detect HFOs: the system predicts postsurgical seizure outcome with state-of-the-art accuracy, specificity and sensitivity (78%, 100%, and 33% respectively). This is the first feasibility study towards identifying relevant features in intracranial human data in real-time, on-chip, using event-based processors and spiking neural networks. By providing"neuromorphic intelligence"to neural recording circuits the approach proposed will pave the way for the development of systems that can detect HFO areas directly in the operation room and improve the seizure outcome of epilepsy surgery.


Introduction
The amount and type of sensory data that can be recorded is continuously increasing due to the recent progress in microelectronic technology 1 . This data deluge calls for the development of low-power embedded edge computing technologies that can process the signals being measured locally, without requiring bulky computers or the need for internet connection and cloud servers. In particular, biomedical signal processing and clinical applications will greatly benefit from a direct and local processing of physiological measurements using compact and portable devices. Spiking neural networks (SNNs) have been proposed as a powerful computing paradigm for processing spatio-temporal signals and detecting complex patterns within them 2, 3 , so they are well suited for biomedical applications.
Neuromorphic engineering 4 has produced mixed signal neuromorphic circuits that can directly emulate the physics of real neurons to implement faithful models of neural dynamics and SNNs 5,6 . By integrating many silicon neurons onto microelectronic chips, it is possible to build compact and low-power SNN processing systems to efficiently process time-varying signals in real time. Examples of neuromorphic systems developed with this goal in mind have already been applied to processing Electrocardiogram (ECG) or Electromyography (EMG) signals [7][8][9][10] .
However, these systems were sub-optimal, as they required external bio-signal recording, frontend devices, and data conversion interfaces. Bio-signal recording headstages typically comprise analog circuits to amplify and filter the signals being measured, and can be highly diverse in specifications depending on the application 11 . For example, neural recording headstages for experimental neuroscience target high-density recordings [12][13][14][15] and minimize the circuit area requirements, while devices used for clinical studies and therapeutic applications require a small number of recording channels and the highest possible signal-to-noise ratio (SNR) [16][17][18][19] In this work, we present a neuromorphic system that combines for the first time a neural recording headstage with a signal-to-spike conversion circuit and a multi-core SNN architecture on the same die for recording, processing, and detecting clinically relevant biomarkers in intracranial EEG recordings (iEEG) from epilepsy patients.
Epilepsy is the most common severe neurological disease. In about one-third of patients, seizures cannot be controlled by medication. Selected patients with focal epilepsy can achieve seizure freedom if the epileptogenic zone (EZ), which is the brain area generating the seizures, is correctly identified and surgically removed in its entirety. Presurgical and intraoperative measurement of iEEG signals is often needed to identify the EZ precisely [20][21][22][23] . High Frequency Oscillations (HFOs) have been proposed as a new biomarker in iEEG to delineate the EZ 17, 18, 24-28 While HFOs have been historically divided into "ripples" (80-250 Hz) and "fast ripples" (FR, 250-500 Hz), detection of their co-occurrence was shown to enable the optimal prediction of postsurgical seizure freedom 24 . In that study, HFOs were detected automatically by a software algorithm that matched the morphology of the HFO to a predefined template (Morphology Detector) 24, 29 An example of such an HFO is shown in Fig. 1a. While software algorithms are used for detecting HFOs offline, compact embedded neuromorphic systems that can record iEEGs and detect HFOs online, in real time, would be able to provide valuable information during surgery, and simplify the collection of statistics in long-term epilepsy monitoring 30, 31 . Here we show how our neuromorphic system paves the way toward the development of a compact embedded battery-operated system that can be used for the real-time online detection of HFOs.
In this paper we first describe the design principles of the HFO detection architecture and its neuromorphic circuit implementation. We discuss the characteristics of the circuit blocks proposed and present experimental results measured from the fabricated device. We then show how the neuromorphic system performs in HFO detection compared to the Morphology Detector 24 on iEEG recorded from the medial temporal lobe 32 2 Results Figure 1 shows how prerecorded iEEG 32 was processed by the frontend headstage and the SNN multi-core neuromorphic architecture. Signals were band-passed filtered into Ripple and Fast Ripple bands (Fig. 1a,b,f). The resulting waveforms were converted into spikes using asynchronous delta modulator (ADM) circuits 33, 34 (Fig. 1c,f) and fed into the SNN architecture (Fig. 1d,g). Neuronal spiking signalled the detection of an HFO (Fig. 1e bottom). All stages were first simulated in software to find optimal parameters and then validated with the hardware components. The HFO detection was validated by comparing the HFO rate across recording intervals (Fig. 1i) and against postsurgical seizure outcome 24 . . For preprocessing the wideband EEG is filtered in Ripple band and Fast Ripple band. A baseline detection stage finds the optimum threshold that is applied in an Asynchronous Delta Modulator (ADM) which converts the signal to spikes. Signal traces are encoded by UP spikes (gray bars) and DOWN spikes (black bars), which are then fed as input into the SNN. The SNN is implemented as a two-layer spiking network of integrate and fire neurons with dynamic synapses. Each neuron in the second layer receives four inputs: two excitatory spike trains from UP channels and two inhibitory ones from DOWN channels. The parameters of the network were chosen to exhibit the relevant temporal dynamics and tune the neurons to produce output spikes in response to input spike train patterns that encode clinically relevant HFOs. (e, top) Time-frequency spectrum of the Fast Ripple iEEG of panel a. (e, bottom) Firing of SNN neurons indicate the occurrence of the HFO. (f) Block diagram of the neuromorphic system input headstage. The headstage comprises a low noise amplifier (LNA), two configurable bandpass filters and two ADM circuits that convert the analog waveforms into spike trains. (g) The spikes produced by the ADMs are sent to a multi-core array of silicon neurons that are configured to implement the desired SNN. (h) MRI with 7 implanted depth electrodes that sample the mesial temporal structures of a patient with drug resistant temporal lobe epilepsy (Patient 1). (i) Rates of HFOs detected by the neuromorphic SNN for recordings made across four nights for Patient 1. HFO rate and variability across intervals within a night is indicated by standard error bars. Recording channels AR1-2 and AR2-3 in right amygdala showed the highest HFO rates which were stable over nights. Thus, the neuromorphic system would predict that a therapeutic resection, which should include the right amygdala, would achieve seizure freedom. Indeed, a resection including the right amygdala achieved seizure freedom for >1 year.

The neuromorphic system
An overview of the hardware neuromorphic system components is depicted in Fig. 2. The chip (Fig 2c) was fabricated using a standard 180 nm Complementary Metal-Oxide-Semiconductor (CMOS) process. It comprises 8 input channels (headstages) responsible for the neural recording operation, band-pass filtering and conversion to spikes 35 , and a multi-core neuromorphic processor with 4 neurosynaptic cores of 256 neurons each, which is a novel type of Dynamic Neuromorphic Asynchronous Processor (DYNAP) based on the DYNAP-SE device 36 . The total chip area is 99 mm 2 . The 8 headstages occupy 1.42 mm 2 with a single headstage occupying an area of 0.15 mm 2 (see Fig. 2a). The area of the four SNN cores is 77.2 mm 2 with a single SNN core occupying 15 mm 2 . For the HFO detection task, the total average power consumption of the chip, at the standard 1.8 V supply voltage, was 614.3 W.  The total static power consumption of a single headstage was 7.3 W. The conversion of filtered waveforms to spikes by the ADMs consumed on average 109.17 W. The power required by the SNN synaptic circuits to process the spike rates produced by the ADMs was 497.82 W, while the power required by the neurons in the second layer of the SNN to produce the output spike rates was 0.2 nW. The block diagram of the hardware system functional modules is shown in Fig. 2b. The Field Programmable Gate Array (FPGA) block the right of the figure represents a prototyping device that is used only for characterizing the system performance. Figure 2c shows the chip photograph, and Fig. 2d represents a rendering of the prototyping Printed Circuit Board (PCB) used to host the chip. Figure 3 shows the details of the main circuits used in a single channel of the input headstage. In particular, the schematic diagram of the Low-Noise Amplifier (LNA) is shown in Fig. 3a. It consists of an Operational Transconductance Amplifier (OTA) with variable input Metal Insulator Metal (MIM) capacitors, that can be set to 2/8/14/20 pF and a Resistor-Capacitor (RC) feedback in which the resistive elements are implemented using MOS-bipolar structures 37 . The MOS-bipolar pseudoresistors 1 and 2, and the capacitors =200 fF of Fig. 3a were chosen to implement a high-pass filter with a low cutoff frequency of 0.9 Hz. Similarly, the input capacitors , , and the transistors of the OTA were sized to produce maximum amplifier gain of approximately 40.2 dB but can be adjusted to smaller values by changing the capacitance of . Figure 3b shows the schematic of the OTA, which is a modified version of a standard folded-cascode topology 38 . The currents of the transistors in the folded branch (M5-M10) are scaled to approximately 1/6th of the currents in the original branch M1-M4. The noise generated by M5-M10 is negligible compare to that of M1-M4 due to the  Figure 3. Schematic diagrams of the input headstage circuits. (a) Variable-gain LNA using variable input capacitor array and pseudo-resistors. The gain of this stage is calculated by / ; the use of the pseudo-resistors allows to reach small low cut-off frequencies. (b) Folded cascode OTA using resistive degeneration to reduce the noise influence of nMOS devices. Note that the current flowing through the bias branch is times smaller than the tail branch of the amplifier. (c) band-pass (Tow-Thomas) filters for performing second-order filtering in both ripple and fast-ripple bands as well as low-frequency component of the iEEG. Tunable pseudo resistors are used to adjust the filter gain, center-frequency and band-width. The same basic structure can be used to provide both low-pass and band-pass outputs, thus is desirable in terms of design flexibility. (d) Asynchronous Delta Modulator (ADM) circuit to convert the analog filter outputs into spike trains. The ADM input amplifier has a gain of / in normal operation when is low and the feedback PMOS switch is off. As the amplified signal crosses one of the two thresholds, or , an UP or DN spike is produced by asserting the corresponding REQ signal. A 4-phase handshaking mechanism produces the corresponding ACK signal in response to the spike. Upon receiving the ACK signal, the ADM resets the amplifier input and goes back to normal operation after a refractory period determined by the value of . The asynchronous buffers act as 4-phase handshaking interfaces that propagate the UP/DN signals to the on-chip Address-Event Representation (AER) spike routing network of Fig. 2. low current in these transistors. As a result, the total current and the total input-referred noise of the OTA was minimized.
To ensure accurate bias-current scaling, the currents of Mb2 and Mb4 in Fig. 3b were set using the bias circuit formed by Mb1, Mb3, and Mb5. The voltages 1 and 2 in the biasing circuit can be set by a programmable 6526-level integrated bias-generator, integrated on chip 39 . The current sources formed by Mb1 and Mb2 were cascoded to increase their output impedance and to ensure accurate current scaling. These devices operate in strong inversion to reduce the effect of threshold voltage variations. The source-degenerated current mirrors formed by M11, M12, Mb5 and resistors R1 and ×R1 assure that the currents in M5 and M6 are a small fraction of the currents in M3 and M4. The R1 gain coefficient was chosen at design time to be = 8.5. Thanks to the use of this source-degenerated current source scheme, the 1/ noise in the OTA is limited mainly to the effect of the input differential pair. Therefore, the transistors of the input-differential pair were chosen to be pMOS devices and to have a large area.

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The active filters implemented in our system are depicted in Fig. 3c. They comprise three operational amplifiers, configured to form a Tow-Thomas resonating architecture 40 . This architecture consists of a damped inverting integrator that is stabilized by 2 and cascaded with another undamped integrator, and an inverting amplifier for adjusting the loop-gain by a factor set by the ratio 6/ 5. The center frequency 0 of the bandpass filter can be calculated as 0 = 1/2 √ 3 4 1 2 . By choosing 3 = 4 = , we can then simplify it to 0 = 1/2 1. Similarly, the gain of the filter is | | = 4/ 1 and its bandwidth = 2 0 √ 3 4/ 2, but with our choice of resistors we can show that | | = / 1 and = 1/( 2 1). Therefore, this analysis shows that is responsible for setting 0 , 1 for adjusting the gain, and 2 for tuning the bandwidth. Moreover, due to the resistive range of the tunable double-PMOS pseudo resistors used in this design 41 , 0 was set in the sub-hundred Hertz region by choosing 1 = 10 . Figure 3d shows the schematic diagram of the ADM circuit 34 . There are four of such circuits per headstage channel. One for converting the wideband signal into spike trains; one for converting the output of the low-pass filter _ ; and two for converting the output of the two band-pass filters _ . The amplifier at the input of the ADM circuit in Fig. 3d implements an adaptive feedback amplification stage with a gain set by / that in our design is equal to 8 when is high, and approximately zero during periods in which is low. In these periods, defined as "reset assertion" the output of the amplifier is clamped to , while in periods when is high, the output voltage represents the amplified version of the input. The signal is then sent as input to a pair of comparators that produce either "UP" or "DN" digital pulses depending if is greater than or lower than . These parameters set the ADM circuit sensitivity to the amplitude of the Delta-change. The smallest values that these voltages can take is limited by the input offset of the ADM comparators (see , in Fig. 3d), which is approximately 500 V.
Functionally, the ADM represents a Delta-modulator that quantizes the difference between the current amplitude of and the amplitude of at the previous reset assertion. The precise timing of the / spikes produced in this way are deemed to contain all the information about the original input signal, given that the parameters of the ADM are known 42 . The UP and DN spikes are used as the request signals of the asynchronous AER communication protocol 43-45 used by the spike routing network for transmitting the spikes to the silicon neurons of the neuromorphic cores (Fig. 2). We call this event-based computation. These signals are pipelined through asynchronous buffers that locally generates / to reset the ADM with every occurrence of an UP or DN event. The output of the asynchronous buffer / ( ) conveys these events to the next asynchronous stages. The bias voltage controls the refractory period that keeps the amplifier reset and limits the maximum event rate of the circuit to reduce power consumption. The bias voltages and control the sensitivity of the ADM and the number of spikes produced per second, with smaller values producing spike trains with higher frequencies. Small and settings lead to higher power consumption and allow the faithful reconstruction of the input signal with all its frequency components. The ADM hyper parameters , , and can therefore be optimized to achieve high reconstruction accuracy of the input signal and suppress background noise (e.g., due to high-frequency signal components), depending on the nature of the signal being processed (see Methods). All of the 32 ADM output channels are then connected to a common AER encoder which includes an AER arbiter 46 used to manage the asynchronous traffic of events and convey them to the on-chip spike routing network. Figure 4 shows experimental results measured from the different circuits present in the input headstage. Fig. 4a shows the transient response of the LNA to a prerecorded iEEG signal used as input. The signal was provided to the headstage directly via an arbitrary waveform generator programmed with unity gain and loaded with a sequence of the prerecorded iEEG data with amplitude in the mV range. We also tested the LNA with an input sine wave of 100 Hz with a 1 mV peak-to-peak swing, revealing <1% of total harmonic distortion at maximum gain, and an output swing ranging between 0.7 V and 1.4 V. To characterize the input referred noise of the LNA, we shorted input terminals of the LNA, + , − , captured LNA output, , on a dynamic signal analyzer and divided it by the gain of the LNA, set to 100, and plotted output power spectral density (see Fig. 4b). The LNA generates a ≤ 100 nV/ √ noise throughout the spectrum. As the 1/ noise dissipates with the increase in frequency, the LNA noise only scales down to the thermal component. Thus, the noise for the Ripple band is < 10 nV/ √ and < 5 nV/ √ for the Fast Ripple band. Figure 4b shows how the noise generated by the LNA is well below the pre-recorded iEEG power, throughout the full frequency spectrum. The LNA features a programmable gain that can be set to 20 dB, 32 dB, 36 dB, or 40 dB. It has a > 40 dB common mode rejection ratio; it consumes 3 W of power per channel; and it has a total bandwidth, defined as /( · ), approximately equal to 11.1 KHz, when the capacitive load is set to =20 fF, the OTA transconductance to =20 nS and the amplifier gain to 40 dB (see Fig. 4c).  The on-chip bias generator can be used to set the filter frequency bands. For HFO detection, we biased the tunable pseudoresistors of the filters to achieve a cutoff frequency of 80 Hz for the low-pass filter, a range between 80 Hz and 250 Hz for the first bandpass filter, appropriate for Ripple detection, and between 250 Hz and 500 Hz for the second bandpass filter, to detect Fast Ripples (see Fig.4c). As we set the tail current of each single-stage OpAmp of Fig. 3c to 150 nA, each filter consumed 0.9 W of power. Figure 4d plots the spikes produced by the AMD circuit in response to Ripple-band data obtained from the pre-recorded iEEG measurements. We set the ADM refractory period to 300 s, making it the longest delay, compared to those introduced by the comparator and handshaking circuits, that are typically <100 s. The spike-rate of the ADM can range from few hundreds of Hz to hundreds of kHz depending on the values of , , and . Each ADM consumed 1.5 nJ of energy per spike, and had a static power dissipation of 96 nW.

System performance
The system-level performance is assessed by measuring the ability of the proposed device to correctly measure the iEEG signals, to properly encode them with spike trains, and to detect clinically relevant HFOs 24 via the SNN architecture.
The SNN architecture is a two-layer feed-forward network of integrate and fire neurons with dynamic synapses, i.e., synapses that produce post-synaptic currents that decay over time with first-order dynamics. The first layer of the network comprises four input neurons: the first neuron conveys the UP spikes that encode the iEEG signal filtered in Ripple band; the second neuron conveys the DN spikes derived from the same signal; the third neuron conveys the UP spikes derived from the Fast-ripple band signal, while the forth neuron conveys the DN spikes. The second layer of the network contains 256 neurons which receive spikes from all neurons of the input layer (see Fig. 5b). The current produced by the dynamic synapses of the second layer neurons decay exponentially over time at a rate set by a synapse-specific time-constant parameter. The amplitude of these currents in response to the input spikes depends on a separate weight parameter, and their polarity (positive or negative) depends on the synapse type (excitatory or inhibitory). In the network proposed, UP spikes are always sent to excitatory synapses and DN 7/16 spikes to inhibitory ones. All neurons in the second layer have the same connectivity pattern as depicted in Fig. 5b with homogeneous weight values. An important aspect of the SNN network lies in the way it was configured to recognize the desired input spatio-temporal patterns: rather than following the classical Artificial Neural Network (ANN) approach of training the network by modifying the synaptic weights with a learning algorithm and using identical settings for all other parameters of synapses and neurons, we fixed the weights to constant values and chose appropriate sets of parameter distributions for the synaptic time constants and neuron leak variables. Because of the different time-constants for synapses and neurons, the neurons of the second layer produce different outputs, even though they all receive the same input spike trains.
The set of parameter distributions that maximized the network's HFO detection abilities was found heuristically

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by analyzing the temporal characteristics of the input spike trains and choosing the relevant range of excitatory and inhibitory synapse time constants that produced spikes in the second layer only for the input signals that contained HFOs as marked by the Morphology Detector 24 (Figure 1a, Figure 5a). This procedure was first done using software simulations with random number generators and then validated in the neuromorphic analog circuits, exploiting their device mismatch properties. The software simulations were carried out using a behavioral-level simulation toolbox 49 based on the neuromorphic circuit equations, that accounts for the properties of the mixed-signal circuits in the hardware SNN. The hardware validation of the network was done using a single core of the DYNAP-SE neuromorphic processor 36 , which is a previous generation chip functionally equivalent to the one proposed, implemented using the same CMOS 180 nm technology node. The 256 neurons in this core received spikes produced by the ADM circuits of the analog headstage, as described in Fig. 5c. The ADM UP spikes were sent to the excitatory synapses, implemented using a DPI circuit 6, 49 that produce positive currents, and DN spikes were sent to complementary versions of the circuit that produce inhibitory synaptic currents. Both excitatory and inhibitory currents were summed into the input nodes of their afferent leaky integrate-and-fire silicon neuron circuit 6 , which produced output spikes only if both the frequency and the timing of the input spikes was appropriate (see Fig. 5c).
The bias values of the excitatory and inhibitory DPI circuits and of the neuron leak circuits were set in a way to match the mean values of the software simulation parameters. All neuron and synapse circuits in the same core of the chip share global bias parameters, so nominally all excitatory synapses would have the same time-constant, all inhibitory ones would share a common inhibitory time-constant value and all neurons would share the same leak parameter value. However, as the mixed-signal analog-digital circuits that implement them are affected by device mismatch, they exhibit naturally a diversity of behaviors that implements the desired variability of responses. Therefore, in the hardware implementation of the SNN, the distribution of parameters that produce the desired different behaviors in the second layer neurons emerges naturally, by harnessing the device mismatch effects of the analog circuits used and without having to use dedicated random number generators 50 . Figure 1e (bottom panel) shows an example of the activity of the hardware SNN in response to an HFO that was labeled as clinically relevant by the Morphology Detector 24 The iEEG traces in the Ripple band and Fast ripple band (Fig. 1a) and the time frequency spectrum (top panel of Fig. 1e) show the HFO shortly before the SNN neurons spike in response to it (bottom panel of Fig. 1e). The delay between the beginning of the HFO and the spiking response of the silicon neurons is due to the integration time of both excitatory and inhibitory synapse circuits, which need to accumulate enough evidence for producing enough positive current to trigger the neuron to spike.
To improve classification accuracy and robustness, we adopted an ensemble technique 51 by considering the assembly response of the 256 neurons in the network: the system is said to detect an HFO if at least one neuron in the second layer spikes in a 15 ms interval. We counted the number of HFOs detected per electrode channel and computed the corresponding HFO rate (Section 5). Examples of HFOs recorded from Patient 1 and detected by the hardware SNN are shown in Fig. 5a; several neurons respond within a few milliseconds after initiation of the HFO. Different HFOs produce different UP and DN spike trains, which in turn lead to different sets of second layer neurons spiking. Figure 5d shows the HFO rates calculated for each electrode from the recordings of this patient. Observe that not all the neurons in the second layer respond to the HFOs. Even for electrode channels with high HFO rates, a very small number of neurons fire at high rates.
The robustness of the HFO rate measured with our system can be observed in Fig 1i, where the relative differences of HFO rates across channels in Patient 1 persisted over multiple nights. To quantify this result we performed a test-retest reliability analysis by computing the scalar product of the HFO rates across all recording intervals (0.95 in Patient 1), where the scalar product is1 for highly overlapping spatial distributions, indicating that the HFO distribution persists over intervals.

Predicting seizure outcome
In Patient 1, the electrodes were implanted in right frontal cortex (IAR, IPR), the left medial temporal lobe (AL, HL) and the right medial temporal lobe (AR, AHR, PHR). The recording channels AR1-2 and AR2-3 in the right amygdala produced the highest HFO rates persistently. We included all channels with persistently high HFO rate in the 95% percentile to define the "HFO area". If the HFO area is included in the resection area, resection area (RA), we would retrospectively 'predict' for the patient to achieve seizure freedom. Indeed, right selective amygdalohippocampectomy in this patient achieved seizure freedom for >1 year. We validated the system performance across the whole patient group by performing the test-retest reliability analysis of all the data. The test-retest reliability score ranges from 0.59 to 0.97 with a median value of 0.91. We compared the HFO area detected by our system with the RA. For each individual, we then retrospectively determined whether resection of the HFO area would have correctly 'predicted' the postsurgical seizure outcome Table 1. Patient characteristics and postsurgical seizure outcome. We 'predict' seizure outcome for each patient based on resection of the HFO area that was delineated by the Morphology Detector 24 and the hardware SNN of our system. HS hippocampal sclerosis; ILAE seizure outcome classification of the International League Against Epilepsy.  (Table 1). Seizure freedom (ILAE 1) was achieved in 6 of the 9 patients. To estimate the quality of our 'prediction', we classified each patient as follows: we defined as "True Negative" (TN) a patient where the HFO area was fully located inside the RA and who became seizure free; "True Positive" (TP) a patient where the HFO area was not fully located within the RA and the patient suffered from recurrent seizures; "False Negative" (FN) a patient where the HFO area was fully located within the RA but who suffered from recurrent seizures; "False Positive" (FP) a patient where the HFO area was not fully located inside the RA but who nevertheless achieved seizure freedom. The HFO area defined by our system was fully included in the RA in patients 1 to 6. These patients achieved seizure freedom and were therefore classified as TN. In Patients 7 and 9, the HFO area was also included in the RA but these were classified as FN since these patients did not achieved seizure freedom. In Patient 8, the HFO area was not included in the RA and the patient did not achieve seizure freedom (TP).

Patient Histology/ Intervals Test-retest Outcome Follow-up Morphology
We finally compared the predictive power of our detector to that of the Morphology Detector 24 for the individual patients (Table 1) and over the group of patients ( Table 2). The overall prediction accuracy of our system across the 9 patients is comparable to that obtained by the Morphology Detector. The 100% specificity achieved by both detectors indicates that HFO analysis provides results consistent with the current surgical planning.

Discussion
The device presented here demonstrates the potential of neuromorphic computing for extreme-edge use cases that cannot rely on computation performed on remote computers (e.g., in the "cloud"), and that require compact and very low power embedded systems (e.g., for battery-operated hand-held operations). By integrating on the same chip both the signal acquisition headstage and the neuromorphic multi-core processor, we developed an integrated system that can demonstrate the advantages of neuromorphic computing in clinically relevant applications.

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this is the first instance of a headstage design that has the capability of adapting to numerous use cases requiring different gain factors and band selections, on the same input channel.
The approach followed to process the signals in the SNN and determine the right architecture for detecting HFOs is radically different from the deep-learning one: rather than using arrays of neurons with homogeneous parameters and no temporal dynamics, and relying on the changes in the synaptic weights, we emulated the dynamic properties of real neurons with mixed-signal analog/digital circuits and exploited their variability to find the right set of randomly distributed parameters for tuning the network to detect HFOs.
The simulations of the SNN not only allowed us to define the optimal architecture for HFO detection, but also gave us solutions for setting the hyperparameters of the analog headstage, such as the refractory period and the threshold ( and ) for the signal-to-spike conversion of the ADM . While mismatch effect is generally a concern in modeling hardware designs based on software simulations, we show here that the mismatch among the silicon neurons resulted in a key feature for the implementation of our SNN architecture. This advantage allowed us to generate the normal distribution of parameters without manually defining the distribution of neuronal time-constants found in simulations or requiring extra memory to allocate these values.
By averaging over both time and the number of neurons recruited by the ensemble technique, the SNN network was able to achieve robust results: the accuracy obtained by the SNN are compatible with those obtained by state-of-the-art software algorithms implemented using complex algorithms on powerful computers 24 . Overall, the high specificity (100%) achieved with our system not only generalizes the value of the detected HFO by the SNN across different types of patients, but still holds true at the level of the individual patients, which is a prerequisite to guide epilepsy surgery that aims for seizure freedom.

Conclusions
This is the first feasibility study towards identifying relevant features in intracranial human data in real-time, on-chip, using event-based processors and spiking neural networks. By providing "neuromorphic intelligence" to neural recording circuits the approach proposed will lead to the development of systems that can detect HFO areas directly in the operation room and improve the seizure outcome of epilepsy surgery.

Design and setup of the hardware device
The CMOS circuit simulations were carried-out using the Cadence ® Virtuoso ADE XL design tools. All circuits including the headstage, the bias generator, and the silicon neurons were designed, simulated and analyzed in analog domain. The asynchronous buffers, spike routing network and chip configuration blocks were simulated and implemented in the asynchronous digital domain. The layout of the chip was designed using the Cadence ® Layout XL tool. The design rule check, layout versus schematic and post-layout extraction were performed using the Calibre tool. We packaged our device using a ceramic 240-pin quadratic flat package. The package was then mounted on an in-house designed six-layer printed circuit board. The programming and debugging of the System-on-Chip (SoC) was performed using low-level software and firmware developed in collaboration with SynSense Switzerland, and implemented using the XEM7360 FPGA (Opal Kelley, USA). The pre-recorded iEEG was fed to the chip using a Picoscope 2205A MSO (Picotech, UK). All frequency-domain measurements were performed using a Hewlett-Pacard 35670A dynamic signal analyzer.

Simulation and validation of the neural architecture
For the software simulation of the network we used the Spiking Neural Network simulator Brian2 58 and a custom made toolbox 49 that makes use of equations which describe the behavior of the neuromorphic circuits. To find the optimal parameters of the SNN, we were guided by the clinically relevant HFO marked by the Morphology Detector 24 : Around the HFOs marked in the iEEG 24 we created snippets of data ±25 ms. These snippets were used to select the parameters for the ADM and the SNN network (see Methods). The SNN architecture was validated using the previous generation of the neuromorphic processor DYNAP-SE 36 , for which a working prototyping framework is available. The high-level software-hardware interface used to send signals to the SNN, configure its parameters, and measure its output was designed in collaboration with SynSense AG, Switzerland.

Patient data
We included long-term iEEG recordings from 9 patients of a data set that is publicly available 32 . Patients had drug-resistant focal epilepsy as detailed in Table 1. Presurgical diagnostic workup at Schweizerische Epilepsie-Klinik included recording of iEEG from the medial temporal lobe. The iEEG data set has been analysed for HFO with state-of-the-art HFO detectors 23, 24 .
The surgical planning technique 20 was independent of HFO. Patients underwent resective epilepsy surgery at UniversitätsSpital Zürich. After surgery, the patients were followed-up for >1 year. Postsurgical outcome was classified according to the International League Against Epilepsy (ILAE): Class 1 Completely seizure free; no auras. Class 2 Only auras; no other seizures. Class 3 One to three seizure days per year; ± auras. Class 4 Four seizure days per year to 50% reduction of baseline seizure days; ± auras. Class 5 Less than 50% reduction of baseline seizure days to 100% increase of baseline seizure days; ± auras. Class 6 More than 100% increase of baseline seizure days.
In a previous publication 24 , we detected HFOs with the Morphology detector 24, 29 and compared the HFO area to the resected area to predict seizure outcome. The dataset with the HFO markings 32 is publicly available and was downloaded for the analyses presented here. The data consist of up to six intervals of approximately five minutes that were recorded in the same night during interictal slow-wave sleep, which promotes low muscle activity and high HFO rates. The intervals were at least three hours apart from epileptic seizures to eliminate the influence of seizure activity on the analysis. The amount of nights and intervals varied across patients (see Table 1). Because of the higher signal-to-noise ratio, in this study we focused on the recordings from the medial temporal lobe. Only the 3 most mesial bipolar channels were included in the analysis.

HFO detection
HFO detection was performed independently for each channel in each 5-min interval of iEEG. The signal preprocessing steps consisted of bandpass filtering, baseline detection and transforming the continuous signal into spikes using the ADM block. The ADM principle of operation is as follows: whenever the amplitude variation of the input waveform exceeds an upper threshold a positive spike on the UP channel is generated; if the change in the amplitude is lower than a threshold , a negative spike in the DN channel is produced. As the amplitude of the recordings changed dramatically with electrode, patient data and recording session, we introduced a baseline detection mechanisms that was used to adapt the values of the and thresholds in order to produce the optimal number of spikes required for detecting HFO signals while suppressing the background noise and outliers in the recordings (see Fig. 6). This baseline was calculated for each iEEG channel in software: during the first second of recording, the maximum signal amplitude was computed over non-overlapping windows of 50 ms. These values were then sorted and the baseline value was set to the average of the lowest quartile. This procedure excluded outliers on one hand, and suppressed the noise floor on the other hand. This procedure was optimal for converting the recorded signals into spikes.
Spikes entered the SNN architecture as depicted in Fig. 5bc. The SNN parameters used to maximize HFO detection were selected by analyzing the Inter-Spike-Intervals (ISIs) of the spike trains produced by the ADM and comparing their characteristics in response to inputs that included an HFO event versus inputs that had no HFO events. This analysis was then used to tune the time constants of the SNN output layer neurons and synapses. Specifically, the approach used was to rely on an ensemble of neurons in the output layer and to tune them with parameters sampled from a uniform distribution. The average time constant for the neurons was chosen to be 15 ms, with a coefficient of variation set by the analog circuit devise mismatch characteristics, to approximately 20%. Similarly, the excitatory synapse time constants were set in the range [3 6] ms and the inhibitory synapse time constants in the range [0.1 1] ms.
After sending the spikes produced by the ADMs to the SNN configured in this way, we evaluated snippets of 15 milliseconds output data produced by the SNN and signaled the detection of an HFO every time spikes were present in consecutive snippets of data. Outlier neurons in the hardware SNN that spiked continuously were considered uninformative and were switched off for the whole study. The activity of the rest of the neurons faithfully signaled the detection of HFOs (see Table tab:metrics). For the HFO count, spikes with inter-spike-intervals <15 ms were aggregated to mark a single HFO.

Post-surgical outcome prediction
To retrospectively 'predict' the postsurgical outcome of each patient in this data set, we first detected the HFOs in each 5-min interval by measuring the activity of the silicon neurons in the hardware SNN. We calculated the rate of HFO per recording channel by dividing the number of HFOs in the specific channel by the duration of the interval. Figure 6. Optimal spike generation threshold for the asynchronous delta modulator (ADM). (a) iEEG from 3 channels in one electrode. The different noise floors are captured by the different baseline levels of [5,8,13] V that we computed. (b) With the optimal channel-wise threshold, the number of UP and DN spikes is optimal for the example HFOs taken from each channel. (c) With a higher threshold (16 V), the number of UP and DN spikes is too low for the example HFOs. (d) With a lower threshold (1 V), the number of UP and DN spikes is too high for the example HFOs.

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The distribution of HFO rates over the list of channel defines the HFO vector. In this way we calculated an HFO vector for each interval in each night. We quantified the test-retest reliability of the distribution of HFO rates over intervals by computing the scalar product of all pairs of HFO vectors across intervals (Table 1). We then delineated the "HFO area" by comparing the average HFO rate over all recordings and choosing the area under the electrodes with HFO rates exceeding the 95 percentile of the rate distribution. Finally, to assess the accuracy of the patient outcome prediction, we compared the HFO area identified by our procedure with the area that was resected in surgery, and compared it with the postsurgical seizure outcome (Table 1).