90% yield production of polymer nano-memristor for in-memory computing

Polymer memristors with light weight and mechanical flexibility are preeminent candidates for low-power edge computing paradigms. However, the structural inhomogeneity of most polymers usually leads to random resistive switching characteristics, which lowers the production yield and reliability of nanoscale devices. In this contribution, we report that by adopting the two-dimensional conjugation strategy, a record high 90% production yield of polymer memristors has been achieved with miniaturization and low power potentials. By constructing coplanar macromolecules with 2D conjugated thiophene derivatives to enhance the π–π stacking and crystallinity of the thin film, homogeneous switching takes place across the entire polymer layer, with fast responses in 32 ns, D2D variation down to 3.16% ~ 8.29%, production yield approaching 90%, and scalability into 100 nm scale with tiny power consumption of ~ 10−15 J/bit. The polymer memristor array is capable of acting as both the arithmetic-logic element and multiply-accumulate accelerator for neuromorphic computing tasks.


Supplementary Tables
Supplementary Table 1 Truth table and operation methodology of a parallel 1-bit full adder   Logic Operation Full Adder

Supplementary Note 1: Synthesis and Characterization of Monomers and Polymers
All chemicals were purchased from Aldrich and used as received without further purification.
Organic solvents were purified, dried, and distilled under dry nitrogen. The compounds 1 and 2 were prepared according to the reported procedures, 1

Supplementary Note 2: UV-Visible Absorption Spectra of Polymers
The

Supplementary Note 5: In-memory Logic Computing with PBDTT-BQTPA Memristors
In the Au/PBDTT-BQTPA/ITO structured memristor devices, the Au top electrodes and the ITO bottom electrodes are defined as T1 and T2 terminals, respectively. The pulse voltages applied onto either T1 or T2 serve as the logic input signals, while the value of V T1 -V T2 determines the devices' states during resistive switching and logic operations. V 0 =0 V and V 1 =0.3 V, with the pulse width of 20 µs, are used as logic inputs "0" and "1" in the present study, while the OFF and ON states with the resistances of 100 Ω~200 Ω and 2.5 kΩ~3.5 kΩ are taken as the logic outputs of "0" and "1", respectively. The output logic (final resistance) state of the memristor can be readout by an additional independent read step with a small voltage pulse of 0.01 V (20 µs pulse width), and is stored directly in the same device non-volatilely.
Supplementary Figure 12 shows the experimental implementation of NAND, NOR, AND and OR operations, respectively. For the NAND operator, the PBDTT-BQTPA device is initially programmed to logic "1" with the resistance of 195 Ω in cycle 1, by setting the T1 and T2 inputs as "1" and "0", respectively. In cycle 2, the Au top electrode T1 is fixed as logic "0", and input q is applied onto the ITO bottom electrode T2. In cycle 3, T1 is fixed as logic "1" and input p is applied onto T2 (left panel of Supplementary Figure 13a). For the p and q input groups of "0, 0", "1, 0", "0, 1" and "1, 1", the final resistances of the polymer memristor are 114 Ω, 140 Ω, 127 Ω and 2678 Ω, respectively (middle panel of Supplementary Figure   13a). Being consistent with the truth table summarized in right panel of Supplementary Figure 13a, we confirm that the NAND function is implemented through these three-step operations.
For the NOR operation, the polymer memristor is first initialized to the logic state "1" with the resistance of 170 Ω in cycle 1, by setting the T1 and T2 inputs as "1" and "0", respectively.
In the subsequent cycles 2 and 3, the Au top electrode T1 is always fixed as logic "0", while the inputs q and p are applied onto the ITO bottom electrode T2, respectively (left panel of Supplementary Figure 13b). For the p and q input groups of "0, 0", "1, 0", "0, 1" and "1, 1", For the OR operator, the PBDTT-BQTPA device is first initialized to logic state "1" with the resistance of 166 Ω in cycle 1, during which the T1 and T2 inputs are taken as "1" and "0", respectively. In cycle 2, the ITO bottom electrode T2 is fixed as logic "1", and input p is ap-plied onto the Au top m electrode T1. In cycle 3, T2 is fixed as logic "0" and input q is applied onto T1 (left panel of Supplementary Figure 13d). For the p and q input groups of "0, 0", "1, 0", "0, 1" and "1, 1", the final resistances of the polymer memristor are 2548 Ω, 166 Ω, 162 Ω and 196 Ω, respectively (middle panel of Supplementary Figure 13d). These logic outputs are consistent with those shown in the truth table of the OR function, as summarized in right panel of Supplementary Figure 13d. The other logic functions of TRUE, FALSE, COPY p, NOT p, COPY q, NOT q, IMP, NIMP, RIMP and RNIMP can be implemented similarly within a single device of the present PBDTT-BQTPA memristor, as report in the literatures, 3,4 while the remaining XOR and XNOR has to be achieved by at least involving a pair of the anti-serially connected polymer devices. [5][6][7] Since the general implementation methodology of these Boolean logic operations are well documented in the references, we herein only show the experimental demonstration of the NAND, NOR, AND and OR gates that are utilized to construct the full adder circuits displayed in Figure 6, and skip the others for the avoidance of the necessary redundancies.

Supplementary Note 6: Modeling of the Polymer Memristor and Construction of Memristive Array
The polymer memristive device was mathematically modeled using verilog-A language. 8 The resistance value is constrained by the length and width of its corresponding conductive filament (CF), both of which are functions of the applied voltage and stressing time. The electrical properties of the devices were evaluated using Cadence spectre and the simulation is shown in Supplementary Figure 18. Then a bit-cell consisting of the present polymer memristor device and a 180 nm N-metal-oxide-semiconductor (NMOS) transistor from the Semiconductor Manufacturing International Corporation (SMIC) was constructed, after which a 64×64 memristive array was able to be built on the basis of the bit-cells. Note that in order to be electrically compatible with the NMOS transistor obtained from SMIC, the device current of the 400×400 µm 2 PBDTT-BATPA memristor is proportionally reduced to that of a 400×400 nm 2 device according to Figure 3k.

Supplementary Note 7: Binary MAC (XNOR) Operation in Memristive Arrays
In binary neural networks, the Multiply-and-Accumulate (MAC) operation can be reduced to XNOR operation. 9 Both weights and input features are constrained to +1 or -1 for convenience in our cases. The weights of a binarized layer in LetNet-5 are stored in memristive arrays, while the input features should be applied sequentially. Each 1-bit XNOR can be accomplished using two bit-cells, wherein the two polymer devices store the weight and the states of the NMOS transistors' gates represent the input features, as depicted in Figure 6b.
We assume a value of "+1" is stored when the upper polymer (M u ) device is in LRS while the lower (M l ) one is in HRS. On the contrary, a "-1" is stored. Similarly, a "+1" will be input if the upper transistors' gate is open and the lower is close, vice versa. The XNOR result can be represented by the output current, with low current representing "+1" and high current standing for "-1". Subsequently, the accumulated current across the long bit-line is to be used as the summation of all the XNOR results according to the Kirchhoff's current law (KCL). Finally, an analog-to-digital converter (ADC) is used to convert the accumulated current to digital signals.