A superconducting switch actuated by injection of high-energy electrons

Recent experiments with metallic nanowires devices seem to indicate that superconductivity can be controlled by the application of electric fields. In such experiments, critical currents are tuned and eventually suppressed by relatively small voltages applied to nearby gate electrodes, at odds with current understanding of electrostatic screening in metals. We investigate the impact of gate voltages on superconductivity in similar metal nanowires. Varying materials and device geometries, we study the physical mechanism behind the quench of superconductivity. We demonstrate that the transition from superconducting to resistive state can be understood in detail by tunneling of high-energy electrons from the gate contact to the nanowire, resulting in quasiparticle generation and, at sufficiently large currents, heating. Onset of critical current suppression occurs below gate currents of 100fA, which are challenging to detect in typical experiments.

Measurements of the gate current I G , flowing between gate and nanowire channel were obtained with a Keysight B2902A source-measure unit and processed by the numerical technique described below. The source-measure unit applied a voltage V G to the gate contact and read the current I G flowing into the setup. An example of an I G vs. V G curve measured with this technique, referred to as Method 1, is shown in Fig. 1 (green dots). When measuring with Method 1, we describe the DC current flowing into the electrical setup as sum of two components: the current that actually flows into the gate electrode and reaches the nanowire, and the current that is lost before reaching the gate by spurious leakage paths present in the cryostat. The first current component is expected to depend exponentially on V G , the second was found to be approximately linear. That is, for small gate voltages, the current flowing to spurious paths and not reaching the gate voltage is dominating. The following numerical procedure was applied to extract the current contribution that actually reaches the nanowire. First, a current off- set related to the measurement device is subtracted from the data (typically within ±5 pA), so that I G = 0 for V G = 0. Second, a line is fit to the experimental I G (V G ) curve for small values of V G (dotted black line in Fig. 1). Third, the obtained line is subtracted from the experimental curve in the entire V G range, resulting in the red triangles in Fig. 1. This procedure typically results in gate currents which are within the noise level of our setup at low V G , and then increase exponentially at large V G . The linear component that we subtracted corresponds to a resistance of about 1 TΩ. Testing different parts of our setup individually showed that this spurious resistance is predominantly associated with the low frequency twisted pair wires that bring the signal from room temperature to the mixing chamber stage, and is present also when no device is connected. In our experience, such a high value of resistance to ground is indicative of a good DC measurement setup.
To verify the validity of this numerical procedure, we measured the current with a second technique, referred to as Method 2. In Method 2, all contacts to the nanowire channel are left floating except for one, which is grounded via a low impedance IV converter (Basel Physics SP 983, with feedback resistance set to 1 GΩ). The gate current I G injected into the nanowire channel flows into the IV converter and gives rise to voltage output of I G × 1 GΩ. The current I G simultaneously measured with Method 2 is also shown in Fig. 1 (blue squares) and is essentially identical to that processed with the numerical technique described above. Adopting Method 2 throughout this work would however not be possible, as the large sourcedrain currents needed to reach the critical current would result in overloading of the IV converter. For example, the current to voltage gain of 1 GΩ allows for a maximum input current of 10 nA, while typical source-drain critical currents extend up to 200 µA. Operating with lower current-to-voltage conversion gain, such as 100 kΩ, would not provide enough resolution to detect small gate currents. Figure 2 of the Main Text shows the critical current I C as a function of gate voltage V G for the device of Fig. 1 of the Main Text measured at various temperatures and fields. In Fig. 2(a) and (b) we show the simultaneously measured gate currents I G . Data indicate that I G is unaffected by both temperatures and magnetic fields.

SUPPLEMENTARY NOTE 3: MEASUREMENT OF A DEVICE WITH LARGE GATES
Data shown in the Main Text was obtained on nanowires where gates were relatively narrow (of the order of 100 nm or less) and terminated with a sharp tip. In Fig. 3 we present measurements obtained on a nanowire as that of Fig. 1(a) of the Main Text, but with 2 µm wide gates. A false-colored scanning electron micrograph of the device is shown in Fig. 3(a), together with the measurement setup. The nanowire is colored in blue and the two gates in red. The gates are separately operated with gate voltages V G1 and V G2 , respectively. The response to a source-drain current was characterized in Fig. 3(b) by sweeping I SD up from the resistive state. As for the wire in Fig. 1(a) of the Main Text, the critical current was I C = 47 µA and the retrapping current I R = 1 µA. The source-drain critical current I C as a function of gate voltage V G1 is shown in Fig. 3(c), with the corresponding gate current I G1 shown in Fig. 3(d). Equivalent measurements performed as a function of gate voltage V G2 are shown in Figs. 3(e) and (f). For both V G1 and V G2 , full suppression of I C was reached at about ±4 V, corresponding to gate currents of about ±1 nA.

SUPPLEMENTARY NOTE 4: TIME-RESOLVED MEASUREMENTS
Here we present time-dependent measurements, indicating fast switching operation as a function of V G and the ability of the device to self-reset from normal to superconducting state. A schematic of the electrical setup used for those measurements is shown in Fig. 4(a), which allows for the simultaneous application of low frequency and high frequency signals (colored blue and red, respectively). The device was mounted on a sample holder with Supplementary Figure 4. High frequency measurements. a Schematic measurement setup for the high frequency experiment presented in Fig. 5 of the Main Text. The dashed box divides the 10 mK (inside) and room temperature (outside) apparatus. Lines for low and high frequency signals are indicated in blue and red, respectively. Low temperature bias-Ts with components RT and CT were connected to the four leads of the wire and a side gate. Low frequency cables were filtered by low-pass (LP) filters. Symmetric application of low frequency voltage ±VSD/2 results in the flow of a current ISD. Fast signals Vin and Vout are applied and recorded, respectively, thorough 50 Ω ports. b Frequency dependent Vout/Vin signal measured with the nanowire in the superconducting state (orange), in the normal state as a consequence of a large source-drain current (blue), and in the normal state as a consequence of a large gate voltage (green).
resistive bias-Ts (resistance R T = 50 kΩ and capacitance C T = 22 nF). The low frequency lines (resistive twisted pairs) passed through RC low pass filters on the sample holder (LP in Fig. 3(a)) and additional RC filters and high frequency pi-filters at the mixing chamber level (not shown), resulting in an additional line resistance R L = 2.5 kΩ. A voltage bias V SD , symmetrically applied between two low frequency inputs, resulted in a sourcedrain current of approximately I SD = V SD /(2R T + 2R L ). Application of a symmetric bias ensured the nanowire potential was constant with respect to the gate potential as I SD varied. Low frequency voltage signals V + and V − were used to calculate the nanowire four terminal resistance as R = (V + − V − )/I SD .
The device transmission was measured via a lock-in amplifier (Zurich Instruments UHFLI, with input and Supplementary Figure 5. Fast switching in a metallic nanowire. a Time-dependent switching characteristics of a device as that of Fig. 1(a) of the Main Text as a function of DC gate voltage V G. A 100 kHz square wave with peak-topeak amplitude of 1 V was added to V G. b Gate current IG as a function of V G measured simultaneously to the data in (a). c Line-cut of the data in (a) for V G = 6.7 V (see red line). d Zoom-in of the data in (c) in proximity to a normal to superconducting state transition. Dashed vertical lines indicate the 10% to 90% amplitude transition, corresponding to 90 ns. This value is limited by the measurement bandwidth of the setup in use and serves as upper limit for the device switching time.
Demonstration of selfresetting. Switching operation as a function of the DC source-drain current ISD. Self-resetting was possible for ISD values smaller than the nanowire retrapping current. output set to 50 Ω impedance.) by applying a voltage V in through a −80 dB attenuator (A) and recording the resulting voltage V out . The ratio V out /V in is shown in Fig. 4(b) as a function of frequency f for three situations. In orange is the situation where the wire was superconducting, meaning I SD = 0 and V G = 0. In blue is the situation in which the wire was turned normal by means of a DC current I SD = 60µA, larger than the nanowire critical current I C = 50 µA. In green is the situation in which the nanowire was turned normal by the application of a DC gate voltage V G = 8V. As expected, for sufficiently high frequency the device transmission in the superconducting state approaches unity. Deviations however occur at specific frequencies, presumably due to the fact that the device was not designed to operate at high frequencies. Measurements shown below were performed at a frequency of 250 MHz.
Using the low temperature bias-Ts, a square wave signal was superimposed to the low frequency gate voltage V G . The ratio between the transmitted voltage V out and the voltage input to the measurement setup V in is shown in Fig. 5(a) as a function of time t and V G , with the timeaveraged gate current shown in Fig. 5(b). Clear switching operation was achieved within a 500 mV interval around V G = 6.7 V, corresponding to a gate current of 1 nA. Figure 5(c) shows a line cut of Fig. 5(a) for V G = 6.7 V, demonstrating fast and reproducible switching between two impedance states. A zoom-in close to a rise point is shown in Fig. 5(d), with dashed lines marking the transition between 10% and 90% of the step height, which takes place in 90 ns (similar results are obtained for the decay time). Such transient equals three times the time constant of the lock-in amplifier used for these measurements (30 ns) and is taken as the shortest switching time measurable with the setup in use, and as the upper limit for the device response time. Future work will take advantage of samples specifically designed for microwave measurements [1] and correlation techniques [2] to test the ultimate switching speed of the device.
Our superconducting switch has the remarkable property to operate without the need of a DC current I SD flowing in it. Measurements shown in Fig. 5 were obtained with I SD = 0, where latching mode is not required. As expected, similar behavior was obtained for |I SD | smaller than the retrapping current I R (I R = 1.1 µA in the present device). Figure 6 demonstrates switching operation as a function of I SD . For |I SD | < 1 µA clear and fast switching operation was obtained, without the need of self-resetting the device at every gate cycle. On the contrary, for |I SD | > I R no switching was observed.