Benchmarking monolayer MoS2 and WS2 field-effect transistors

Here we benchmark device-to-device variation in field-effect transistors (FETs) based on monolayer MoS2 and WS2 films grown using metal-organic chemical vapor deposition process. Our study involves 230 MoS2 FETs and 160 WS2 FETs with channel lengths ranging from 5 μm down to 100 nm. We use statistical measures to evaluate key FET performance indicators for benchmarking these two-dimensional (2D) transition metal dichalcogenide (TMD) monolayers against existing literature as well as ultra-thin body Si FETs. Our results show consistent performance of 2D FETs across 1 × 1 cm2 chips owing to high quality and uniform growth of these TMDs followed by clean transfer onto device substrates. We are able to demonstrate record high carrier mobility of 33 cm2 V−1 s−1 in WS2 FETs, which is a 1.5X improvement compared to the best reported in the literature. Our experimental demonstrations confirm the technological viability of 2D FETs in future integrated circuits. Here, the authors perform a benchmark study of field-effect transistors (FETs) based on 2D transition metal dichalcogenides, i.e., 230 MoS2 and 160 WS2 FETs, and track device-to-device variations to gauge the technological viability in future integrated circuits.

T wo-dimensional (2D) semiconducting materials beyond graphene 1,2 are receiving increasing attention owing to their ultra-thin body nature that can mitigate detrimental short-channel effects in aggressively scaled devices through improved electrostatics, enabling them to replace or complement the aging Si technology [3][4][5] . Molybdenum disulfide (MoS 2 ) and tungsten disulfide (WS 2 ), belonging to the family of transition metal dichalcogenides (TMDs), have been studied extensively in this context. In fact, high performance MoS 2 field-effect transistors (FETs) with a contact pitch of 70 nm and 42 nm have already been experimentally demonstrated 6,7 . Circuit level implementations of 2D FETs such as inverters, logic operators, ring oscillators, and radio-frequency devices have also been achieved 8-12 . Recently, a microprocessor based on MoS 2 FETs was reported 13 . Additionally, 2D FETs have found applications in various emerging technologies such as sensors for internet of things, neuromorphic computing, biomimetic devices, valleytronics, straintronics, and optoelectronic devices [14][15][16][17][18][19][20][21] . While initial demonstrations of prototype devices relied on exfoliated flakes, the 2D community has rapidly transitioned towards the growth of large-area films to address manufacturing needs for any commercial applications. In this context, chemical vapor deposition (CVD) 22,23 and metal-organic CVD (MOCVD) 7,24 are the most promising techniques, enabling growth of high quality 2D materials with different thermal budgets on various substrates. In fact, there are several reports demonstrating high-performance FETs based on CVD and MOCVD grown monolayer MoS 2 and WS 2 . However, most of these studies are based on one or only a few devices.
To assess the potential of 2D materials for future very large scale integrated (VLSI) circuits, it is important to study the variation in key device parameters that determine the ON-state and OFF-state performance across a large number of devices. Unfortunately, there are only a few studies that report device-todevice variation in 2D FETs 7 26 . However, both works concentrate on longer channel devices where the effects of contact resistance are not pronounced. In a separate study, Smithe et al. 22 measured scaled MoS 2 FETs based on synthetic monolayers; however, they did not provide any statistics. Smets et al. 7 demonstrated the most significant study on scaling of CVD grown monolayer MoS 2 , wherein multiple devices with channel lengths ranging from 5 μm down to 29 nm were measured. However, their study was focused on the OFF-state performance. Finally, all of the aforementioned studies are based on MoS 2 FETs, and none exist for WS 2 FETs.
This work focuses on a comprehensive study of variation in key parameters related to both OFF-state and ON-state performance, such as threshold voltage, subthreshold slope, ratio of maximum to minimum current, field-effect carrier mobility, contact resistance, drive-current, and carrier saturation velocity, for different channel lengths ranging from 5 μm down to 100 nm using 230 MoS 2 FETs and 160 WS 2 FETs. In addition, we offer extensive benchmarking of our devices with respect to the abovementioned demonstrations as well as ultra-thin body (UTB) silicon (Si) on insulator (SOI) FETs with similar gate lengths to assess the technological viability and maturity of 2D FETs. Using statistical measures such as mean, median, standard deviation, and minimum/maximum values, we show low device-to-device variation. We are also able to demonstrate record high carrier mobility of 33 cm 2 V −1 s −1 in WS 2 FETs, which is a 1.5X improvement compared to the best reported in the literature. We attribute our accomplishments to the epitaxial growth of highly crystalline 2D monolayers on sapphire substrate via MOCVD technique at 1000°C using chalcogen and sulfur precursors that minimize carbon contamination in the film, as well as to the clean transfer of the film from the growth substrate to the device fabrication substrate.

Results
Synthesis and characterization of monolayer MoS 2 and WS 2 . MoS 2 and WS 2 were deposited by MOCVD on epi-ready 2″ diameter c-plane sapphire wafers. Figure 1 summarizes the growth, structural, and optical characterization of the MOCVD grown MoS 2 and WS 2 . Figure 1a shows the schematic of the MOCVD system, comprising of a cold-wall horizontal reactor with an inductively heated graphite susceptor equipped with wafer rotation as previously described 27 . Molybdenum hexacarbonyl (Mo(CO) 6 ) and tungsten hexacarbonyl (W(CO) 6 ) were used as metal precursors, while hydrogen sulfide (H 2 S) was the chalcogen source with H 2 as the carrier gas. MoS 2 was deposited in a single step process at 1000°C, where coalesced monolayer growth across the 2″ wafer was achieved in 18 min. WS 2 was deposited using a multi-step process with nucleation at 850°C and lateral growth at 1000°C, resulting in coalesced monolayer growth across the 2″ wafer in 10 min 28 . In both cases, after growth the substrate was cooled in H 2 S to 300°C to inhibit decomposition of the MoS 2 and WS 2 films. Figure 1b shows uniformly grown MoS 2 and WS 2 films over 2″ sapphire wafers. Further growth details can be found in the "Methods" section. The morphology of the monolayer films at the center and edge of the 2″ wafer is shown in Fig. 1c, d for MoS 2 and WS 2 , respectively, using atomic force microscopy (AFM). Height profiles obtained from scratch testing confirm monolayer film formation (see Supplementary Fig. 1a, b). The monolayers are fully coalesced, with undulations arising from steps on the sapphire surface. The overall bilayer density is low but a higher density of bilayers is present at the center of the MoS 2 film compared to the WS 2 film. The in-plane X-ray diffraction (XRD) patterns in Fig. 1e, f highlight the epitaxial relation between the sulfide monolayers and the underlying sapphire substrates. The fullwidth at half maxima of the ϕ-scan peaks are 0.3°and 0.17°for MoS 2 and WS 2 , respectively, indicating a low rotational misorientation of domains within the monolayers. The films were transferred to Al 2 O 3 /Pt/TiN/p ++ -Si substrates for device fabrication, as discussed later. The transferred film quality was assessed using Raman maps as shown in Fig. 1g, h, and photoluminescence (PL) maps as shown in Fig. 1i, j, for MoS 2 and WS 2 , respectively. Raman maps show less than 5% variation in the representative A 1g peak position. The uniform PL peak positions observed at 1.84 eV for MoS 2 and 1.97 eV for WS 2 correspond to their monolayer response. Representative Raman and PL spectra are included in the Supplementary Fig. 1c-f.
Monolayer MoS 2 and WS 2 device fabrication and characterization. To investigate the electrical properties of the MOCVD grown TMD films, back-gated FETs were fabricated on Al 2 O 3 /Pt/ TiN/p ++ -Si substrates. 50 nm Al 2 O 3 gate dielectric was deposited using atomic layer deposition (ALD). The choice of a thin, high-k gate dielectric with an effective oxide thickness (EOT) of 22 nm, compared to conventionally used 300 nm SiO 2 , was to allow for better gate electrostatics. The Pt/TiN/ p ++ -Si stack acts as the gate electrode (see "Methods" section for more details on gate dielectric fabrication) for each substrate. The TMD films were transferred from sapphire (growth substrates) onto the Al 2 O 3 substrates via the poly(methyl methacrylate) (PMMA)-assisted wet-transfer process 29 , as shown in Fig. 2a (see "Methods" section for more details on transfer of monolayer films). Following transfer, electron beam (e-beam) lithography and dry etching using SF 6 plasma were used to isolate the channel area of each device. Next, transmission line measurement (TLM) structures were defined using another set of e-beam exposures. Finally, ebeam evaporation was performed to sequentially deposit 40 nm Ni and 30 nm Au to serve as the contacts for the FETs (see "Methods" section for more details on device fabrication). The TLM structures were designed to have channel lengths (L CH ) of 100 nm, 200 nm, 300 nm, 400 nm, 500 nm, 1 μm, 2 μm, 3 μm, 4 μm, and 5 μm, while the channel width (W) was kept constant at 5 μm. Figure 2b, c, respectively, show the schematic and scanning electron microscope (SEM) image of the fabricated TLM structures. Figure 2d-g show the transfer characteristics, i.e., drain current (I DS ) versus gate voltage (V GS ), for different drain voltages (V DS ) in linear and logarithmic scales for representative longest-channel length (L CH = 5 μm) and shortest-channel length (L CH = 100 nm) FETs, for both MoS 2 and WS 2 . Strong n-type conduction is observed due to Fermi-level pinning of the contact metal close to the conduction band of both MoS 2 and WS 2 30 . Figure 2h-k show the corresponding output characteristics, i.e., I DS versus V DS , for different V GS . Measurement protocols are described in the "Methods" section.
Device-to-device variation in monolayer MoS 2 and WS 2 FETs. To understand the variation in the FET performance across the entire 1 × 1 cm 2 substrates, as well as to study of the impact of channel length scaling on FET performance, 230 MoS 2 FETs (23 TLM structures) and 160 WS 2 FETs (16 TLM structures) were measured. Figure 3a, b display the transfer characteristics of all measured MoS 2 and WS 2 FETs, respectively, for different L CH , which were used to extract key device parameters. For each parameter, the mean, median, standard deviation, minimum, and maximum values are reported. Finally, median values are used for benchmarking since they reflect the central tendency, even in the presence of outliers in the data, and offer higher accuracy in case of skewed distributions. Devices with the best number for a given parameter are termed as "champion" devices.
Threshold voltage. Threshold voltage is extracted using three different methods: linear extrapolation (V t lin ), Y-function (V t Y ), and constant-current method (V t cc ). Supplementary Fig. 2a-c describes the extraction of V t lin , V t Y , and V t cc , Supplementary  Table 1 summarize the device-to-device variations. It was found that the threshold voltage is independent of the channel length for both MoS 2 and WS 2 FETs. Figure 4a, b show the distributions of V t lin for all measured MoS 2 and WS 2 FETs, respectively. Median V t lin of 2.9 V with a standard deviation of σ V t = 0.8 V is obtained for MoS 2 , and median V t lin of 6.4 V with a σ V t = 0.8 V is obtained for WS 2 . Threshold voltage was found to be more positive for WS 2 FETs compared to MoS 2 FETs, which can be attributed to higher intrinsic n-type doping of MoS 2 either due to the specific nature of the impurity present in the MOCVD grown MoS 2 film or due to surface charge transfer induced Variation in threshold voltage is widely used for benchmarking emerging devices based on novel materials 25 . Note that median V t lin depends on the work function of the gate metal and unintentional/intrinsic doping of the 2D material and that both V t lin and σ V t depend on the thickness of the gate oxide. Hence for a fair comparison we use Sσ V t , which is defined as the projected threshold voltage variation at a scaled effective oxide thickness (SEOT) obtained using Eq. (1). We use SEOT = 0.9 nm for comparison with other literature results.
This equation assumes linear scaling of variation in threshold voltage with respect to the EOT. However, for ultra-scaled devices, deviation from the linear scaling can be expected due to increased effect of metal-gate granularity 32 . For our MoS 2 and WS 2 FETs, we project Sσ V t = 33 mV, which is similar to the value projected for CVD grown monolayer MoS 2 FETs reported by Smithe et al. 25 . We also employed this method to other reports on top-gated and wafer-scale monolayer MoS 2 FETs and extracted Sσ V t = 45 mV for 26 and Sσ V t = 11 mV for 12 , respectively. Recently, Smets et al. 7 have demonstrated σ V t = 44 mV for an EOT of 1.9 nm that would correspond to Sσ V t = 20 mV for monolayer MoS 2 FETs with channel lengths scaled down to 30 nm. These results are compared with the state-of-the-art UTB SOI and Si FinFET (Table 1). Channel dimensions are included in Table 1 since σ V t has been found to be inversely proportional to the channel area in ultra-scaled devices which is shown using Pelgrom plots 32,33 . However, we did not observe such a trend due to relatively large channel areas in our MoS 2 and WS 2 FETs. It is encouraging that monolayer 2D FETs show Sσ V t comparable to the state-of-the art Si FETs in spite of an order of magnitude smaller body thickness. Note that UTB Si FETs are expected to encounter challenges associated with the precise thickness control, random dopant fluctuations, and detrimental quantum confinement effects beyond 5 nm body thickness 34,35 , which are unlikely for 2D monolayers. At the same time further improvement in threshold voltage variation can be achieved for 2D FETs through optimization of the monolayer growth and improvement in the fabrication process flow (see Supplementary Note 2 for further discussion). Hence, 2D materials offer an alternative for the realization of UTB MOSFETs. The exhibition of low deviceto-device variation in this work, which can be attributed to uniform and contaminant-free MOCVD growth of monolayer TMDs and clean device fabrication process can accelerate the incorporation of 2D FETs in future VLSI technologies.    Table 2 summarizes the device-to-device variation in SS. For a FET with ohmic contacts, it is expected that SS 1 = SS 2 = SS 3 = SS 4 . However, for a Schottky barrier (SB) FET, the SS may increase when extracted for higher orders of magnitude change in I DS . A greater increase can be attributed to higher SB height at the metal/semiconductor interface, which not only limits the ONcurrent but also impacts the OFF-state performance. In the existing 2D FET literature there is a tendency to report SS value without mentioning the orders of magnitude change in I DS over  which it is evaluated. This leads to considerable discrepancy and unfair comparisons. In fact, most SS values are reported for only one or two orders of magnitude of the drain current, whereas circuit operations require at least four orders of magnitude ON/ OFF ratio to be technologically relevant.
We found that the median SS values are independent of L CH for both MoS 2 and WS 2 FETs ( Supplementary Fig. 3a, b).  Table 2). However, no significant difference is found in the standard deviation values for SS 1 and SS 4 . Note that the "champion" MoS 2 FET demonstrates SS 1 = 93.3 mV.dec −1 and SS 4 = 166 mV.dec −1 , and the "champion" WS 2 FET demonstrates SS 1 = 295.6 mV.dec −1 and SS 4 = 452.8 mV.dec −1 . The deviation of SS from its ideal value of 60 mV.dec −1 even for "champion" devices can be explained using Eq. (2).
Here, k B is the Boltzmann constant, T is the temperature, q is the electronic charge, m is the body factor, C S is the semiconductor capacitance, C IT is the interface trap capacitance, C OX is the oxide capacitance, and D IT is the interface trap density. For fully depleted UTB FETs such as monolayer MoS 2 and WS 2 FETs, C S = 0. In case of a clean oxide-semiconductor interface, C IT ( C OX , ensuring that m = 1 and SS = 60 mV.dec −1 . Clearly, in our MoS 2 and WS 2 FETs, m > 1 indicates the presence of interface traps at the 2D/ dielectric interface (finite value of C IT ).

Interface traps.
To evaluate the quality of the interface, we have extracted D IT using Eq. (2) and the corresponding distributions are shown in Fig. 4e 38,39 . In addition, photoresist residue from the lithography and/or the wet transfer process can cause an increase in D IT . Therefore it is possible to reduce D IT through further optimization of growth, post-growth processing, and improvement in fabrication process flow.
Current ON/OFF ratio. Fig. 4g, h show the distribution of the ratio of maximum to minimum current (I max /I min ) across all MoS 2 and WS 2 FETs, respectively. Here, I max is the maximum current obtained from the transfer characteristics for V DS = 1 V and I min is the average noise floor. Note that the true device current in the OFF-state is beyond the measurement range of the instrument. See Supplementary Fig. 4a, b for the distribution of I max and I min , Supplementary Fig. 4c, d for the distribution of I max /I min for different L CH for MoS 2 and WS 2 FETs, and Supplementary Table 3 for a summary of device-to-device variation in I max /I min . The median and standard deviation for I max /I min were found to be 2.1 × 10 7 and 5.5 × 10 7 for MoS 2 FETs and 2.1 × 10 7 and 2.6 × 10 7 for WS 2 FETs. These values are over an order of magnitude higher than the I max /I min of 1.3 × 10 6 for UTB Si MOSFETs 36 . I max /I min is benchmarked against literature reports for L CH = 100 nm as shown in Supplementary Table 4. Note that the key OFF-state performance indicators, i.e., threshold voltage, SS, D IT , and I max /I min , are mostly found to be independent of L CH . Even for L CH = 100 nm, no detrimental short-channel effects are observed, which is expected and can be ascribed to the atomically thin body nature of monolayer TMDs, as well as the use of thin and high-k Al 2 O 3 as the gate dielectric with EOT = 22 nm.
Field-effect mobility and contact resistance. Field-effect mobility (μ FE ) is an important device parameter that strongly influences the ON-state performance of a FET. While intrinsic mobility is a material related parameter, μ FE is determined by extrinsic effects, such as contact resistance (R c ), and often depends on how it is extracted from the device characteristics. Three popular methods for extracting μ FE are peak transconductance (μ g m ), Y-function (μ Y ) 40 , and TLM (μ TLM ) as described in Supplementary Note 3. Figure 5a, b, show the distribution and the corresponding median values for μ g m as a function of L CH for MoS 2 and WS 2 FETs, respectively. Additionally, 25th and 75th percentile values of the distribution are also marked. Clearly, μ g m shows a strong L CH dependence, with the median value varying from 23.9 cm 2 V −1 s −1 to 3.6 cm 2 V −1 s −1 for MoS 2 and 29 cm 2 V −1 s −1 to 2.7 cm 2 V −1 s −1 for WS 2 as the devices are scaled from L CH = 5 μm down to L CH = 100 nm. Supplementary Fig. 5a, b shows a similar analysis of μ Y for MoS 2 and WS 2 FETs, respectively and Table 1 Benchmarking device-to-device variation in threshold voltage.  Table 5 summarizes the device-to-device variation in μ g m and μ Y . Both μ g m and μ Y extracted from shorter-channel devices show significant reduction in their median values, indicating the dominant role of R c in scaled 2D FETs 6 . The contact resistance is seen as a result of Fermi-level pinning at the metal/TMD contact interface, resulting in a finite SB height 30 . To investigate further, we used the TLM structure shown in Fig. 2c to extract R c and evaluate its impact on L CH scaling as shown in Fig. 5c-f. We used Eq. (3) to extract R c .
Here, R T is the total measured resistance of the FET, and R ch is the channel resistance, which is directly proportional to L CH and inversely proportional to the carrier density (n S ) when the FET is measured in the linear operation regime. However, R c is independent of L CH and hence can be extracted from the y-intercept of R T versus L CH plots, as shown in Fig. 5c, d for MoS 2 and WS 2 , respectively, for different n S 41 (see Supplementary Note 4 for further discussion on the extraction of n S ). Figure 5e, f show the distribution of corresponding extracted R c as a function of n S . A steady decrease in R c with increasing n S is attributed to the phenomenon of contact-gating in global back-gated FET geometry, since the SB width at the metal/2D interface is modulated by the back-gate voltage 30 . Lower SB width allows for easier carrier tunneling, reducing R c . For the MoS 2 FET, the median R c value was found to be 9.2 kΩ−μm, corresponding to n S = 1 × 10 13 cm −2 . However, for WS 2 , n S was limited to 4.4 × 10 12 cm −2 , owing to the more positive V t lin , resulting in a higher median R c = 29.2 kΩ−μm. For a case of identical carrier concentration, n S = 2.7 × 10 12 cm −2 , similar median R c values of 33 kΩ−μm and 39.4 kΩ−μm are obtained for MoS 2 and WS 2 , respectively. The difference in R c between MoS 2 and WS 2 can be explained from the fact that the charge neutrality level is closer to the conduction band for MoS 2 than it is for WS 2 , resulting in a higher SB height at the Ni/WS 2 contact interface compared to the Ni/MoS 2 contact interface 42 . The relative effect of R c is assessed for different L CH . Figure 5g, h show the contribution of R c and R ch to the total resistance R T using stacked bar plots as a function of L CH for MoS 2 and WS 2 , respectively. It is clear that for L CH ≤ 1 μm, the contact effects are significant since 2R c > R ch . This explains why the extracted μ g m is L CH dependent and is severely underestimated by more than 80% for both MoS 2 and WS 2 when extracted from scaled devices with L CH = 100 nm. Since μ g m extraction is limited by R c , extracting μ TLM following Eq. (3) is more appropriate for short channel devices. Supplementary Fig. 5c, d show the distribution of μ TLM  5 Device-to-device variation in field-effect mobility and contact resistance. Distribution of mobility extracted using peak transconductance (μ g m ) for different channel lengths for a MoS 2 and b WS 2 FETs. Median, 25th percentile, and 75th percentile is also denoted. Total resistance (R T ) versus L CH for c MoS 2 and d WS 2 for different carrier concentrations (n S ) extracted using a representative TLM structure. The distribution of contact resistance (R c ) across multiple TLM structures, extracted from the y-intercepts in c and d, as a function of n S for e MoS 2 and f WS 2 , respectively. The relative contribution of R c and channel resistance (R ch ) to the total resistance for g MoS 2 and h WS 2 for different L CH . In scaled devices, as R ch scales with the channel length, the contribution of R c (note that R c is independent of L CH ), i.e., 2R c /R T , is more significant compared to R ch , i.e., R ch /R T .   Table 3 shows the benchmarking of our "champion" devices with the best reports from the literature using μ FE (μ g m for longer channel devices and μ TLM for shorter channel devices) and R c for both MoS 2 and WS 2 . We have also included median/mean values wherever applicable. Note that while higher μ FE values have been reported based on "champion" exfoliated and CVD grown MoS 2 FETs 7,12,24,25,44-46 , our report is statistically more significant as it demonstrates variation across multiple TLM structures. For WS 2 , μ FE = 33 cm 2 V −1 s −1 is the highest reported, 1.5X better than the previous report on synthetic WS 2 47 . Higher μ FE values reported for WS 2 are either for exfoliated materials at room temperature 48 and low temperatures 49 , or for CVD grown materials with contact engineering via the use of multilayer graphene as interlayers 50 . More interestingly, UTB Si MOSFETs with 0.9 nm thick Si show μ FE ≈ 6 cm 2 V −1 s −151 , which is more than 2 orders of magnitude smaller compared to bulk Si mobility and is primarily attributed to thickness fluctuation in UTB Si.
Metal/2D contact resistances are comparatively high even for the "champion" devices with R c = 3 kΩ−μm and R c = 2.1 kΩ−μm for MoS 2 and WS 2 , respectively, when compared to the R c = 0.1 kΩ−μm typically reported for state-of-the-art Si FETs. However, various methods have been developed to reduce the effect of SB-limited carrier transport in 2D TMDs 52 , such as work function engineering to reduce the SB height 30 , introduction of interlayers such as graphene to decouple the metal/2D interface to alleviate Fermi-level pinning 53,54 , and achieving higher carrier concentration underneath or near the metal/2D contacts through substitutional or surface charge transfer doping to reduce the SB width 42,55 . Nevertheless, our MOCVD grown monolayer MoS 2 FETs demonstrate R c similar to values reported in the literature 7,22,25,56 . The "champion" devices are benchmarked in Table 3. To the best of our knowledge, this is the first report of R c for synthetic WS 2 . Additionally, our work marks the first study on the extraction of contact resistance from multiple TLM structures for both MoS 2 and WS 2 . Smithe et al. 25 have demonstrated a pseudo-TLM analysis where independent devices with different channel lengths and widths were used to extract the distribution of R T . TLM analysis is done on the devices between 10th and 90th percentile 25 . Our demonstration involves the extraction of contact resistance from separate TLM structures and finding the variation across these TLM structures, and the analysis is not limited to a percentile limit.
Drive-current and saturation velocity. Finally, high performance FETs are benchmarked using the drive current (I ON ) that is achievable for a given supply voltage (V DS = V DD ). Higher values of I ON ensure faster circuit operation as the intrinsic delay of a FET is proportional to CV DD /I ON , where C is the load capacitance. In digital electronics, higher I ON allows larger fan-out. Figure 6a, b display the output characteristics of MoS 2 and WS 2 FETs, respectively, for different channel lengths, which were used to assess the ON-state performance of the devices. At high biases, high current density leads to self-heating, resulting in negative differential resistance (NDR) behavior. This is a common phenomenon seen in ultra-thin body FETs, including SOI FETs 57 , nanowire FETs 58 , graphene FETs 59 , and, more recently, exfoliated multilayer MoS 2 FETs 60 and CVD grown monolayer MoS 2 FETs 61 . It is possible to reduce or eliminate the self-heating effect through pulsed measurements with pulse widths less than 100 μs 60 . Figure 7a-d show the median for I ON as a function of L CH for V DS = 1 V and V DS = 5 V for MoS 2 and WS 2 FETs, respectively, extracted from their respective output characteristics. For both TMDs, at low V DS = 1 V, i.e., in the linear region, I ON is expected to demonstrate an inverse channel length dependence following Eq. (4).
This trend is observed for both MoS 2 and WS 2 FETs in Fig. 7a, b, respectively, for channel lengths L CH ≥ 1 μm. However, for devices with channel length L CH < 1 μm, the inverse channel length dependence is obscured by R c . Similar linear dependence is observed for I ON in longer-channel devices (L CH ≥ 1 μm) at Table 3 Benchmarking ON-state performance at V DS = 1 V (best values are compared with median/mean values shown within parentheses).  Fig. 7c, d, respectively, following Eq. (5).
These results are in accordance with classic long-channel FET characteristics (i.e., at low drain bias, the device operates in the linear regime (Eq. (4)), whereas for V DS ≥ V GS À V t lin , the channel is pinched-off, resulting in current saturation). The saturation current follows a square-law dependence on the overdrive voltage and, therefore, on n S (Eq. (6)) 62 . In shorter-channel devices (L CH < 1 μm), as the lateral electric field (ξ % V DS L CH ) becomes more than the critical electric field (E C ), the carrier velocity reaches  saturation velocity (v SAT ). This leads to current saturation, with the saturation current being independent of L CH as described by Eq. (6) 62 .
However, in order to observe current saturation due to velocity saturation, the drain bias must meet the criterion given by Eq. (7).
For example, as seen in Fig. 6, current saturation is achieved at V DS = 4 V for 100 nm MoS 2 FET and WS 2 FET, which is much lower than the corresponding V GS À V t lin of 11.6 V and 6.7 V, respectively. This explains why the drive current in shorterchannel MoS 2 and WS 2 FETs display little-to-no channel length dependence for high drain bias (V DS = 5 V), as seen in Fig. 7c Supplementary Fig. 6 and the corresponding device-to-device variation is summarized in Supplementary Table 7 for MoS 2 and WS 2 FETs. The higher drive current seen for MoS 2 FETs compared to that of WS 2 FETs is a direct consequence of lower V t lin , which allows for higher n S in MoS 2 channels. Further improvement in the drive current of scaled 2D FETs can be achieved by reducing R c . Note that, while there are reports of higher I ON in large-area grown MoS 2 films, none of the earlier studies provide extensive device statistics 22,[63][64][65] . I ON for UTB Si MOSFET is 35 nA.μm −1 for 0.9 nm thick Si 51 . The "champion" devices are benchmarked in Table 3. Supplementary Table 8 shows benchmarking of our statistical study on MoS 2 FETs using field-effect mobility and drive current (at V DS = 2 V) with similar channel length dependent statistical studies from the literature. The mean and standard deviation is compared with the L CH dependence and plotted in Supplementary Fig. 7. Better performance is seen for our channel length dependence study compared to ref. 66 for both the drive current and mobility.
Finally, saturation velocity (v SAT ) is another key material parameter that determines I ON in scaled FETs. This is because at low lateral electric field (ξ) the average electron drift velocity increases linearly through the mobility (v d ¼ μ FE ξ), but at large electric fields, which are easily achievable in sub-micron FETs, the carrier velocity saturates. Thus, I ON becomes less dependent on μ FE and is instead proportional to v SAT , following Eq. (6). Additionally, high v SAT is needed for faster switching 11 .  69 . However, their measurements were done using nanosecond range pulses to reduce the impact of selfheating and hot carrier capture by deep oxide traps. For WS 2 , this is the first report of v SAT .

Discussion
In conclusion, we have performed a detailed study of device-todevice variation and impact of channel length scaling on the electrical parameters, such as threshold voltage, subthreshold slope, density of interface trap states, ratio of minimum to maximum current, field-effect electron mobility, drive current, contact resistance, and saturation velocity, of MOCVD grown MoS 2 and WS 2 monolayer based FETs using statistical measures such as median, mean, standard deviation, and minimum/maximum values and have benchmarked our findings against other similar reports from 2D literature as well as UTB Si FETs. While in absolute terms the spatial variations in the respective benchmarking parameters appear to be large for MoS 2 and WS 2 FETs, when compared at scaled oxide thickness, our results are not significantly different from the projected variations for UTB Si FETs. Our "champion" long-channel MoS 2 and WS 2 FETs with L CH = 5 μm demonstrated electron mobilities of 30 cm 2 V −1 s −1 and 33 cm 2 V −1 s −1 , respectively, when extracted using peak transconductance and 46 cm 2 V −1 s −1 and 33 cm 2 V −1 s −1 , respectively, when extracted using TLM method. For synthetic monolayer WS 2 films, these are the highest reported room temperature electron mobilities, 1.5X better than the best report from the literature. Similarly, our "champion" shortest channel length MoS 2 and WS 2 FETs, with L CH = 100 nm, demonstrated drive currents as high as 161 μA.μm −1 and 53 μA.μm −1 for V DS = 5 V at carrier densities of n S = 1 × 10 13 cm −2 and 4.4 × 10 12 cm −2 , respectively, in spite of the presence of high contact resistances. We attribute our accomplishments to the epitaxial growth of highly crystalline 2D monolayers on sapphire substrate via MOCVD at 1000°C using chalcogen and sulfur precursors that minimize carbon contamination in the film, as well as to the clean transfer of the film from the growth substrate to the device fabrication substrate. Our findings suggest that 2D FETs are promising alternatives for future VLSI circuits.

Methods
MOCVD growth. Uniform monolayer deposition was achieved in a cold-wall horizontal reactor with an inductively heated graphite susceptor equipped with wafer rotation as previously described 27 . Molybdenum hexacarbonyl (Mo(CO) 6 ) and tungsten hexacarbonyl (W(CO) 6 ) were used as metal precursors while hydrogen sulfide (H 2 S) was the chalcogen source with H 2 as the carrier gas. Mo (CO) 6 maintained at 10°C and 950 Torr in a stainless-steel bubbler was used to deliver 0.036 sccm. W(CO) 6 maintained in a bubbler at 10°C and 760 Torr delivered 6.4 × 10 −4 sccm. The flow rate of H 2 S was 400 sccm and the reactor pressure was 50 Torr for both sulfides. MoS 2 was deposited in a single step process at 1000°C where coalesced monolayer growth across the 2″ wafer was achieved in 18 min. WS 2 was deposited using a multi-step process with nucleation at 850°C and lateral growth at 1000°C, which resulted in coalesced monolayer growth across the 2″ wafer in 10 min 28 . In both cases, after growth, the substrate was cooled in H 2 S to 300°C to inhibit decomposition of the MoS 2 and WS 2 films.
Material characterization. A Bruker Icon atomic force microscope was used to measure surface morphology and film thickness. Scanasyst AFM tips with a nominal tip radius of ≈2 nm and spring constant of 0.4 Nm −1 were used in the peak-force tapping mode for the measurements. Photoluminescence (PL) maps were acquired over a 5 × 5 μm 2 area with a laser wavelength of 532 nm and 300 grooves per mm grating in a WITec apyron Confocal Raman Microscope. A PANalytical MRD diffractometer with a 5-axis cradle was used for in-plane X-ray diffraction characterization of the sulfide films 70 . A Cu anode X-ray tube operated at 40 kV accelerating voltage and 45 mA filament current was used as the X-ray source. On the primary beam side, a mirror with ¼°slit and Ni filter were used to filter the Cu Kα line. On the diffracted beam side, an 0.27°parallel plate collimator with 0.04 rad Soller slits with PIXcell detector in open detector mode were employed. To determine the in-plane epitaxial relation of the film with respect to a substrate, sample surface was ≈2-4°away from the X-ray incidence plane.
Transfer of monolayer films. Both the MoS 2 and WS 2 films were grown on 2″ sapphire wafers. The 2″ sapphire wafers were then cut into 1 × 1 cm 2 pieces. For each material, two (2) 1 × 1 cm 2 sapphire substrates were chosen, one corresponding to the center and another one corresponding to the edge of the 2-inch wafer. To fabricate the FETs, monolayer MoS 2 and WS 2 films grown on sapphire substrates were transferred onto 1 × 1 cm 2 device fabrication substrates, i.e., 50 nm Al 2 O 3 on Pt/TiN/p ++ -Si, using a PMMA (polymethyl-methacrylate) -assisted wet transfer process. First, the sapphire substrate with the monolayer film was spin coated with PMMA and then baked at 180°C for 90 s. The corners of the spin coated films were scratched using a razor blade and immersed inside a 1 M NaOH solution kept at 90°C. Capillary action drew NaOH into the substrate/film interface, separating the PMMA/monolayer film stack from the sapphire substrate. The separated film was then rinsed multiple times inside a water bath and finally transferred onto the 50 nm alumina substrate and baked at 50°C and 70°C for 10 min each to remove moisture and residual PMMA, ensuring a pristine interface.
Gate dielectric fabrication. Direct replacement of thermally oxidized SiO 2 with a high-κ dielectric such as Al 2 O 3 grown via atomic layer deposition (ALD) is a logical choice to scale the EOT. However, we found that a Al 2 O 3 /p ++ -Si interface is not ideal for back gated FET fabrication owing to higher gate leakage current, more interface trap states, and large hysteresis, all of which negatively impact the performance of the device. Replacing Si with Pt, a large work function metal (5.6 eV) allows for minimal hysteresis and trap state effects 71 . Since Pt readily forms a Pt silicide at temperatures as low as 300°C, a 20 nm TiN diffusion barrier deposited by reactive sputtering was placed between the p ++ Si and the Pt, permitting subsequent high temperature processing 72 . This conductive TiN diffusion barrier allows the back-gate voltage to be applied to the substrate, thus simplifying the fabrication and measurement procedures. The polycrystalline Pt introduces very little surface roughness to the final Al 2 O 3 surface, with a rms roughness of 0.7 nm.
Device fabrication. Back gated field-effect transistors (FET) are fabricated using ebeam lithography. To define the channel region the substrate is spin coated with PMMA and baked at 180°C for 90 s. The photoresist is then exposed to e-beam and developed using 1:1 mixture of 4-methyl-2-pentanone (MIBK) and 2 propanol (IPA). The monolayer MoS 2 film is subsequently etched using sulfur hexafluoride (SF 6 ) at 5°C for 30 s. Next the sample is rinsed in acetone and IPA to remove the photoresist. In order to fabricate the source/drain contacts the substrate is again spin coated with MMA and PMMA followed by the e-beam lithography, developed using MIBK and IPA, and e-beam evaporation of 40 nm Ni/30 nm Au stack. Finally, the photoresist is rinsed away by lift off process using acetone and IPA.
Electrical characterization. Lake Shore CRX-VF probe station and Keysight B1500A parameter analyzer were used to perform the electrical characterization at room temperature in high vacuum (≈10 −6 Torr). Standard DC sweeps are used for the measurements of transfer and output characteristics of all devices. To ensure that the FETs are stabilized, they are conditioned by multiple repetitions of the same measurement. The transfer characteristics are measured three times to condition each FET and the fourth measurement is used for the analysis. The output characteristics are measured twice following the transfer characteristics and the second measurement is used for the analysis. We have found that no burn-in procedure is needed to ensure proper contact formation. Both MoS 2 and WS 2 FETs were measured as-fabricated.
Reporting summary. Further information on research design is available in the Nature Research Reporting Summary linked to this article.

Data availability
The datasets generated during and/or analyzed during the current study are available from the corresponding authors on reasonable request.

Code availability
The codes used for plotting the data are available from the corresponding authors on reasonable request.