Interface controlled thermal resistances of ultra-thin chalcogenide-based phase change memory devices

Phase change memory (PCM) is a rapidly growing technology that not only offers advancements in storage-class memories but also enables in-memory data processing to overcome the von Neumann bottleneck. In PCMs, data storage is driven by thermal excitation. However, there is limited research regarding PCM thermal properties at length scales close to the memory cell dimensions. Our work presents a new paradigm to manage thermal transport in memory cells by manipulating the interfacial thermal resistance between the phase change unit and the electrodes without incorporating additional insulating layers. Experimental measurements show a substantial change in interfacial thermal resistance as GST transitions from cubic to hexagonal crystal structure, resulting in a factor of 4 reduction in the effective thermal conductivity. Simulations reveal that interfacial resistance between PCM and its adjacent layer can reduce the reset current for 20 and 120 nm diameter devices by up to ~ 40% and ~ 50%, respectively. These thermal insights present a new opportunity to reduce power and operating currents in PCMs.


Supplementary Note 1 -Electron vs. phonon contribution in thermal conductivity
An important factor in the thermal transport mechanism in GST is the contribution from the electrons vs. phonons in the total thermal conductivity. Application of the Wiedmann-Franz (WF) law is a common approach that makes use of electrical resistivity for estimating the electronic contribution in thermal conductivity.
where k p and k e are thermal conductivities due to phonon and electron contribution, respectively, L is the Lorenz number, often assumed as the low temperature value of 2.44 × 10 −8 W Ω K −2 , T is temperature, and ρ is the electrical resistivity. Lyeo and coworkers [1] reported negligible electronic contribution in a-GST and c-GST, while ∼70% contribution in h-GST based on electrical resistivity measurements. However, a survey of the data available in literature, as given in Supplementary Table 1 for the electrical resistivity of the h-GST reveals a significant variations among reported values for the electrical resistivity of h-GST, ranging by as much as an order of magnitude. This difference among the electrical resistivities could be partially due to the different deposition process, composition variation, annealing time, or different measurement techniques. For example, Bragaglia et al. [2] reported that the resistivity of the h-GST largely depends on the degree of order in vacancy layers. They showed that for single crystalline h-GST, where the vacancy layers are highly ordered, the electrical resistivity could be substantially lower than reported values.
According to these studies, in h-GST, depending on the degree of disorder the thermal conductivity can largely vary. This is consistent with the observation of a disorder-induced metal-insulator transition in h-GST [3]. However, as the system transitions towards more order, as well as increased electron thermal conductivity the lattice thermal conductivity is expected to increase. First principle calculations demonstrate that the lattice thermal conductivity of bulk h-GST can vary in the range of 0.87-1.67 W m −1 K −1 depending on the crystal orientation [4]. Similarly, using first principle calculations, Campi et al. [5] showed that by adding various scattering terms (Sb/Ge sublattice disorder and vacancies), the lattice thermal conductivity of bulk h-GST can be adjusted to reduce from an ideal value of ∼1.6 W m −1 K −1 to experimentally reported value of ∼0.45 W m −1 K −1 . A more focused study on the effect of MIT on thermal conductivity can be found in Ref. [6].  [10][11][12]. Supplementary Figure 1(a) shows the experimental data with its corresponding theoretical fit for 20 and 160 nm h-GST. To find the GST thermal conductivity and the thermal boundary conductance (TBC) between GST and W (G GST/W ), we perform measurements on various thicknesses of GST. This is due to the fact that the sensitivity of our measurements to thermal conductivity and TBC varies with respect to thickness and, therefore, by measuring thermal conductance across various thicknesses we can distinguish the thermal conductivity from that of TBC. According to the sensitivity analysis in Supplementary Figure 1 (b,c), for 20 nm GST, the sensitivity of our measurements to TBC is highest whereas in the 160 nm thick GST, the sensitivity to TBC is negligible. Therefore, we obtain the intrinsic thermal conductivity of GST from 160 nm film where the influence from TBCs are minimum and obtain the TBC from the 40 and 20 nm films where the resistance from TBCs are comparable to that of the GST film.
For this, we measure the thermal conductance across Ru/W/GST/W/Si for a 20 and 40 nm thick GST, which includes the contribution of all resistances, i.e., layers and their corresponding interfaces.
In TBC measurements, although it makes more sense to use the thinnest GST films like 5 and 10 nm where the resistance due to the GST film is less, we refrained from taking these ultra-thin thicknesses into account since the thermal transport are not fully within a diffusive regime. For diffusive thermal transport, the mean free paths of heat carriers must be shorter than the thickness of the film [13]. As discussed in the main manuscript, the carriers mean free paths for W layer can be up to 10 nm.
Supplementary Figure 1. Thermal model analyses.(a) Theoretical fit for 20 and 160 nm GST thickness, (b,c) Sensitivity to thermal conductivity and TBC on either side of GST layer for a 20 and 160 nm GST (d) Schematic representing the approach used in this study to find the thermal boundary conductance between GST and W.
In 20 and 40 nm thick GST, the existence of a thinner GST layer increases the sensitivity of our measurements to G GST/W (Supplementary Figure 1(b)). To find G GST/W , as depicted in Supplementary Figure 1(d), we need to subtract the effect of all other resistors in the series from the total resistance. For this, since the 20 and 40 nm GST film yield a relatively small resistance between the Ru and Si, we can treat the entire stack (W/GST/W) as an interface and using a two layer model, measure the thermal conductance across the Ru/Si interface. The penetration depth in our measurement is on the order of ∼100 nm. The substrate is silicon which acts as a heat sink and therefore the resistance due to this layer is negligible. This leaves us with seven resistors between Ru and Si as depicted in the first schematic in Supplementary Figure 1(d).
Now, in order to deconvolve the thermal conductivity from that of the TBC, we need to know the intrinsic thermal conductivity of each layer as well as their corresponding TBCs. For this, using a different set of samples, we measure the thermal conductance across Ru/10 nm W/Si to account for the intrinsic thermal conductivity of W, Ru/W, and W/Si interfaces. Next, assuming the intrinsic thermal conductivity of 20 and 40 nm thick GST film is similar to that of the 160 nm, we subtract the resistance due to the intrinsic thermal conductivity of the 20 and 40 nm GST layer from the total resistance. In order to mathematically derive an equation for estimating the TBC between GST and W, we assume each layer and interface introduces a resistance to the thermal transport from the transducer to the substrate similar to the schematic in Supplementary Figure 1 (d). We can obtain the overall resistance of the stack between Ru and Si as follows: Where R represents the thermal resistance and is defined as the inverse of thermal conductance, R total = 1/G total . Due to high thermal conductivity of W, the thermal resistance of the W layer compared to that of GST is negligible and can be dropped from Eq 3. Additionally, due to electronic transport of heat between the metals, the interfacial thermal resistance between metal-metal interface such as Ru/W is negligible. Furthermore, we assume the boundary conductance at the front and rear sides of the GST that are in contact with tungsten are identical ( R W/GST = R GST/W ). As a result, Eq. 3 can be simplified to: In the above equation, except for the R W/GST , other parameters can be measured from TDTR and TEM. Considering that the thermal resistance is the inverse of the thermal conductance, by rearranging the terms in Eq. 4 we can obtain an equation for GST/W thermal boundary conductance as follows: In this analysis, G total is the total thermal conductance across the composite Ru/W/GST/W/Si stack and d film is the thickness of the GST film. Assuming a similar top and bottom interface between GST and W, we multiply the obtained TBC by two (in the numerator) to estimate an individual GST/W interface. Using Eq. 3, we provide an estimate for the G W/GST across different temperatures by averaging the values from 20 and 40 nm GST films. However, it must be noted that due to low thermal conductivity of the GST film in amorphous and cubic phases, the sensitivity to the G W/GST is not sufficient to enable us to directly fit for this parameter. Supplementary Figure 2 (a-c) shows the sensitivity of our measurements to parameters like thermal conductivity and TBC at each phases. There is negligible sensitivity to TBC in the amorphous phase. Upon transformation of a-GST to c-GST, the sensitivity to TBC increases but is still significantly lower than that of the thermal conductivity and therefore, would not affect the thermal conductivity measurements. The existence of low sensitivity to TBC in a-GST and c-GST, explains why the thermal conductivity for both 40 and 160 nm thick GST is similar up to 300°C. However, as the c-GST transitions to h-GST, the sensitivity to the thermal conductivity decreases relative to those of the TBCs across the interfaces, and therefore, above 320°C, the effective thermal conductivity is suppressed by the influence of interfaces.
Supplementary Figure 2 (d-f) shows our motivations behind using a lower bound in the main manuscript for G W/GST across different phases. These contour plots indicates the residual value for our model's fit relative to the best-fit with respect to the input thermal conductivity and G W/GST . For this, a range of different values for the thermal conductivity and G W/GST are used to fit our model to the experimental data, and based on the amount of deviation from the best-fit value these plots are generated for different phases of GST. The blue region in these plots corresponds to the minimum deviation from the best-fit value. In other words, for any thermal conductivity and G W/GST that are taken from the blue region, the model generates the same quality of fit to the empirical data.
This being said, since we can find the thermal conductivity of GST using the thick sample (160 nm), technically, we should be able to directly fit for the G W/GST in our thermal model using the 20 or 40 nm GST measurements. However, as demonstrated in Supplementary Figure 2 (d and e), due to lack of sensitivity in a-GST and c-GST, for any G W/GST that has a value higher than the red circle mark (20 and 110 MW m −2 K −1 for amorphous and cubic, respectively), the model produces a good fit. For example, in the amorphous phase, if we only fit for the thermal conductivity and fix G W/GST to any value between 20 MW m −2 K −1 and infinity, the model produces the same quality of fit to the experimental data. On the other hand, in h-GST (2 (f)), the G W/GST that are in the range of 45-115 MW m −2 K −1 can produce a good fit. This observation leads to prescribing a minimum limit to G W/GST for amorphous and cubic phases. In order to calculate a lower bound for the G W/GST across different phases, we assume 10% uncertainty in the measurement of parameters that play a role in the thermal transport such as thermal conductivity of GST and its thickness. The following table indicates the sign for calculation of uncertainty that leads to a lower bound for TBC shown  Table 2. The selected sign for setting a lower bound on TBC between GST and W given in the Fig 3 (c,d) in the main manuscript. G tot is the thermal conductance across Ru/W/GST/W/Si Similar to Supplementary Figure 3 (b) in the manuscript, in order to observe the thermal conductance of the stack when GST is in cubic vs.∼ hexagonal phase, we perform a similar measurement for 5 and 40 nm thick films. For this, we initially measure the thermal conductance for an as-deposited GST across different temperatures to determine the thermal conductance as the phase transition occurs.
Then, we take another as-deposited sample, anneal it to 300°C, then cool the sample down to room temperature, and measure its thermal properties at different temperatures. Again, the same sample was annealed to 400°C and the thermal conductance was measured upon cooling. In this way, we obtained the thermal conductance across different temperatures for c-GST and h-GST. Supplementary nm, the ballistic transport of carriers prevents us from observing the changes in the thermal boundary resistance (TBR), and for the case of 40 nm, we lose sensitivity to the TBC due to increased resistance of the GST film itself.
Supplementary Figure 3 (a,b) indicates the thermal conductance from room temperature to 400°C for different thicknesses of GST sandwiched between 2 and 5 nm of W spacers, respectively. As can be seen, the thermal conductance is lower when the W thickness is 2 nm. This is also observed in the room temperature measurements as discussed in the main manuscript. Here, we observe a significant difference especially above the phase transition temperature (≥ 150°C). Above this temperature, the thermal conductance for 5 nm GST in both W thicknesses linearly increases with temperature. We attribute this to ballistic transport of phonon and electron across GST layer, as discussed in the main manuscript. It is worthwhile to mention that the effect of TBC between GST and W above 340°C is most noticeable for GST thickness of 20 nm. This is because for thicknesses thinner than 20 nm, the sample was heated up to 140°C and after waiting long enough for the sample to equilibrate, the temperature was raised to 160°C at a rate of 50 K/min. As can be seen, it takes nearly 2000 s for the GST layer to transition from amorphous to crystalline structure. Supplementary Figure 4 (c) indicates the thermal conductivity of thin GST films that have been annealed in a furnace for more than two hours at different temperatures. In our thin films, by applying a linear fit to the thermal resistance data as a function of the layer thickness, the thermal conductivity can be found. This method, however, only applies to GST for amorphous and cubic phase where the sensitivity to TBC is negligible, and we do not expect size effects in the thermal conductivity due to the relatively small mean free paths in the GST. As can be seen, the thermal conductivity increases as the annealing temperature increases and the values match the those obtained from the 160 nm measurements. On the other hand, in the hexagonal phase, since the reduction in TBC influences the measurements, the obtained resistance for the sample that is annealed to 400°C is close or even higher than the 320°C sample. Considering that h-GST has a factor of two higher thermal conductivity than c-GST, the measurement of higher Supplementary Figure 4. (a) Elemental map for the constituents materials in the stack configuration studied (b) Thermal conductivity evolution as the GST transitions from amorphous to cubic crystalline at 140°C to 160°C as a function of time for a 40 nm thick GST film with W spacers. (c) Thermal conductivity of GST at different annealing temperatures. Note, the thermal conductivity of 400°C annealed case is measured lower than reported in the manuscript due to the effect of reduced thermal boundary conductance.
thermal resistance for 400°C annealed samples than 320°C is unexpected. After performing in situ TEM and confirming that the GST film has not been damaged due to heating, we attributed this to the change in the thermal boundary conductance of GST with W layer.
Supplementary Note 3 -Why does interfacial resistance between GST and W change as the GST transitions from cubic to hexagonal?
As the GST undergoes the cubic to hexagonal phase transition, not only does the lattice structure change, but so do the electronic structure and the bonding. Obviously, the variation of several properties in GST makes it exceedingly difficult to pinpoint the exact reasons behind the observed reduction in TBC. Nonetheless, in order to provide more insight into the role of crystal structure and interfacial disorder on the observed transition in TBC, we conduct a series of molecular dynamics simulations of the TBC across cubic and hexagonal close packed interfaces of materials that have equivalent masses to W and GST using a 6-12 Lennard-Jones (LJ) potential. Lennard-Jones is a 2body potential; therefore, the only free parameter is the distance between the atoms, and this enables us to create different lattice structures using the same potential. This therefore allows us to study the role of crystal structure and disorder on TBC without making any assumptions regarding changes in the bonding character from the cubic to hexagonal phases. To this extent, this highlights the advantages of conducting these molecular dynamics simulations using the LJ potential. Additionally, the simplicity of these potentials allows us to assess our hypotheses to general classes of materials, thus providing means to broadly study our posits of the origin of reduction in TBC across the crystalline phase transitions.
Supplementary Figure 5. Molecular dynamics simulations configuration. Simulation set up and the location of heat baths for the molecular dynamic calculations.
Since we are using LJ potentials to describe the crystalline W and GST films, in order to avoid confusion or misrepresentation, we call the section that represents W as type 1 and the section that represents GST as type 2. With that in mind, we use parameters provided by Filippova et al. [14] for solid tungsten at room temperature ( = 1.451420 eV and σ = 2.50374 nm). Although according to the paper, these parameters are supposed to result in a BCC lattice structure, we observe the lattice is unstable and tends to reorient to FCC structure. Nonetheless, we use this potential since our main purpose here is to investigate the effect of structural changes on TBC. For the atoms in type 2 (GST), we could use a LJ potential with softer bonding energy compared to that of tungsten, yet, to keep the Supplementary and type 2, we use a simulation box of 300Å length with cross section area of 50×50Å 2 . In order to investigate the effect of disorder at the interface, we used a melt-quench technique to amorphize type 2 (GST) atoms. However, due to ordered interface of type 1, the amorphous structure nucleates near interface and turns into a thin FCC layer at the type-1/type-2 interface. We refer to this nucleated region as a disordered crystalline region which shows a higher TBC as compared to our "ordered" crystalline interfaces. The summary of our calculated TBC between different lattice structure are presented in supplementary table 3.
Our results suggest that a change in phase from cubic to HCP does not significantly change the thermal boundary conductance. However, structural disorder at the interface could play an important role in the reduction of TBC from the cubic to HCP phase in our measured data across the W/GST/W interfaces. This is consistent with previous computational and experimental observations regarding the effect of disorder at the interface on the enhancement of TBC [15][16][17][18]. Tian et al. [15] used a theoretical approach -atomistic Green's function-and showed that the interface roughness in Si/Ge can increase phonon transmission compared to an ideal sharp interface. They concluded that this effect is even more pronounced if the acoustic mismatch between the materials at the interface is large, which is the case for GST and W. Several molecular dynamics simulations [16,19] have shown that compositionally disordered interfaces show higher TBCs than sharp interfaces. In addition, Gorham et al. [17] experimentally showed that TBC can increase across ion irradiated interfaces of Al/native oxide/Si with sufficiently high ion dose due to compositional mixing and point defect formation. With respect to these previous works on the effect of disorder at the interface supported by our MD simulations, we hypothesize that one driving factor for the reduction in TBC from cubic to hexagonal phase could be due to the reduction of disorder rather than structural phase transition.
Supplementary Figure 8. Normalized density of states for type 1 and type 2 for different cases studied here. The Y-axis is dimensionless and has arbitrary units (arb. units).

Supplementary Note 4 -Sound speed measurement in ultra-thin GST
The phonon mean free path in materials plays an important role in the analysis of thermal conductivity which can be estimated with the knowledge of the sound speed, specific heat, and thermal conductivity [20]. Here, using the picosecond ultrasonic technique, we estimate the sound speed in GST for thicknesses less than 40 nm. In the configuration studied here, due to incorporation of multiple thin layers on top of each other (inset in Supplementary Figure 9 (b)), the interpretation of picosecond ultrasonic data can be complicated by the existence of reflections off different interfaces.
Therefore, in order to decipher the picosecond ultrasonic results accurately, we began our measurements with a simple substrate/transducer sample and gradually added more layers to the stack to deconvolve the effects of additional layers on the picosecond ultrasonic signals. Supplementary Figure   9  different layers for the configuration studied here. As can be seen in Fig 5 (b) i, a strain wave is launched from the surface and travels across the Ru layer. Upon reaching the Ru/W interface, a lack of sufficient acoustic mismatch between Ru and W, allows the wave packet to completely pass through the interface without any interference (Fig 5 (b) ii). On the other hand, once the strain wave reaches the W/GST interface (Fig 5 (b) iii), as a result of large acoustic mismatch between W and GST, the wave is partially reflected and travels back to the surface and appears as upward "humps" in the residual plot. The other portion of the wave that passes the interface travels across the GST layer, and again, is partially reflected upon reaching the other GST/W interface where the consequence of this reflection appears as downward "troughs" in the residual plot.  were taken using the OneView operating in DP mode to maximize the dynamic range of the camera.
Selected-area diffraction patterns were acquired using an aperture collecting from an area 160 nm in diameter. The large collection region of the selected-area aperture relative to the thin-film thickness allowed sampling from both the GST layer and Si substrate providing a self-consistent calibration for GST amorphous ring patterns and crystalline diffraction patterns.
Supplementary Figure 13. Transmission electron microscopy for a-GST, c-GST, and h-GST phases and their corresponding diffraction patterns. (a-c) 160 nm GST, (e-g) 40 nm GST film.