Abstract
Silicon quantum dots are attractive for the implementation of large spinbased quantum processors in part due to prospects of industrial foundry fabrication. However, the large effective mass associated with electrons in silicon traditionally limits singleelectron operations to devices fabricated in customized academic clean rooms. Here, we demonstrate singleelectron occupations in all four quantum dots of a 2 x 2 splitgate silicon device fabricated entirely by 300mmwafer foundry processes. By applying gatevoltage pulses while performing highfrequency reflectometry off one gate electrode, we perform singleelectron operations within the array that demonstrate singleshot detection of electron tunneling and an overall adjustability of tunneling times by a global top gate electrode. Lastly, we use the twodimensional aspect of the quantum dot array to exchange two electrons by spatial permutation, which may find applications in permutationbased quantum algorithms.
Introduction
Silicon spin qubits have achieved highfidelity one and twoqubit gates^{1,2,3,4,5}, above errorcorrection thresholds^{6}, promising an industrial route to faulttolerant quantum computation. A significant next step for the development of scalable multiqubit processors is the operation of foundryfabricated, extendable twodimensional (2D) quantumdot arrays. In gallium arsenide, 2D arrays recently allowed coherent spin operations and quantum simulations^{7,8}. In silicon, 2D arrays have been limited to transport measurements in the manyelectron regime^{9}.
Here, we operate a foundryfabricated 2 × 2 array of silicon quantum dots in the fewelectron regime, achieving singleelectron occupation in each of the four gatedefined dots, as well as reconfigurable single, double, and triple dots with tunable tunnel couplings. Pulsedgate and gatereflectometry techniques permit singleelectron manipulation and singleshot charge readout, while the twodimensionality allows the spatial exchange of electron pairs. The compact form factor of such arrays, whose foundry fabrication can be extended to larger 2 × N arrays, along with the recent demonstration of spin control^{10,11,12} and spin readout^{13,14}, paves the way for dense qubit arrays for quantum computation and simulation^{15}.
Results
Device and gate reflectometry
Our device architecture consists of an undoped silicon channel (Fig. 1a, dark gray) connected to a highly doped source (S) and drain (D) reservoir. Metallic polysilicon gates (light gray) partially overlap the channel, each capable of inducing one quantum dot with a controllable number of electrons^{16,17}.
While devices with a larger number of splitgate pairs are possible (see Supplementary Fig. S1 and refs. ^{17,18}), we focus on a 2 × 2 quantumdot array as the smallest twodimensional unit cell in this architecture, that is, a device with two pairs of splitgate electrodes, labeled G_{i} with corresponding control voltages V_{i}. The device studied is similar to the one shown in Fig. 1a, but additionally has a common top gate 300 nm above the channel, and was encapsulated at the foundry by a backend that includes routing to wirebonding pads. Quantum dots are induced in the 7nmthick channel by 32nmlong gates, separated from each other by 32nm silicon nitride (see “Methods”). The handle of the silicononinsulator wafer is grounded during measurements, but can in principle be utilized as a back gate. Figure 1b shows a schematic of the device with V_{i} tuned to induce a fewelectron double quantum dot underneath G_{1} and G_{4}. Source and drain contacts allow conventional I(V) transport characterization, while an inductor (wirebonded to G_{4}) allows gatebased reflectometry, in which the combination of a radiofrequency (RF) carrier (V_{RF}) and a homodyne detection circuit yields a demodulated voltage V_{H}^{19}. Bias tees connected to G_{1−3} (not shown) allow the application of highbandwidth voltage signals.
Measurement of the source–drain current I as a function of V_{1} and V_{4} reveals a conventional doubledot stability diagram (Fig. 1c), with bias triangles arising from a finite source bias V = −3 mV and cotunneling ridges indicating substantial tunnel couplings in this fewelectron regime (each dot is occupied by 6–9 electrons). The characteristic honeycomb pattern is also observed in the demodulated voltage V_{H} (Fig. 1d, acquired simultaneously with Fig. 1c), and suggests the potential use of G_{4} for (dispersively) sensing charge rearrangements (quantum capacitance) anywhere within the 2D array. In the following, we keep dot 4 in the fewelectron regime (6–9 electrons, serving as a sensor dot), resulting in an enhancement of V_{H} whenever dot 4 exchanges electrons with its reservoir, and reduce the occupation numbers of the other three dots (which in the singleelectron regime we refer to as qubit dots). In fact, the large capacitive shift of the dot4 transition by nearby electrons (evident in Fig. 1c for dot 1) was used to count the absolute number of electrons within each of the three qubit dots (see “Methods”).
Singleelectron control
It is convenient to control the chemical potential of the three qubit dots without affecting the chemical potential of the sensor dot, as illustrated for dot 1 by the compensated control parameter \({V}_{{\mathrm{1}}}^{{\mathrm{c}}}\) (Fig. 1d). This is done experimentally by calibrating the capacitive matrix elements α_{i4} such that V_{4} compensates for electrostatic crosscoupling between V_{1−3} and dot 4, that is, by updating voltage \({V}_{{\rm{4}}}={V}_{{\rm{4}}}^{{\mathrm{o}}}\mathop{\sum }\nolimits_{{{i}} = 1}^{3}{\alpha }_{{{4i}}}({V}_{{{i}}}{V}_{{{i}}}^{{\mathrm{o}}})\) whenever V_{1−3} is changed relative to a chosen reference point \(({{V}_{1}^{\mathrm{o}}},{{V}_{2}^{\mathrm{o}}},{{V}_{3}^{\mathrm{o}}})\). The presence of this compensation is indicated by adding a superscript “c” to the respective control parameters. Using this compensation, and setting the operating point of dot 4 with \({{V}_{4}^{\mathrm{o}}}\), the associated reflectometry signal V_{H} can be used to detect charge movements between the three qubit dots.
The compensated voltages are used to map out groundstate regions of various desired charge configurations of the qubit dots. For example, Fig. 2a was acquired by first parking V_{1} and V_{2} in the first Coulomb valley of dot 1 and dot 2 (keeping dot 3 empty by setting V_{3} = 0), then tuning V_{4} to the degeneracy point of dot 4 (maximum of V_{H}), before sweeping \({V}_{{\mathrm{2}}}^{{\mathrm{c}}}\) vs. \({V}_{{\mathrm{1}}}^{{\mathrm{c}}}\). The enhancement of V_{H} clearly shows the extent of the 110 groundstate region. (Here, numbers indicate the occupation of the three qubit dots, as illustrated in the schematics of Fig. 2.) Due to the relatively large capacitive coupling of the sensor dot to the qubit dots, dot 4 is in Coulomb blockade outside the 110 region; there V_{H} reduces to its approximately constant background. (The gain of the reflectometry circuit had been changed relative to the acquisition in Fig. 1d.)
In addition to the transverse double dot in Fig. 2a, we also demonstrate the longitudinal (Fig. 2b, with V_{1} = 0) and diagonal (Fig. 2c, with V_{2} = 0) double dots. While such a degree of singleelectron charge control is impressive for a reconfigurable, siliconbased multidot circuit, it is not obvious how coherent singlespin control (e.g., via micromagnetic field gradients^{20} or spin–orbit coupling^{12}) can most easily be implemented in these foundryfabricated structures. One option is to encode qubits in suitable spin states of 111 triple dots, and operate these as voltagecontrolled exchangeonly qubits^{21,22}. To this end, we demonstrate in Fig. 2d the tuneup of a triple dot (in order to populate also dot 2, V_{2} = 197 mV was chosen more positive relative to Fig. 2c), revealing the pentagonal crosssection expected for the 111 charge state.
Tuning of tunneling times
To demonstrate fast singleshot charge readout of the qubit dots, we apply voltage pulses to G_{1}–G_{3} while digitizing V_{H}^{19}. Specifically, twolevel voltage pulses V_{1,2,3}(t) are designed to induce oneelectron tunneling events into the quantumdot array or within the array, as illustrated by colorcoded arrows in Fig. 3a. One such pulse is exemplified in Fig. 3b, preparing one electron in dot 1 (P) before moving it to dot 2 for measurement (M). P and M are chosen such that the groundstate transition of interest (in this case the interdot transition) is expected halfway between P and M, using a pulse amplitude of 2 mV. This pulse is repeated many times, with V_{4} fixed at a voltage that gives good visibility of the transition of interest in V_{H}(τ_{M}). Here, V_{H}(τ_{M}) serves as a singleshot readout trace that probes for a tunneling event at time τ_{M} after the gate voltages are pulsed to the measurement point (Fig. 3).
Figure 3c shows the repetition of 100 such readout traces obtained at a topgate voltage of 6 V, revealing the stochastic nature of tunneling events, in this case with an averaged tunneling time of 300 μs. This time is obtained by averaging all singleshot traces and fitting an exponential decay. In the lower panel of Fig. 3c, \({\bar{V}}_{{\rm{H}}}\) indicates that the average (triangles) has been normalized according to the offset and amplitude fit parameters, which allows comparison with similar data (stars) obtained at a topgate voltage of 10 V (see “Methods”). The deviation of the data from the fitted exponential decay (solid line) may indicate the presence of multiple relaxation processes, and the reported decay times should therefore be understood as an approximate quantification of characteristic tunneling times within the array.
While the compact onegateperqubit architecture in accurately dimensioned silicon devices^{10,12} may ultimately facilitate the wiring fanout of a largescale quantum computer^{23}, an overall tunability of certain array parameters may initially be essential. Figure 3d demonstrates phenomenologically that all transition times studied can be decreased significantly by increasing the topgate voltage. (The specific gate voltages associated with each data point are listed in Supplementary Table S1.)
Electron shuttling in two dimensions
An important resource for tunnelcoupled twodimensional qubit arrays is the ability to move or even exchange individual electrons (and their associated spin states) in real space^{24}. In fact, a twodimensional triple dot, as in our device, is the smallest array that allows the exchange of two isolated electrons (Heisenberg spin exchange, as demonstrated in linear arrays^{25}, requires precisely timed wavefunction overlap).
To demonstrate the spatial exchange of two electrons, we first follow the 111 groundstate region of Fig. 2d towards lower voltages on G_{1−3}. In Fig. 4a, this is accomplished by reducing the commonmode voltage \({\epsilon }_{{\rm{1}}}^{{\rm{c}}}\), such that the 111 region only borders with twoelectron ground states. In this gatevoltage region, the charge configuration of the qubit dots is most intuitively controlled using a symmetryadopted coordinate system defined by
Physically, \({\epsilon }_{{{1}}}^{\mathrm{c}}\) induces overall gate charge in the qubitdot array, whereas detuning \({\epsilon }_{{{2}}}^{\mathrm{c}}\) (\({\epsilon }_{{\rm{3}}}^{c}\)) relocates gate charge within the array along (across) the silicon channel (cf. Fig. 1b). As expected from symmetry, the 111 region within the \({\epsilon }_{{{2}}}^{\mathrm{c}}\)–\({\epsilon }_{{{3}}}^{\mathrm{c}}\) control plane appears as a triangular region, surrounded by the three twoelectron configurations 011, 101, and 110, as indicated by guides to the eye in Fig. 4b. Importantly, due to the finite mutual charging energies within the array (set by interdot capacitances), these three twoelectron regions are connected to each other, allowing the cyclic permutation of two electrons without invoking doubly occupied dots (wavefunction overlap) or exchange with a reservoir.
In principle, any closed control loop traversing 011 → 101 → 110 → 011 should exchange the two electrons, which are isolated at all times by Coulomb blockade, making this a topological operation that may find use in permutational quantum computing^{26}. In practice, leakage into unwanted qubit configurations (such as 111, 200, 020, etc.) can be avoided by mapping out their groundstate regions, as demonstrated in Fig. 4c by slightly adjusting the operating point \({{V}_{4}^{\mathrm{o}}}\) of the sensor dot. This sensor tuning also allows us to verify the sequence of traversed charge configurations while sweeping gate voltages along the circular shuttling path C, by simultaneously digitizing V_{H}. The time trace of one shuttling cycle, starting and ending in 011, is plotted in Fig. 4d, and clearly shows the three charge transitions associated with the twodimensional exchange (i.e., spatial permutation) of two electrons.
Discussion
In this experiment, only gates G_{1}, G_{2}, and G_{3} can be pulsed quickly, due to our choice of wirebonding G_{4} as a reflectometry sensor. Therefore, the acquisition in Fig. 4d took much longer (51 s) than the intrinsic speed expected from the characteristic tunneling times in Fig. 3. We did not observe any effects indicating alternative tunneling channels^{27}, but verified by intentionally changing the radius of C and inspecting V_{H}(C) that leakage into undesired charge configurations does indeed now occur. In future experiments, a faster execution of C combined with spinselective readout^{28} may allow a more direct confirmation of the electrons’ shuttling paths within the array.
We verified that dot 4 can also be depleted to the last electron (see “Methods”) and future work will investigate whether the sensor dot can simultaneously serve as a qubit dot. Our choice of utilizing dot 4 as a charge sensor (read out dispersively from its gate) realizes a compact architecture for spinqubit implementations where each gate in principle controls one qubit. This technique also alleviates drawbacks associated with the pure dispersive sensing of quantum capacitance, such as tunneling rates constraining the choice of RF carrier frequencies or significantly limiting the visibility of transitions of interest. For example, the honeycomb pattern in Fig. 1d with a clear visibility of dot4 and dot1 transitions is unusual for gatebased dispersive sensing in the fewelectron regime, where small tunneling rates typically limit the visibility of dottolead or interdot transitions^{29}. This is a consequence of the strong crosscapacitance between the reflectometry gate G_{4} and dot 1, allowing the RF excitation to probe also the quantum capacitances arising from dot 1. This also explains the visibility of discrete features within the bias triangles of Fig. 1d and shows the potential of gatebased reflectometry for directly revealing excited quantumdot states. The binary nature of the highbandwidth charge signal (evident in Fig. 2) may also simplify the algorithmic tuning of qubit arrays^{30}.
While all data presented were obtained at zero magnetic field, application of finite magnetic fields to explore spin dynamics and to characterize spinqubit functionalities should also be possible. In LETI’s silicononinsulator technology, coherent spin control was demonstrated for holes in double dots using spin–orbit coupling^{10,12}, and electrically driven spin resonance was observed for electrons in double dots using the interplay of spin–orbit coupling and valley mixing^{11}. Readout of spin using reflectometry has been demonstrated both for holes^{10,12} and electrons^{13,14}.
Another important next step is the application of our findings to larger 2 × N devices (see Supplementary Fig. S1 for a 2 × 4 and 2 × 8 device). Unlike linear arrays of qubits^{31}, which do not tolerate defective qubit sites, the development of 2 × N qubit arrays may prove useful for the realization of faulttolerant spinqubit quantum computers, trading topological constraints against lower error thresholds^{32}. The systematic loading of such extended arrays with individual electrons, as well as the controlled movement of electrons along the array, can be facilitated by virtual control channels similar to those used in linear arrays^{24,33}. Recent experiments even suggest that the capacitive coupling of multiple 2 × N arrays on one chip may be possible^{34,35}, opening further opportunities for functionalizations and extensions.
Further development of a spinqubit architecture employing this platform will rely on array initialization^{33}, coherent spin manipulation^{36}, and highfidelity operations^{37}, as well as readout protocols^{14,38}.
In conclusion, we demonstrate a twodimensional array of quantum dots implemented in a foundryfabricated silicon nanowire device. Each dot can be depleted to the last electron, and pulsedgate measurements and singleshot charge readout via gatebased reflectometry allow manipulation of individual electrons within the array, while a common top gate provides an overall tunability of tunnel couplings. We demonstrate that the array is reconfigurable in situ to realize various multidot configurations, and utilize the twodimensional nature of the array to physically permute the position of two electrons. We have also tested device stability, including charge noise (see “Methods” section) and reproducibility upon multiple thermal cycles from room temperature to base temperature (see Supplementary Table S2). In conjunction with complementary experiments in various other laboratories using similar LETI devices from the same fabrication run^{14,18,34,35}, these results constitute key steps towards faulttolerant quantum computing based on scalable, gatedefined quantum dots.
Methods
Sample fabrication
Our quantumdot arrays are fabricated at CEALETI using a topdown fabrication process on 300mm silicononinsulator (SOI) wafers, adapted from a commercial fullydepleted SOI (FDSOI) transistor technology^{16}. Compared to singlegate transistors (in which a singlegate electrode wraps across a silicon nanowire) two main changes in regards to gate patterning are needed in order to realize 2 × N arrays. First, N gate electrodes are patterned, in series along one silicon channel. Second, a dedicated etching process is introduced that creates a narrow trench through the gate electrodes, along the nanowire, thereby splitting each gate electrode into one splitgate pair^{17}. The main fabrication steps are described below. For illustrative purposes, the device shown in Fig. 1a was imaged after gate patterning and first spacer deposition^{16}, and does not represent the top gate and backend.
Starting with a blank SOI wafer (12 nm Si/145 nm SiO_{2}), the active mesa patterning is performed in order to define a thin, undoped nanowire via a combination of deepultraviolet (DUV) lithography and chemical etching. The silicon nanowire is 7nm thin after oxidation, and has a width of ~70 nm for the device studied in this work. Then, a highquality 6nmthick SiO_{2} gate oxide is deposited via thermal oxidation. To define the metal gate, a 5nmthick layer of TiN followed by 50 nm of n+doped polysilicon is used from the standard FDSOI processing. The gate is patterned using a combination of conventional DUV lithography combined with an electronbeam lithography process, allowing to achieve an aggressive intergate pitch down to 64 nm (gate length, longitudinal gate spacing, and transverse gate spacing as small as 32 nm) without the need for extreme ultraviolet technology. Then, 32nmthick SiN spacers between gates and between gates and source/drain regions are formed, which serve two roles: they protect the intergate regions from selfaligned doping (therefore keeping the channel undoped), and they define tunnel barriers within the array. Afterwards, raised source/drain regions are regrown to 18 nm to increase the crosssection of source and drain access. Then, to obtain low access resistances, source/drain are doped in two steps: first with lightly doped drain implant (using As at moderate doping conditions) and consecutive annealing to activate dopants, and then with highly doped drain implant (As and P at heavy doping conditions). To complete the device fabrication, the gate and lead contact surfaces are metallized to form NiPtSi (salicidation), in preparation for metal lines to be routed to bonding pads on the surface of the wafer. Finally, a standard copperbased backendofline process is used to define an optional metallic top gate 300 nm above the nanowire, to make interconnections to bonding pads, as well as to encapsulate the device in a protective glass of silicon oxide. Using the powerful parallelism of foundry fabrication, we obtain dozens of dies on a single 300mmdiameter wafer, each of them containing hundreds of quantumdot devices buried 2–3 μm below the chip surface.
Voltage control
Lowfrequency control voltages are generated by a multichannel digitaltoanalog converter (QDevil QDAC) (https://www.qdevil.com), whereas highfrequency control voltages are generated using a Tektronix AWG5014C arbitrary waveform generator. To acquire voltage scans that involve compensated control voltages, we use appropriately programmed QDevil QDACs.
RF reflectometry
The reflectometry technique is similar to that described in ref. ^{19}, in which a sensor dot tunnelcoupled to two reservoirs was monitored via a SMDbased tank circuit wirebonded to the accumulation gate of the sensor. In this work, the sensor dot (located underneath G_{4}) is tunnel coupled only to one reservoir (source in Fig. 1a), and the increased crosscapacitance to the three qubit dots results in much larger electrostatic shifts of dot 4 whenever the occupation of the qubit dots changes. For example, each pair of triple points in Fig. 1d is spaced significantly larger than the peak width associated with the sensordot transition.
In order to increase the signal intensity as well as to allow for inaccuracies in α_{4i}, we find it useful to occupy the sensor dot with several electrons (6–9 in Fig. 2), and to intentionally powerbroaden the Coulomb peaks of dot 4 (with −70 dBm applied to the inductor) for all acquisitions in Fig. 2. The SMD inductance used is 820 nH, and the RF carrier has a frequency of 191.3 MHz. A voltagecontrolled phase shifter is used to adjust the phase of the reflected reflectometry carrier relative to the localoscillator signal powering the mixer. The output of the mixer is lowpass filtered to generate the demodulated voltage V_{H}. For the data presented here, the phase shifter was adjusted to remove a large background signal in the demodulated voltage, making V_{H} sensitive to phase changes in the reflected reflectometry carrier.
For the realtime detection of interdot tunneling events in Fig. 3c, an Alazar digitizing card (ATS9360) is used with a sample rate set to 500 kS/s. The integration time per pixel is set by a 30 kHz lowpass filter (SR560), yielding a signaltonoise ratio as high as 1.4 in this device.
Determination of electron number
For a given tuning of the quantumdot array, the occupation number of each qubit dot is determined by counting the number of discrete electrostatic shifts of the sensor dot (i.e., shifts of a dot4 Coulomb peak in V_{H} along V_{4}) as the qubit dots are emptied by continuously reducing the control voltage of the dot of interest. If the total number of electrons within the qubitdot array is desired, voltages V_{1,2,3} can be reduced simultaneously, while sweeping V_{4} over one or more Coulomb peaks of dot 4, which serves as an electrometer. An example of such a diagnostic scan, for the case of a 111occupied triple dot, is shown in Supplementary Fig. S3. To determine the number of electrons in the sensor (dot 4), we utilized Coulomb peaks associated with dot 3 as an electrometer for dot 4, while continuously reducing V_{4}. This works because the strong dispersive signal associated with the dot3tolead transition shows discrete shifts (along V_{3}) whenever the dot4 occupation changes (similar to the large mutual shifts evident in Fig. 1d).
Capacitance matrix
To support our interpretation of dot i being localized predominantly underneath gate i (i = 1, ..., 4), we extract from stability diagrams the capacitances C_{ij} between gate j and dot i (in units of aF) for oneelectron occupations:
In this capacitance matrix, the relatively large diagonal elements reflect the strong coupling between each gate and the dot located underneath it. By adding several electrons to the array, we have also observed that the capacitances change somewhat, indicating a spatial change of wavefunctions (not shown) and suggesting an alternative way to change tunnel couplings.
Fitting tunneling times
In Fig. 3c we show 100 singleshot traces (upper panel) and the average of all traces. The average has been fitted by an exponential decay with the initial value, the 1/e time, and the longtime limit (offset) as free fit parameters. For plotting purposes, \({\bar{V}}_{{\rm{H}}}\) is then calculated by substracting the offset from the average, and dividing the result by the initial value. For clarity of presentation (the sampling rate for raw data of Fig. 3c was 500 kS/s), in the lower panel of Fig. 3c we also decimated the time bins by a factor of 4. Such a decimation was also used for plotting the data related to the other transitions investigated, as reported in Supplementary Fig. S2.
Assessing device stability
At base temperature of our dilution refrigerator (≲50 mK) the charge noise of the device is estimated as follows. The device is configured as a single quantum dot and the current flow is measured in the presence of a small source–drain voltage. Due to Coulomb blockade, current peaks as a function of gate voltage can then be used to measure the effective gatevoltage noise, by measuring the noise spectrum of the current and converting it to gatevoltage noise based on the first derivative of current with respect to gate voltage^{18}. Using the gatevoltage lever arm, we convert the inferred gatevoltage noise into an effective noise in the chemical potential of the quantum dot, yielding ~1.1 μeV/\(\sqrt{\mathrm{Hz}}\) at 1 Hz. This value should be regarded as an upper bound (as it does not take instrumentation noise into account), and is comparable to the best values we found in literature for Si/SiGebased quantum dots^{39}.
In addition to charge noise, we report the spread in gate voltages needed to accumulate the first electron in each dot (which we refer to as threshold voltage), and their reproducibility in different cool downs. When measuring the three double dots in Fig. 2a–c, the nonparticipating gate voltages (V_{3}, V_{1}, and V_{2}, respectively) are fixed at zero. Therefore, the position and size of the shown Coulomb diamonds represent the variation of threshold voltages within this array. The sloped boundaries arise from capacitive cross coupling (offdiagonal elements of \(\hat{C}\)), and imply that the voltage threshold for the 0to1 transition of a particular gate electrode depends on the values of the other gate voltages. To facilitate comparison of 0to1 threshold voltages between different gate electrodes (and between different cool downs), the observed slope of a particular charge transition in the fivedimensional gatevoltage space can be used to extrapolate from the observed threshold voltage of each gate electrode to a hypothetical gatevoltage configuration where all other side gates are held at zero volt. Threshold voltages from three different cool downs of the same device are provided in Supplementary Table S2. The observed spread in extrapolated threshold voltages for different gate electrodes (of order 40 mV) is comparable to the change of voltage thresholds when warming the device to room temperature and cooling it back down, consistent with homogeneous gate definition during fabrication.
Reporting summary
Further information on research design is available in the Nature Research Reporting Summary linked to this article.
Data availability
The datasets generated and analyzed during the current study are available from the corresponding author (F.K.) upon reasonable request.
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Acknowledgements
We thank Silvano De Franceschi for technical help and the coordination of samples. This project received funding from the European Union’s Horizon 2020 research and innovation program under grant agreements 688539 and 951852. F.A. acknowledges support from the Marie SklodowskaCurie Action SpinNANO (Grant Agreement No. 676108). A.C. acknowledges support from the EPSRC Doctoral Prize Fellowship. F.K. acknowledges support from the Independent Research Fund Denmark.
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F.A. and A.C. performed the measurements. B.B., L.H., and M.V. produced the samples and commented on the manuscript. F.A., A.C., H.B., and F.K. analyzed the data and prepared the manuscript.
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Ansaloni, F., Chatterjee, A., Bohuslavskyi, H. et al. Singleelectron operations in a foundryfabricated array of quantum dots. Nat Commun 11, 6399 (2020). https://doi.org/10.1038/s41467020202803
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DOI: https://doi.org/10.1038/s41467020202803
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