Atomic threshold-switching enabled MoS2 transistors towards ultralow-power electronics

Power dissipation is a fundamental issue for future chip-based electronics. As promising channel materials, two-dimensional semiconductors show excellent capabilities of scaling dimensions and reducing off-state currents. However, field-effect transistors based on two-dimensional materials are still confronted with the fundamental thermionic limitation of the subthreshold swing of 60 mV decade−1 at room temperature. Here, we present an atomic threshold-switching field-effect transistor constructed by integrating a metal filamentary threshold switch with a two-dimensional MoS2 channel, and obtain abrupt steepness in the turn-on characteristics and 4.5 mV decade−1 subthreshold swing (over five decades). This is achieved by using the negative differential resistance effect from the threshold switch to induce an internal voltage amplification across the MoS2 channel. Notably, in such devices, the simultaneous achievement of efficient electrostatics, very small sub-thermionic subthreshold swings, and ultralow leakage currents, would be highly desirable for next-generation energy-efficient integrated circuits and ultralow-power applications.

Where d andsare calculated from equation (2) forby setting Vch = 0 V and VD', respectively. q is the basic electron charge, and n2D is the electron density per area in the channel.
Herein, vt is the thermal voltage, defined as kT/q. n is called the ideal factor, which represents the impact of the interfacial trap density (Dit) and n is estimated as 2~3 from the experiments.
In the forward sweep, VD' has to be reduced when VG increases to keep a relatively small offstate current, because the TS device works at the HRS, as shown in Supplementary Figure 6e.
When VG increases to -1.55 V, the working state of ATS-FET jumps from A to B with a constant VG while VD' and ID go up obviously. One can see that the increment of ID is only caused by the increment of VD' in this process as shown in equation (9 ≈ 0 mV/dec when → ∞ As shown in Supplementary Figure 6d and 6e, β is approximated to be infinity (e.g. ∆ G = 20 0) in the forward switching process ( → ). As a result, SS is approximated to be zero. Thus, the internal amplification gain (β = dVD'/dVG) is also a result of the NDR effect of TS device.
In practical terms, SSATS-FET is smaller than 2.3nkT/q (~SSBaseline-FET), which is induced by VD' modulated by VG, meanwhile the abrupt increase of ID is closely/directly related with the large increase of VD' (instead of VG) in the switching process.

Supplementary Note 2 | Analysis of hysteresis-free in the ATS-FET
The ATS-FET has the possibility to realize the hysteresis-free operation. As stated in ref.
[10], the hysteresis-free operation can be achieved by matching the resistance of the MOSFET (Rs) and the negative differential resistance (RTS) of TS device. Once the condition of RS >| TS | is satisfied, the hysteresis-free operation can be achieved in the ATS-FET.
To explain the physical mechanism of hysteresis-free operation more clearly, we define a similar parameter, (slope), which is defined as 10 ( sub )/ 10 ( ′ ) in the log-log coordinates as shown in Supplementary Figure 13. Two different ATS-FETs have been fabricated, denoted as Dev. #1 and Dev. #2. For the baseline MoS2 FET, the parameter can be obtained from its output characteristics. In the subthreshold regime, the subthreshold current ( sub ) can be expressed as where I 0 is a constant and dependent on the specific geometric dimension and fabrication process of the baseline MoS2 FET, ℎ is called as thermal voltage (= It can be observed that the S (slope) of the output curve of the MoS2 FET is about 1 for a given gate voltage for a small ′ in the log-log coordinates as shown in Supplementary Figure   13. For Dev. #1 as shown in Supplementary Figure 13a, the S of the NDR regime of TS device (0.6) is smaller than the slope of the output curve (1) and the numbers of the intersection of two curves could be three, which leads to the hysteresis. However, for Dev. #2 as shown in Supplementary Figure 13b, the S of the NDR regime of TS (~4) is bigger than the slope of the output curve (~1) and the numbers of the intersection of two curves only can be one, which would lead to the hysteresis-free operation.
Note that the slope of the NDR regime in the TS device is dependent on its threshold voltage (Vth-TS), threshold current (Ith-TS), hold voltage (Vhold-TS), and hold current (Ihold-TS), which can be tuned by optimizing its geometric dimension and fabrication process. [11][12][13]