Graphene memristive synapses for high precision neuromorphic computing

Memristive crossbar architectures are evolving as powerful in-memory computing engines for artificial neural networks. However, the limited number of non-volatile conductance states offered by state-of-the-art memristors is a concern for their hardware implementation since trained weights must be rounded to the nearest conductance states, introducing error which can significantly limit inference accuracy. Moreover, the incapability of precise weight updates can lead to convergence problems and slowdown of on-chip training. In this article, we circumvent these challenges by introducing graphene-based multi-level (>16) and non-volatile memristive synapses with arbitrarily programmable conductance states. We also show desirable retention and programming endurance. Finally, we demonstrate that graphene memristors enable weight assignment based on k-means clustering, which offers greater computing accuracy when compared with uniform weight quantization for vector matrix multiplication, an essential component for any artificial neural network.


The paper by Schranghamer et al. entitled "Graphene Memristive Synapses for High Precision
Neuromorphic Computing" demonstrated graphene-based atomically thin memristive synapses using traditional GFET device. The authors fabricated the back-gate GFET synapse device using CVD grown graphene as a channel and Al2O3 as gate dielectrics. Their graphene-based mersister synapse showing non-volatile and multi-bit characteristics through the application of drain voltage pulses of differing magnitudes. The authors also simulated "on-chip vector matrix multiplication (VMM)" using Graphene memristor.
The results are convincing but I am concerned with some aspect that are reported in the following: 1) Underlining hysteresis switching mechanism was not explained to support experimental data in We are glad that the reviewer found the results convincing. The reviewer has raised some excellent points related to the work. We completely agree with the reviewer that a clearer and more informative explanation of the hysteresis switching mechanism should be included in our manuscript. In addition, we acknowledge that the statement "programmable conductance in graphene field effect transistors (GFETs) devices similar to that seen in oxide-based memristors" was somewhat misleading but was not intended to insinuate that GFET memristors share the same programming mechanism as oxide-based memristors (i.e. formation/degradation of conductive filaments in the oxide). We also concur that testing passivated GFETs should allow for a clearer analysis of the switching mechanisms involved.
We have added the following brief discussion to address the distinction between oxide-based memristive mechanisms and that shown by GFETs  Indeed, as will later be discussed, the bulk oxide (Al2O3) is not believed to play any major role in the memristive mechanisms shown, instead being dominated by interactions at the graphene/Al2O3 interface.
We have added the following discussions on the hysteresis and conductance switching mechanisms to the revised manuscript: Hysteresis loops of the drain-to-source current have long been noted in graphene and related materials, including graphene oxide and carbon nanotubes (CNTs). This phenomenon has been the subject of numerous studies and is generally attributed to interactions between the materials and trap sites on their substrates and/or extraneous molecules adsorbed on the material surface or at the material/substrate interface [1,2]. Of these adsorbates, water molecules (H2O) have seen attention in studies due to their prevalence in most ambient environments, as well as the use of water baths in traditional graphene transfers [3][4][5]. While surface-bound H2O can be easily removed via vacuum or the addition of a passivation layer, H2O trapped at the graphene/substrate interface requires specific treatments to remove and can have significant impact on the electrical properties of the graphene. An investigation by Cho et al [6] on the effects of water trapping at the graphene/Al2O3 interface identified two possible adsorption modes for water trapped at the interface: molecular adsorption (in which the oxygen atom is bound to an AlS site on the substrate surface) and dissociative adsorption (in which the water molecule is split into an OHmolecule bound to an AlS site and a H + ion bound to an OS site). The alignment of H2O relative to graphene differs between the two modes (parallel for H2O in molecular adsorption and perpendicular for OHin dissociative adsorption), leading to differences in the local electrical field, with the field induced by dissociative adsorption being magnitudes larger than that induced by molecular adsorption. The stronger dissociative field in turn leads to a higher planaraveraged charge density and p-type doping of the graphene [2,5,6].
Based on the distinctly p-type nature of the GFETs tested and discussed in this manuscript, it is reasonable to assume that it is a result of dissociative adsorption of H2O trapped at the graphene/Al2O3, most likely as a result of the graphene transfer process discussed in the Methods section. Similar processes have been noted to result in trapped water adlayers at the interfaces of graphene and a number of different substrates [3,6,7]. Stemming from this, it is also reasonable to assume that the hysteresis shown in Fig. 1d Fig. R2). The hysteresis seen for the positive and negative sweeps in Supporting Information 2a and 2b closely resembles that seen in Fig. 1d and 1e, respectively.
This indicates that the hysteresis and hysteresis switching is not tied to any adsorbates on the free surface of the graphene channel.
However, this does not rule out contributions from adsorbates trapped at the graphene/Al2O3 interface. Previous studies, such as that by Woong Kim et al [8], have established that hysteresis due to adsorption of water at the interface can persist following surface passivation. Based on these observations, the forming process discussed in this paper is believed to be a result of switching between different adsorption modes for water molecules trapped at the graphene/Al2O3 interface.
Following fabrication, these molecules are believed to be dissociatively adsorbed on account of following the initial bias sweeping, any subsequent sweeping fails to demonstrate any significant hysteresis, a known characteristic of molecular adsorption. This can be seen in Fig. R2c and R2d.
The conductance switching demonstrated in GFETs following the forming process, as highlighted by Fig. 1d through 1g, is believed to be the result of dipole moment switching due to the generated electric field. Such effects have been shown to result in threshold and conductance shifting in field effect transistors with interfacial dipole monolayers, leading to the development of distinct memory states [9][10][11][12][13]. Following the forming process (the transition from dissociative adsorption of water molecules at the interface to molecular adsorption), the water molecules are randomly oriented due to the uncoordinated nature of AlS states at the Al2O3 surface [6]. In this state, the local electric field generated by the water molecules is far weaker than in dissociative adsorption, owing to the interference caused by the random orientation of neighboring dipoles. As a result, the graphene tends to display ambipolar transfer characteristics as opposed to its initial p-type characteristics. Previous studies have shown that interfacial water molecules at a graphene surface can be reoriented through the application of an external electric field [14,15]. This polarizes the water molecules and can align their dipoles due to their preference for an orientation parallel to the electric field, enhancing the local electric field and increasing conductance of the graphene channel [16]. Experimentally, this phenomenon is reflected by the increase in conductance increasing the number of distinct achievable memory states while retaining similar endurance. In contrast, all 200 nm channel length devices tested were found to be intrinsically ambipolar and displayed little-to-no shifting when programming pulses were applied. These results were taken to support our initial hypothesis regarding the role of water molecule adsorption and dipole alignment at the interface regarding changing conductance states. It is believed that the small area of the 200 nm channel length devices did not allow for sufficient water molecules to be trapped to  The channel scalability demonstrated also shows promise for large-scale integration of GFETs into crossbar-array architectures. As shown and discussed in Supporting Information 7, the nature of the programming phenomenon of GFETs, bias pulsing through the drain, allows for electrostatic isolation of devices in close proximity to one another despite the presence of a global back-gate.
Together with the aforementioned scaling, this indicates the potential for high integration density of GFET memristors, offering an attractive alternative for close-packed memristive device architectures such as dense crossbar-arrays. We are glad that the reviewer found the contents of the manuscript to be novel and interesting.

4) Several studies have been proposed on
However, we respectfully disagree with the reviewer regarding the suitability of the manuscript for Nature Communications. We do not dispute that the manuscript predominantly focuses on discussing the results obtained for our investigation into graphene-based resistive memory.
However, the reasons behind this investigation (the slow decline of the von Neumann architecture and subsequent push for biologically-inspired computing) have wide-reaching, multi-disciplinary connections that extend our work far outside of just being an investigation into a novel device technology. This is touched on in the manuscript by our investigation into device-level vector matrix multiplication (VMM) operations using GFETs, where we establish that not only are GFETs capable of storing the weight values necessary for VMM as conductance states but that they are also capable of realizing advanced quantization techniques such as k-means clustering at a device level. This, in turn, establishes the suitability of GFETs to be utilized as analog synapses for neuromorphic computing and artificial neural networks. We are glad that the reviewer found the manuscript to be well organized and well written. We are happy that the reviewer found the Supporting information to be relatively in good match with the explanations. between other, inactivated, neurons [28,29]. The most well-known example of this mechanism is the existence of modulatory neurons, also known as interneurons. When activated, these neurons release chemicals known as neuromodulators, differentiated from typical neurotransmitters by their ability to alter synaptic efficacy instead of generating an electrical response. These alterations can last up to several minutes, providing comparatively long-term modulation of synaptic events [30]. In addition, repeated heterosynaptic modulation has, through study, been found to promote the growth/retraction of synaptic connections, creating persistent changes in synaptic weight and contributing to long-term memory formation/storage [31]. This has made the implementation of heterosynaptic plasticity an important goal for developing the next generation of novel neuromorphic systems [29]. The modulation of conductance states afforded by different modulatory bias Vmod (VBG) values can be seen in Supporting Information 5 (included here as Fig. R4). All measurements were conducted on the same GFET using the same VDS pulsing scheme utilized in Figure 2e. Each state was held for 100 s with no observable degradation into neighboring states, indicating good retention for all Vmod. The changes in conductance states and memory ratios between adjacent states as a result of changing Vmod indicate the ability to implement synaptic potentiation and depression by using the back-gate bias to increase or decrease conductance states

Figure R4: Effects of Back-Gate Voltage on Conductance States in GFETs. The 16 conductance states (memory levels) obtained using write pulses (VDS) with a step size of 0.125 V and duration 1 s are shown for different backgate voltages: 0 V (blue), +5 V (black), +10 V (grey-blue), +15 V (orange), -5 V (yellow), and -10 V (green). At all non-zero back-gate voltages, the conductance for all 16 states is increased. Additionally, the memory ratio between neighboring states is controllably varied by changing the applied voltage, initially increasing for +/-5 V and then decreasing at higher voltages as the device saturates. Notably, despite poor conductance switching (memory ratio) in the GFET at higher pulse magnitudes when VBG = 0 V, performance is significantly improved for all back-gate voltages tested. It is apparent that applying different back-gate voltages to the GFETs during read and write operations allows for modulation, and even enhancement, of the memory levels achieved by
GFETs.

(weight values) independently from the application of programming pulses across the Source and
Drain. Thus, the extra degree of freedom offered by the multiterminal design of GFETs allows for synaptic modelling that is not possible in traditional two-terminal synaptic devices, such as those that operate using oxide-based memristors.
(2) The direction of hysteresis and the hysteresis window of some curves in Fig. 1d and 1e are unclear and clear figures should be provided.
These are very helpful observations provided by the reviewer.
Alterations have been made to Fig. 1 to remedy the issue.

(3) The authors claimed that increasing the sweep range appeared to increase the hysteresis window of the GFET until VDSmax = 5 V, after which the direction of hysteresis reversed and the hysteresis window began to decrease, which was similar to the situation in opposite voltage
polarity. Why the direction of hysteresis reversed? And why did the hysteresis window gradually increase initially and then decrease? (5) As shown in Fig. 1f and 1g, why higher positive and negative source-drain voltages can induce typical n-type and ambipolar characteristics respectively? The internal mechanism needs to be explained in detail and experimentally verified.
Both of these questions posed by the reviewer are very relevant for establishing/conveying a greater understanding of the underlying switching mechanisms present in GFET memristors.
We have added the following discussion on the hysteresis and conductance switching mechanisms to the revised manuscript: Hysteresis loops of the drain-to-source current have long been noted in graphene and related materials, including graphene oxide and carbon nanotubes (CNTs). This phenomenon has been the subject of numerous studies and is generally attributed to interactions between the materials and trap sites on their substrates and/or extraneous molecules adsorbed on the material surface or at the material/substrate interface [1,2]. Of these adsorbates, water molecules (H2O) have seen attention in studies due to their prevalence in most ambient environments, as well as the use of water baths in traditional graphene transfers [3][4][5]. While surface-bound H2O can be easily removed via vacuum or the addition of a passivation layer, H2O trapped at the graphene/substrate interface requires specific treatments to remove and can have significant impact on the electrical properties of the graphene. An investigation by Cho et al [6] on the effects of water trapping at the graphene/Al2O3 interface identified two possible adsorption modes for water trapped at the interface: molecular adsorption (in which the oxygen atom is bound to an AlS site on the substrate surface) and dissociative adsorption (in which the water molecule is split into an OHmolecule bound to an AlS site and a H + ion bound to an OS site). The alignment  Fig.  1d  of H2O relative to graphene differs between the two modes (parallel for H2O in molecular adsorption and perpendicular for OHin dissociative adsorption), leading to differences in the local electrical field, with the field induced by dissociative adsorption being magnitudes larger than that induced by molecular adsorption. The stronger dissociative field in turn leads to a higher planaraveraged charge density and p-type doping of the graphene [2,5,6].
Based on the distinctly p-type nature of the GFETs tested and discussed in this manuscript, it is reasonable to assume that it is a result of dissociative adsorption of H2O trapped at the graphene/Al2O3, most likely as a result of the graphene transfer process discussed in the Methods section. Similar processes have been noted to result in trapped water adlayers at the interfaces of graphene and a number of different substrates [3,6,7]. Stemming from this, it is also reasonable to assume that the hysteresis shown in Fig. 1d and 1e is primarily caused by the trapped H2O as well. To explore this phenomenon further, effort was made to observe the effects of passivation upon the demonstrated GFET hysteresis switching, a separate set of GFETs was fabricated on a separate Al2O3 substrate and passivated via the deposition of 120 nm of PMMA. Following passivation, the hysteresis switching tests discussed and demonstrated in Fig. 1d and 1e were performed upon the passivated devices. The results for these tests are demonstrated in Supporting Information 2 (included here as Fig. R2). The hysteresis seen for the positive and negative sweeps in Fig. R2a and R2b closely resembles that seen in Fig. 1d and 1e, respectively. This indicates that the hysteresis and hysteresis switching is not tied to any adsorbates on the free surface of the graphene channel.
However, this does not rule out contributions from adsorbates trapped at the graphene/Al2O3 interface. Previous studies, such as that by Woong Kim et al [35], have established that hysteresis due to adsorption of water at the interface can persist following surface passivation. Based on these observations, the forming process discussed in this paper is believed to be a result of switching between different adsorption modes for water molecules trapped at the graphene/Al2O3 interface.
Following fabrication, these molecules are believed to be dissociatively adsorbed on account of the distinctly p-type nature of the transfer characteristics for all GFETs tested as well as the noticeable hysteresis when observing the swept output characteristics. The increase in the drain bias applied during these sweeps is believed to induce a transition to molecular adsorption of the water molecules. The OHmolecule and H + ion bound to an AlS site and OS site, respectively, on the Al2O3 surface would recombine and bind to an AlS site, with the OH-bonds of the resulting H2O molecule lying relatively parallel to the plane of the graphene. This is supported by the transition of the GFET transfer characteristics following each sweep; as VDSmax increases in magnitude, VDirac shifts more and more negative, causing the transfer characteristics to become either ambipolar (for negative bias pulsing) or n-type (for positive bias pulsing). While the GFET is then able to demonstrate analog switching between the n-type and ambipolar states, it is unable to return to the original p-type characteristics indicative of dissociative adsorption. In addition, following the initial bias sweeping, any subsequent sweeping fails to demonstrate any significant hysteresis, a known characteristic of molecular adsorption. This can be seen in Supporting   Information 2c and 2d.
The conductance switching demonstrated in GFETs following the forming process, as highlighted by Fig. 1d through 1g, is believed to be the result of dipole moment switching due to the generated electric field. Such effects have been shown to result in threshold and conductance shifting in field effect transistors with interfacial dipole monolayers, leading to the development of distinct memory states [9][10][11][12][13]. Following the forming process (the transition from dissociative adsorption of water molecules at the interface to molecular adsorption), the water molecules are randomly oriented due to the uncoordinated nature of AlS states at the Al2O3 surface [6]. In this state, the local electric field generated by the water molecules is far weaker than in dissociative adsorption, owing to the interference caused by the random orientation of neighboring dipoles. As a result, the graphene tends to display ambipolar transfer characteristics as opposed to its initial p-type characteristics. Previous studies have shown that interfacial water molecules at a graphene surface can be reoriented through the application of an external electric field [14,15]. This polarizes the water molecules and can align their dipoles due to their preference for an orientation parallel to the electric field, enhancing the local electric field and increasing conductance of the graphene channel [16]. Experimentally, this phenomenon is reflected by the increase in conductance observed when positive bias pulses are applied to the GFETs through the drain, as demonstrated in Fig. 2g through 2j. When negative bias pulses are applied, the water molecules are oppositely polarized leading to reorientation. This is reflected by the decrease in conductance through negative bias pulsing shown in Fig. 2b through 2e.

(4) Are there any defects at the interface between alumina and graphene? If the defects exist, will they affect the channel conductance when the gate voltage is applied?
We have added the following discussion on interface defects to the revised supplemental materials as Supporting Information 10: As stated in the manuscript, the dominant interaction at the graphene/Al2O3 interface is believed to be that involving trapped water molecules. When the molecules are dissociatively adsorbed to the Al2O3 surface, the strong negative electric field generated has significant effect of the band structure of the graphene channel, effectively raising the valence band and inducing p-type doping. It has also been shown to induce interbanding between the graphene and OS bands at the Dirac point. When the water molecules are shifted to a molecularly adsorbed state, the local electric field is removed, lowering the valence band and returning the Dirac point of the graphene to the Fermi level [6]. Experimentally, this is reflected by the transition of the GFETs to an ambipolar state from their initial p-type characteristics. While adsorbed water molecules at the interface are believed to be the dominant mechanism in the shown hysteresis and conductance switching, this does not rule out the existence of Al2O3 defects and trap states or other adsorbates, such as PMMA residue from the transfer and lithography processes, that may also affect the graphene channel. However, based on past studies of the effects of PMMA residue, such as heavy p-type doping, low conductivity due to carrier scattering, and large hysteresis from the introduction of trap states, PMMA residue should not be a major concern [32].
The rather moderate p-type doping demonstrated by the GFETs, as well as the fact that both it and the demonstrated hysteresis are removable by applying bias pulses through the drain, indicate that resist residues have very little effect, if any, on the graphene characteristics. While the argument may be made these phenomena may be in part due to current-induced cleaning of the graphene channel [33], GFETs have been shown to return to their original p-type characteristics if left unused for long (on the order of weeks to months) periods of time and still remain programmable, ruling out PMMA residue as the dominant interaction. In addition, most trap states at interfaces with Al2O3 are attributed to dangling Al-O bonds at the oxide surface [34]. As most of these states would be occupied by the adsorbed water molecules, the overall charge trapping should remain small.  Fig. 1 [18,25,27,35]. b) Conductance states over 500 cycles of SET and RESET pulses of magnitude 5 V. Memory ratio remains consistent between the high and low conductance states over the entirety of the cycling process, signifying long term endurance.

(7) What's the energy consumption of graphene field effect transistors?
We have added the following comment on the power/energy consumption of GFET memristors to the revised manuscript: Power consumption for the GFETs is approximately 5 mW for write operations at a pulse magnitude of 5 V and less than 40 nW for read operations at a read voltage of 10 mV. Using of pulse time of 1 s, this establishes a switching energy of approximately 5 mJ.
(8) There seems to be no obvious error difference in Fig. 4e and 4f when N increase from 2 to 4.
Please make more comments.
The reviewer is correct to observe that the overall error difference between Fig. 4e and 4f is minimal. This is an artifact from an earlier draft on the manuscript that was overlooked during editing and we sincerely apologize for its inclusion. When the GFETs are allowed to operate using four memory levels (N = 4), 1 and 2 are reprogrammed in an effort to reduce the error between the targeted and actual conductance values, with 1 being set to 200 µS and 2 to 170 µS. However, these states, like those when N = 2, are 15 µS off from the targeted conductance values. As demonstrated by Fig. 4f, this means that while the error distribution is shifted slightly due to the relative position of the conductance states changing, the overall accuracy of the synapse is not improved. This serves to highlight a drawback of uniform weight distribution and its implementation using devices with discrete memory states, such as oxide-based memristors. When the desired weight (conductance) value lies between set states, it can be very difficult for the system to reach it unless it utilizes a very large number of memory states. The analog nature of GFET memristors, on the other hand, allows for precise programming of any weight (conductance) value within the distribution of conductance states. The experimentally obtained output current for when the GFETs are directly programmed to the nearest achievable conductance states, 1 = 214 µS and 2 = 156 µS, can be seen in Fig. 4g. The error between this output current and the expected output current shown in Fig. 4b is displayed by Fig.   4h. As would be expected, the error is significantly reduced.
(9) There are some format mistakes that need to be dealt with in the citation.
We thank the reviewer for this observation and have edited the citations accordingly.
The authors have addressed all the issues. However, in my opinion, there are still two questions need to be revised before accepted. 1, According to figure 1d and e, the relatively large hysteresis still exists at VDS=6.5V after the forming process at 5.5 V. It seems contradictory to the results in Figure R2c and d with almost no hysteresis. Based on the forming mechanism about H2O adsorption, dissociative adsorption can be transited to molecular adsorption during the forming process. Therefore, the hysteresis at 6.5V may be contradictory to the known characteristic of molecular adsorption.
2, What is the value of the gate voltage used to read Ids in Figure 2b to j ? According to Figure R4, the linearity of the Ids can be improved if the optimized gate voltage was applied. So, whether the accuracy in Figure 4 will be raised furtherly under an optimized gate voltage?

Response to Reviewers
Reviewer 3: The authors have addressed all the issues. However, in my opinion, there are still two questions need to be revised before accepted.
1, According to figure 1d and e, the relatively large hysteresis still exists at VDS=6.5V after the forming process at 5.5 V. It seems contradictory to the results in Figure R2c and d with almost no hysteresis. Based on the forming mechanism about H2O adsorption, dissociative adsorption can be transited to molecular adsorption during the forming process. Therefore, the hysteresis at 6.5V may be contradictory to the known characteristic of molecular adsorption.
We are glad that the reviewer found the revisions satisfactory. The reviewer has raised an excellent point related to the work. The presence of hysteresis following the completion of the forming process in Fig. 1 may seem contradictory to the results shown in Fig. S2. However, it is our belief that the hysteresis shown in Fig. 1 and Fig. S2 following the forming process is the result of remanent polarization, the dipole polarization remaining after the reorienting electric field is removed.
We have added the following brief discussion on hysteresis to the revised supplemental material as Supporting Information 11: It is important to note the significant hysteresis at high VDSmax demonstrated in Fig. 1d and 1e and Fig. S2a and S2b. Although the forming process was demonstrated to occur at lower VDSmax values, as denoted by the switching of the sweep direction, the hysteresis remains high following forming. Based on the postulated forming mechanism discussed in the manuscript (i.e. the switching of water molecules at the graphene/Al2O3 interface from dissociative adsorption to molecular adsorption), the post-forming hysteresis should be negligible, akin to that seen in Fig. S2c and S2d. To investigate the origins of the hysteresis at high VDSmax, the GFETs used for the tests shown in Fig. S2 were subjected to large (6.5 V) programming pulses of negative and positive polarity immediately following the tests shown in Fig. S2c and S2d, respectively. The output characteristics of the GFETs were then measured for different VDS sweep ranges, as in Fig. 1 and Fig. S2, with the results being shown in Fig. S11. The results show hysteresis greater than that displayed in Fig. S2c and S2d, though less than that displayed in Fig.   1 and Fig. S2a Fig. S2c and S2d, the dipoles are already polarized, resulting in no hysteresis. When the devices are reset using programming pulses of opposite polarity (Fig. S11), the repolarization of the dipoles during following VDS sweeps causes the hysteresis to return, albeit at a smaller magnitude than before the forming process, as would be expected of molecularly adsorbed water molecules when compared to dissociatively adsorbed molecules. Figure S11: Hysteresis of reset graphene devices. Output characteristics of GFETs at a back-gate bias of VBG = 0 V for different VDS sweep ranges denoted by VDSmax from a) 1 V to 6.5 V and b) -1 V to -6.5 V in steps of 0.5 V. Measurements were taken following those shown in Fig. S2c and S2d, corresponding to (a) and (b), respectively, with the GFETs first being reset using a programming pulse of opposite polarity, magnitude 6.5 V, and duration 1 s. Figure 2b to j ? According to Figure   R4, the linearity of the Ids can be improved if the optimized gate voltage was applied. So, whether the accuracy in Figure 4 will be raised furtherly under an optimized gate voltage?

2, What is the value of the gate voltage used to read Ids in
We thank the reviewer for pointing out that the read gate voltage for the results shown in Fig. 2 was never specified. The manuscript has been modified to accurately reflect the read gate voltage, VBG = 0 V. The results shown in Fig. 4 were also obtained at a read gate voltage of 0 V. Based on the results shown in Supporting Information 5, varying the back-gate voltage has such effects on GFET operation as changing the range of achievable conductance values and increasing/decreasing the memory ratio between neighboring conductance states. While proper optimization of these factors could result in increased VMM accuracy for devices utilizing discrete memory states, such as oxide-based memristors, that is not believed to be the case for the GFET memristive devices discussed in the manuscript. In the discussion pertaining to the results displayed in Fig. 4, it is established that the accuracy shown is enabled by the analog nature of GFETs, which allows for direct programming of a device to a desired conductance state. As a result, changing the memory ratio between states would have no effect on the VMM accuracy as the desired state would still be programmed directly. However, the effects of varying VBG may still be utilized for optimization of VMM operations. The ability to change the achievable range of conductance values of a GFET may be used to allow the GFET to reach weight values outside of its intrinsic range, allowing greater differentiation between synapses. Additionally, varying VBG can change the conductance value of the set state, allowing for tuning of weight values without requiring the use of programming pulses. Proper utilization of this could allow for less SET/RESET programming cycles and thus longer device lifetimes. Finally, while changing the memory ratio between neighboring states will not affect programming accuracy, it would change the pulse magnitudes needed to program different states. Proper optimization could thus be used to reduce power/energy consumption of GFET write steps by minimizing the necessary pulse magnitudes.