Nonvolatile ferroelectric field-effect transistors

Future data-intensive applications will have integrated circuit architectures combining energy-efficient transistors, high-density data storage and electro-optic sensing arrays in a single chip to perform in situ processing of captured data. The costly dense wire connections in 3D integrated circuits and in conventional packaging and chip-stacking solutions could affect data communication bandwidths, data storage densities, and optical transmission efficiency. Here we investigated all-ferroelectric nonvolatile LiNbO3 transistors to function through redirection of conducting domain walls between the drain, gate and source electrodes. The transistor operates as a single-pole, double-throw digital switch with complementary on/off source and gate currents controlled using either the gate or source voltages. The conceived device exhibits high wall current density and abrupt off-and-on state switching without subthreshold swing, enabling nonvolatile memory-and-sensor-in-logic and logic-in-memory-and-sensor capabilities with superior energy efficiency, ultrafast operation/communication speeds, and high logic/storage densities. There is growing interest in non-traditional materials for logic applications. Here, the authors demonstrate a domain device architecture based on ferroelectric LiNbO3 crystals with gate voltage controlled transistor without subthreshold swing and source voltage controlled nonvolatile transistor.

T he frequent data shuttling between the physically separated processing and memory units in traditional digital computers incurs considerable penalties on the energy efficiency and data bandwidth, which is further intensified by the increasing disparity between the speed of the memory unit and the processor 1 . The latest generation of computing approaches requires memory devices to enable high-throughput, energyefficient, and area-efficient information processing. Ferroelectric materials with spontaneous polarizations have piezoelectric, pyroelectric, and electro-optic properties and are widely used in nonvolatile memories, sensors, and electro-optic modulators that rely on heterogeneous integration of field-effect transistors (MOSFETs) [2][3][4][5] . Recently, there have been many observations of ferroelectric single crystals in which the domain walls are highly conductive [6][7][8][9][10][11][12] . Hall voltage measurements of ErMnO 3 and YbMnO 3 consistently indicated high mobilities of 670 cm 2 V −1 s −1 for active p-type carriers in tail-to-tail domain walls at room temperature 13,14 . These walls can be reversibly created, positioned and shaped using electric fields on a femtosecond time scale 15 , which is encouraging for future high-speed domain-wall nanoelectronics [16][17][18] . Although control over the injection of conducting domain walls between the source and drain electrodes has allowed landmark demonstration of threeterminal resistance memory devices 19,20 , they lack the superior abrupt on-and-off state switching capability of nonvolatile transistors. This functionality is pivotal for the performance of in situ data computing, storage, and sensing operations 21 .
Here we demonstrate such transistors using 5 mol% MgOdoped LiNbO 3 (LN) monodomain single crystals that offer significantly enhanced diode-like wall currents 10,11 . LN single-crystal thin films can currently be produced by ionic slicing of surface layers off bulk crystals and chemical bonding of these layers to Si wafers, and have been widely applied in pyroelectric sensors, surface acoustic wave filters, and electro-optic modulators 3,4 . In this work, conducting drain-gate and drain-source conduits were complementarily created and erased using a controlled gate/source voltage through 180°reversal of the local domains. These junctionless transistors demonstrate low leakage, fast operating speeds (<5 ns), high wall currents (~110 μA μm −1 ), and abrupt off-andon state switching without subthreshold swings (SS). In addition, these transistors offer uniform, programmable threshold voltages like those of the nanowire Ge/Si core/shell FET, with computing, memory, and addressing capabilities 22 .

Results
Device design and electrical measurement of LN FET. Figure 1a ( Supplementary Fig. 1a-c) displays phase-field simulations of the switched domains (thick arrows) and conducting walls between the drain (D), gate (G), and source (S) electrodes for a cross-sectional three-terminal LN cell (S2) controlled via the gate voltage (V g ) under application of sufficiently high drain voltage (V d ) when the source voltage is grounded (V s = 0). Because V g is smaller than the forward threshold voltage (V t1 ), the electric field (E) between D and G is strong enough to reverse the D-G domain during headto-head D-G wall formation, as shown in Step 1. The charged D-G wall in the thickness of 1.06 nm (inset in Supplementary Fig. 1a) is conducting and is partially screened by free electrons near G to compensate for the polarization charge (P) of 70 μC cm −2 to reduce the depolarization energy 23 . At this instant, the D-G current (I dg ) is on but the D-S current (I ds ) is off. When V g increases above V t1 , E strengthens between G and S, which allows the D-G domain to grow throughout the entire cell in forming a D-S wall to turn on I ds , as illustrated in Step 2. Simultaneously, the previous conduit between D and G is blocked (i.e., I dg = 0). When V g is reduced again below the backward threshold voltage V t2 , the D-S domain contracts back into the Step 1 state to shut I ds off via reversal of the local G-S domain in Step 3. This repetitive redirection of the conducting domain walls between D, G, and S appears similar to a single-pole, double-throw digital switch controlled by the gate voltage. Normally, V t1 ≠ V t2 because of hysteretic domain switching behavior that can be defined using the geometrical sizes of the samples (S1-13) listed in Table 1. Figure 1b shows planar scanning electron microscope (SEM) image of S9, where l dg and l gs are the distances between D and G and between G and S in widths of w, respectively, and the gate electrode width is l g . This mesa-like transistor was etched to a depth (h) of 64 nm with left and right side slopes (~80°) to contact D and S fully using Pt electrodes that were fabricated on an X-cut LN surface via electron-beam lithography (EBL) and dry etching processes (see the "Methods"). Figure 1c shows double I ds −V d and I dg −V d curves between 0 and 8 V when V g = V s = 0 V. During the first V d sweep from 0 to 8 V, the initially off I dg (I ds ) begins to turn on (off) at 2.6 V before turning off (on) again at 5.7 V. Subsequently, the off (on) state is maintained until V d drops to 0. The complementary on/off I dg and I ds follow the phase-field simulation results for wall redirection between G, D, and S in Fig. 1a (see Steps 1 and 2). During the next repeated sweep, I dg (I ds ) is always off (on above 2.2 V), indicating the nonvolatile natures of the D-G and D-S walls when created. Because the device was poled at an opposite voltage of −8 V, the on-and-off state switching above is reproduced in the first sweep. Subsequent in-plane piezoresponse force microscopy (PFM) phase imaging showed the remnants of the partially switched D-G domain after poling at +5 V (Step 1), which later extended throughout the D-S cell at +8 V (Step 2), as indicated by the yellow-colored regions in Fig. 1d.
When the D-S wall has been created, I ds can be controlled using V g through a major carrier accumulation/depletion mechanism within the unchanged D-S conduit without invoking of domain motion between D, G, and S, similar to a volatile MOSFET. Figure 1e shows semi-logarithmic I ds −V g plots at different V d values for S8 with much longer l dg and l gs to avoid D-S wall redirection during sweeping within the voltage range studied. Normally, the forward and backward on/off switching curves are hysteretic ( Supplementary Fig. 2a) that can be minimized by reducing the D and S electrode contact heights to the LN mesa for S13 ( Supplementary Fig. 2b). From the solidline fittings shown in Fig. 1e, we consistently estimated SS values as high as 216 mV dec −1 .
V g -controlled transistor without subthreshold swing. Progressive downscaling of the operating voltages and device sizes of conventional MOSFETs in pursuit of multigenerational computing with superior energy efficiency and high integration density has reached the Boltzmann limit at SS no less than 60 mV dec −1 at room temperature 24 . This could be avoided in the DW transistors. To minimize the SS, l dg , and l gs in S1-S5 were shortened so that the repetitive G-S domain switching would occur in Step 3 to turn off/on the complementary I g and I s by controlling either V s or V g , where I s = I ds + I gs and I g = I dg + I sg . For subscript description, I sg , for example, indicates the current flowing from S to G, where I sg = −I gs . Figure 2a shows V g -controlled complementary I s and I g characteristics for S1 at various applied V d when V s = 0. During forward V g sweeping from −6 to 2 V, I s switches abruptly from off to an on-state above V t1 that varies from −0.93 to −4.54 V as V d increases from 4 to 6.3 V; in contrast, I g switches in the opposite manner.
During subsequent backward sweeping of V g from 2 to −6 V, I s (I g ) turns off (on) below V t2 (−4.30 to −5.32 V). Simultaneously, several overshoots of negative I s peaks were observed near V t2 (see upper panel of Fig. 2a), indicating the temporary current flow occurring from S to G during wall redirection (from Step 2 to Step 1) through an intermediate Step 3 (Fig. 1a). When l gs was shortened from 70 nm in S1 to 57 nm in S6, V t2 increased up to −1.95 V and the I sg overshoots were too short to be detected ( Fig. 2b), thus indicating the adjustable hysteresis of both V t1 and V t2 . This abrupt on-and-off state switching advances the collective domain switching behavior that breaks through the SS limit of conventional MOSFETs. Figure 2c, d show typical V t1 −V d and V t2 −V d plots for the samples listed in Table 1. The two types of plots reflect the domain hysteretic switching behavior that can be adjusted by changing either the geometrical sizes (l dg , l gs , l g ) or V d . Normally, domain switching initiates from reverse domain nucleation at the interface near D or S above a coercive field of E c2 . When the domain exceeds a critical size in Step 1, it can penetrate throughout the entire cell in Step 2 under a much smaller driving field 23 . If l g >> h, we approximately obtain where E c1 is the average coercive field for D-S domain growth (0 < E c1 < E c2 ). The solid lines in Fig. 3c, d are the best  12 Step 1: Step 2: Step 3:  NATURE COMMUNICATIONS | https://doi.org/10.1038/s41467-020-16623-9 ARTICLE fits to the data according to Eqs (1) and (2), from which we found that E c1 = 260-300 kV cm −1 and E c2 = 330-350 kV cm −1 , respectively. The semi-logarithmic I ds −V g plots for S2 when V d = 8.5 V show the large on/off ratio (~10 4 ) and abruptness (SS = 0) of the on-to-off and off-to-on state switching over 100 cycles (Supplementary Fig. 3a). However, V t1 and V t2 show broad dispersions (~0.8 V) over the cycles. These dispersions are believed to be correlated with etching damage to the D and S electrode contacts to an LN cell during device fabrication that also sets the upper limit for large current flows. To mitigate this damage, thick electroplated Ni electrodes were fabricated above Pt (Supplementary Fig. 3b). Subsequently, double I ds −V d measurements showed a wall current as high as~110 μA μm −1 at 656 kV cm −1 V g dependences of complementary I s and I g under application of various V d with V s = 0 for S1 and S6, respectively, where I s turns on above V t1 (upward arrows) but turns off below V t2 (downward arrows); this contrasts with I g , which responds in the opposite manner. c, d V d dependences of V t1 and V t2 for various samples fitted using solid lines based on Eqs. (1) and (2)  ( Supplementary Fig. 3c), and after the initial three I ds −V d sweeps, the coercive field levelled off at 284 kV cm −1 with negligible dispersion over next 120 cycles ( Supplementary Fig. 3d). Unfortunately, this Ni electroplating technique cannot define fine sub-100 nm nanodevice patterns using academic facilities. Figure 2e shows successful on-and-off switching of I ds transients for S4 when toggled using V g pulses between −7 and 3 V at a frequency of 37 Hz under various applied V d .
V s -controlled nonvolatile transistor. In addition, the complementary on/off I g and I s can be controlled using V s between −4 and +4 V at various applied V d when V g = 0, as shown in Fig. 3a for S10, where the initially-on (-off) I g (I s ) turns off (on) abruptly below V t2 (<0) but back on (off) again above V t1 (>0). There are large misfits at the start and end points in each hysteretic loop. into Step 1 through the intermediate Step 3 (Fig. 1a). Both on-tooff and off-to-on I g (I s ) switching can be realized during the first V s sweeps from 0 → −4 V → 0 and from 0 → 4 V → 0 in Fig. 2b ( Supplementary Fig. 4a), respectively; both the on and off states are nonvolatile, as confirmed by the next two repeated cycles. The on-state current increases by more than four times after the first cycle, which appears to correlate with the wall reconstruction after removal of all applied voltages ( Supplementary Fig. 4b). Figure 3c shows the nonvolatile on-and off-states when toggled using V s pulses between −4 and 4 V at a repeat frequency of 8.2 Hz, where I g was accessed intermittently from an oscilloscope at V d = 6 V at a repeat frequency of 96 Hz. The switching remains stable versus switching number of up to 240 with an on/off current ratio > 10 4 , as shown in Fig. 4a; and the on-and off-states when toggled using V s pulses between −5 and 5 V are stable over retention time of 24 h, as shown in Fig. 4b. During reliability testing, a large body of data from two-terminal LN cells were adopted either at room temperature ( Supplementary Fig. 5a-d) or at 85°C (Supplementary Fig. 6a-d), where G electrodes were omitted for the convenience of electrical characterization and device fabrication. It is believed that the reliability data adopted either in three-terminal transistors or in two-terminal nanodevices are comparative due to the universality of their operation principles on the basis of domain nucleation and growth. The testing results are summarized here: (1) on/off currents in the ratio > 10 4 are both stable over retention time of >10 6 s at 20°C or >10 5 s at 85°C; (2) fatigue cycles can highly reach the number of 10 10 under the inhibited space-charge injection; and (3) operation speeds can be fastened from 330 ns at 500 kV cm −1 to <5 ns at 600 kV cm −1 . Meantime, the diode-like I ds current in this study can suppress sneak current paths through the persistent DWs (crosstalk) when using crossbar connection of high-density LN cells ( Supplementary Figs 7a-e and 8a, b). The DW transistor can enable the non-volatile information storage among D-G, G-S, and D-S domains. Though the neutralized D-S wall is more energetically stable than the charged D-G and G-S walls, the write voltage (V ds > V c ) is highest. However, once the G electrode is grounded (V g = V s = 0), the local domain nucleating field between D and G strengthens under a constant V d ; once the head-to-head needle-like domain is nucleated above a critical size between D and G, it can grow throughout the low field G-S region due to the driving force of a depolarization field during the compensation of the increased domain wall energy at the expense of the depolarization energy 23 . In this way, V c is reduced. Figure 4c shows I ds -V d curves for S13 at various V g , where V c decreases nearly by one third as V g = 0 and reduces further to 4.3 V as V g = −1 V with the energy consumption of~0.15 pJ bit −1 (~2PhwV c ). The V c can be scaled down almost linearly with l dg + l g + l gs , and the addressed cell (V g = −1 V) has a much smaller write voltage than other undressed cells (floating), which can increase the reliability of the crossbar architecture (disturbance immunity during the write). Likewise, V c can also be reduced through the E strengthening between G and S as V g > 1.5 V, as indicated from the V g −V c plot in Fig. 4d, since the tail-to-tail needle-like domain once nucleated between G and S can also grow throughout a low field D-G region in the same way.
Remarkably, the nonvolatility in the DW transistors not only reduces gate/source leakage, thus reducing standby power, but also enables programmable nanoprocessor development with computing, memory and addressing capabilities at much faster operating speeds than other charge-trapped FETs 22 .
Domain wall structure. The nonvolatile D-G and D-S domain walls in S11 and S12 after voltage poling can be imaged by lowangle annular dark-field scanning transmission electron microscopy (LAADF-STEM), as shown in Fig. 5a-e. Before focused ion beam thinning of the two samples, the D-G and D-S domains were also inspected by in-plane PFM amplitude and phase imaging ( Supplementary Fig. 9a, b). LAADF-STEM data were later collected along the [ 1100] direction (the R3c space group in hexagonal indexes 25 ) after optimization of the dose rate, the mechanical instability, and the radiation damage. The heavy Nb atoms appear brighter than the lightweight O atoms, and ferroelectric displacements of Nb cations are inverted horizontally across the domain wall (the dotted line), as indicated by the inset images in Fig. 5a. A straight D-G wall runs slightly beyond G at the mid-height of an etched cell upon the local 180°domain reversal (thick arrows), as indicated by the dotted line in Fig. 5a. Subsequent high-resolution images of the framed region in the insets show the head-to-head wall at an incline angle (θ) of 3.7°, which is much higher than the typical~1°observed in bulk crystals 11 . This increased inclination angle enhances I g in Figs. 2 and 3 by more than four orders of magnitude when compared with the 1.2 × 10 −5 -1.0 × 10 −2 μA μm −1 observed in bulk LN crystals [6][7][8][9][10][11] . When the domain grows throughout the entire cell, a decurved D-S wall then forms at the bottom (Fig. 5b). Subsequent high-resolution images of the framed regions in Fig. 5c-e unambiguously show a charged tail-to-tail wall near D, a neutral wall below G, and a charged head-to-head wall near S. The LAADF-STEM image was fitted with a parametric model in which the column Nb position was derived from the intensity distribution of each atom described as a Gaussian function ( Supplementary Figs 10a-d and 11a-c) 12,26 , where off-center displacements of the Nb columns near the ferroelectric domain wall with the thickness λ were analyzed using a hyperbolic tangent (tanh) function 27 , as lineated between two dashed lines in Fig. 5c, e. These wall regions are rich with antiparallel dipoles for the D-G wall with a smaller inclined angle in the middle (see the inset in Fig. 5a) but with walls meandering back and forth for the decurved D-S wall with larger inclined angles near the D and S edges ( Supplementary Fig. 10b) 12 . λ broadens with increasing tilt angle, as illustrated by the plot in the inset of Fig. 5e. These plots can be fitted using a solid line based on the following equation: where λ 0 is the neutral wall thickness, α is a coefficient, and 2P sin θ is the projected polarization charge along the wall. From the fitting, we found that λ 0 = 0.25 nm and α = 1.5 × 10 3 μm 3 μC −1 , implying a Low magnification TEM image of thinned S11 lamella viewed along the 1100 direction after poling at V d = 10 V and V g = 0 V with S floating, where the dotted and dashed lines delineate a straight D-G wall running along the 000 1 direction with a tilt angle of 3.7°, as estimated from high-resolution LAADF images of the framed region shown in the insets. b Decurved D-S wall in S12 after poling at V d = 10 V and V g = V s = 0 V. c, d, e High-resolution LAADF images of the framed regions in b, which demonstrate the presences of a charged tail-to-tail wall near D, a neutral wall below G, and a charged head-to-head wall near S; the insets show magnified dipole displacements near the wall regions in panel d and the tilt angle dependence of the wall thickness in panel e. Scale bars: 5 nm. Thick arrows indicate the domain/dipole orientations. The error bars are defined as standard deviation. NATURE COMMUNICATIONS | https://doi.org/10.1038/s41467-020-16623-9 ARTICLE NATURE COMMUNICATIONS | (2020) 11:2811 | https://doi.org/10.1038/s41467-020-16623-9 | www.nature.com/naturecommunications a single unit-cell thickness for a neutral wall (θ = 0°) that thickens up to 10 unit cells when θ = 90°.

Discussion
In summary, nonvolatile LiNbO 3 transistors were fabricated with high complementary on/off source and gate currents that were controlled using either gate or source voltages without subthreshold swings. The working principle of these transistors uses repetitive redirection of the conducting domain walls between D, G, and S upon ultrafast reversal of a collective ferroelectric order parameter. The observed ultrathin wall with high conductivity that could be increased further through wall angle tilt advances the voltage and size scalabilities of all-ferroelectric transistors beyond the limits of traditional MOSFETs. Each cell can perform independent data computation, storage and sensing with superior energy efficiency, stimulating processing-in-memory implementation of neuromorphic computing, general-purpose memcomputing and cybersecurity 1 . However, the digital switches are still premature at present stage when competing to the Si-based transistors: p-MOSFET is lacking for complementary operation in cascaded logic; operation voltages are very large; the hysteresisfree I ds -V gs transfer characteristics are limited in some specific V ds as SS = 0; and the nanosecond switching speed between offand on-states is still insufficient. Some significant improvements are required in logic for the development of next-generation domain wall nanoelectronics technologies.

Methods
Nanodevice fabrication. Congruent LN single crystals containing 48.5 mol% Li 2 O with 5 mol% MgO dopant were grown using the Czochralski technique with highpurity (99.99%) Li 2 CO 3 , MgO, and Nb 2 O 5 powders that were melted at 1250°C. The crystal was poled into a single domain pattern at 1180-1200°C at a current density of 8-10 mA cm −2 for 30 min. 200-nm-thick poly(methyl methacrylate) photoresist layers were spin-coated onto the surfaces of X-cut LN single crystals; the LN cell sizes were then defined using electron-beam lithography (EBL; JEOL 6300FS). 30-nm-thick Cr mask layers were subsequently deposited by thermal evaporation (NANO 36, Kurt J. Lesker), while any redundant Cr or photoresist layers that lay outside the written area were removed using a lift-off technique. The LN top layer that lay outside the area protected by the Cr mask layer was etched away to depths of 55-70 nm via ion milling using a reactive ion etching system (RIE-10NR, Samco, Japan). Finally, 30-nm-thick Pt top electrode layers were grown by magnetron sputtering (PVD-75, Kurt J. Lesker) at 400°C; these layers were then etched into the D, G, and S electrodes to contact the LN mesas by repeating the EBL patterning and ion milling processes described above. To mitigate etching damage to the D and S contacts, additional 150-nm-thick electroplated Ni electrodes with widths of~300 nm were fabricated above the Pt to strengthen the electrode contacts. All transistors were checked via planar-view SEM images (Sigma HD, Zeiss).
Phase-field simulations. The spatiotemporal evolution of the spontaneous polarization P i was determined using the time-dependent Ginzburg-Landau (TDGL) equations 28 : where L is the kinetic coefficient related to the domain mobility, δF δP i r;t ð Þ is the thermodynamic driving force for domain evolution, F is the total free energy, r(x 1 , x 2, x 3 ) is the spatial vector, and t is time. The total free energy is given by the following equation: where f Land , f grad , and f elec are the Landau energy, gradient energy, and electrical energy densities, respectively. The Landau energy density can be expressed as f Land ¼ α 1 P 2 3 þ α 11 P 4 3 þ α 2 P 2 1 (refs. 29,30 ), where α 1 , α 11 , and α 2 are the dielectric stiffnesses and the higher-order dielectric stiffnesses, respectively. The gradient energy density is related to the domain wall energy such that f grad ¼ 1 2 G ijkl P i;j P k;l , where P i,j is the spatial derivative of the ith component of polarization vector P i with respect to the jth coordinate and G ijkl represent the gradient energy coefficients. The electrostatic energy can be expressed as f elec ¼ À 1 2 κ c E i E i À E i P i , where κ c is the dielectric permittivity of the background materials. The electric field is calculated from where φ is the electrical potential. It was obtained by solving the Poisson equation of ∇ 2 φ = 0 using the specified electric potentials at the D, G, and S electrodes of the LN transistor. An open-circuit boundary condition was imposed on the top free surface area without the electrode. The elastic energy term is neglected in Eq. (5) based on the assumption that the elastic energy makes only a small contribution to the final domain wall configuration. To solve the governing equations above in the real space, a nonlinear multi-field coupling finite-element method was used. All the material constants used in the simulations are α 1 = −1.0 × 10 9 C −2 m 2 N, α 2 ¼ 0:9725 10 9 C À2 m 2 N, α 11 ¼ 0:9025 10 9 C À4 m 6 N, G 11 ¼ G 44 ¼ 0:4 α 1 j j, and κ c ¼ 10 κ 0 ¼ 10 8:85 10 À12 F m À1 (refs. 25,28 ). For convenience of the calculation, the material parameters were normalized 31 . The simulations were performed using a two-dimensional system, and four-node elements with a size of 1 nm 2 were used to model the LN structure. To model the semi-infinite LN single crystal substrate, the charge densities on the right and left edges of the LN substrate were set to be +P and −P, respectively. Partially reversed polarizations are assumed as the initial conditions to initiate the domain evolution process in the LN structure under application of various values of V d , V g , and V s . The final equilibrium domain structures were obtained under the applied voltages as shown in Fig. 1a (Supplementary Fig. 1a-c).
PFM and LAADF-STEM characterization. The domain patterns obtained after poling using positive and negative voltages were inspected via in-plane PFM amplitude and phase imaging (Icon, Bruker) using a contact PtIr-coated silicon tip with radius of~20 nm, a force constant of 2.8 N m −1 , and an AC amplitude of 0.5 V at 210 kHz. The LN surface was later coated with a protective Pt layer (∼35 nm thick). A cross-sectional specimen was cut and thinned using a dual-beam focused ion beam/scanning microscopy (Helios G4 UX, Thermo Fisher Scientific, USA) system with Ga-ion acceleration voltages ranging from 2 to 30 kV followed by ion-milling (Gatan 691, Gatan, USA) at voltages ranging from 1.5 to 0.5 kV to remove the damaged layer. A 200 kV JEM-2100F (JEOL Ltd., Japan) microscope was used to perform the LAADF-STEM observations.
Electrical characterization. All current-voltage curves were measured using an Agilent B1500A semiconductor analyzer operating in voltage-sweep mode. The sweep times were 1 s when using a current amplification range of 1 μA with instrumental off-current resolutions of 20 pA. For domain switching testing, two square test pulses with rise times of 2 ns were supplied to D and G (S) using a twochannel Agilent 81110A pulse generator. The steady-state on-and-off I s (I g ) current transient behavior with time was observed directly using a four-channel oscilloscope (LeCroy HDO6054, USA) in series with the S (G) with 12-bit voltage resolution and a 1 GHz bandwidth. During the nanosecond-scale domainswitching period, the internal resistance of the oscilloscope in series with the sample was adjusted to 50 Ω to realize a short circuit RC time constant, and was later adjusted to 1 MΩ (100 kΩ) to enable read-out of on-and off-currents with 0.2 nA (1 nA) resolution limits as shown in Figs. 2e and 3c, respectively.