Electronic-photonic arithmetic logic unit for high-speed computing

The past two decades have witnessed the stagnation of the clock speed of microprocessors followed by the recent faltering of Moore’s law as nanofabrication technology approaches its unavoidable physical limit. Vigorous efforts from various research areas have been made to develop power-efficient and ultrafast computing machines in this post-Moore’s law era. With its unique capacity to integrate complex electro-optic circuits on a single chip, integrated photonics has revolutionized the interconnects and has shown its striking potential in optical computing. Here, we propose an electronic-photonic computing architecture for a wavelength division multiplexing-based electronic-photonic arithmetic logic unit, which disentangles the exponential relationship between power and clock rate, leading to an enhancement in computation speed and power efficiency as compared to the state-of-the-art transistors-based circuits. We experimentally demonstrate its practicality by implementing a 4-bit arithmetic logic unit consisting of 8 high-speed microdisk modulators and operating at 20 GHz. This approach paves the way to future power-saving and high-speed electronic-photonic computing circuits.

The electronic circuit diagrams of the PGU and SGU are shown in Supplementary Figure 2a and 2b, respectively.
Arithmetic operations such as addition and subtraction have a potential to run into a condition known as overflow. Therefore, an overflow detector is required after the calculation, whose input ports include input operands, output carry signals, and the operation code. For example, the overflow in a signed addition is the XOR of the carry signals of the last two bits before it interacts with the operation code 1 . The operation code means the instruction which determines the function (addition, subtraction, and so on) to perform in the circuit. Fortunately, a traditional electrical overflow detector will fit in this EPALU well since all these required signals are in the electrical domain.

Supplementary Note 4: Latency analysis
The total latency of the EPALU can be expressed as = + × + 2 × , where = + + is the constant part, is the electro-optic transition time of the modulators, is the optical propagation latency per gate, is the opto-electronic transition time of the PDs, is the electrical latency in the MUXU per stage, and is the delay for the other electrical parts.
With the assumption that and for electrical gates are both 7 ps 2 , and for OE/EO conversion are both 10 ps 3,4 , is 0.3 ps 5 , we can obtain the curves in Figure 4a. All these values will vary with platform and fabrication node that are adopted. They could be further reduced as technology advances.

Supplementary Note 5: Loss analysis
To minimize the loss of the circuit, the coupling coefficient could be fine-tuned with the slightly revised structure shown in Supplementary Figure 3a with the one-bit diagram shown in Supplementary Figure 3b. It is obvious that the critical path is the lossiest one which goes through all the couplers. A relatively higher coupling efficient will contribute to the reduction of insertion loss. To be specific, more light should be coupled from port 1 to port 4 or 6. Port 5 is a tap path and only a small portion is required so that we treat the coupling coefficient h to be negligible.
Considering the splitting loss, propagation loss, and device insertion loss, we can get the total ratio of the entire input power (all input ports) to the output at the last port, which is

Supplementary Note 6: Scaling of dynamic power consumption
Our estimation is based on the experimental demonstration of a 64-bit ALU using the 90 nm technology node 6 . We first estimate the power consumption of the ALU part out of the entire chip by calculating the area ratio based on the reasonable assumption that the power consumption is proportional to the area. Along with the scaling equation 2 , we can write the scaling equation of power consumption as P = P 0 , where the P 0 is the power consumption of the entire chip, is area ratio and is the scaling ratio. The activity coefficient is 10% in the experiment and we also use this value in our calculation hereinafter. Further, the power increases exponentially with the frequency. From the experimental data in reference 6 , we could obtain the relationship between the frequency and the required voltage as well as predict the supply voltage needed at a higher frequency by linearly fitting. Therefore, we could easily predict the power consumption based on the equation of ∝ 2 .
The power consumption for each modulator in the proposed EPALU is The definitions of the related coefficients in the equation are list in the Supplementary Table 1 with the assumption that the inputs a and b are random signals.
Assuming the capacitance is 10 fF, and swing voltage is 1 V, we have the dynamic power consumption = 384 2 for a 64-bit ALU. Activity coefficient for ALU 10% In this section, we will carry out a systematic calculation of the power consumption, which includes not only the dynamic part but also the laser part and the thermal tuning part for a microresonator-based EPALU. The estimation is based on the characteristics of the state-of-theart photonic components.
First, the laser power will be largely determined by the loss as we calculated in Supplementary Note 5. Upon the optimistic assumption that the waveguide propagation loss is 0.002 dB/bit (1 dB/cm), the insertion loss of directional coupler is 0.05 dB, the insertion loss of grating/edge coupler is 1 dB, and the insertion loss of modulator is 0.5 dB 7 , we can get total loss for a 64-bit EPALU (e.g. m×n = 8×8) will equal to 21.97 dB (from Fig. 4b) + 9 dB (n is 8) + 3 dB (two wavelengths) + 1 dB (input coupler) = 34.97 dB. When the minimal detectable power is 1 uW 8,9 and the wall-plug efficiency of laser is up to 20% 10 , then the total laser power consumption will be 15.7 mW.
Second, microresonator-based modulators will require additional thermal tuning. This part will consume around 50 fJ/bit for each microresonator in a state-of-the-art monolithic electronicphotonic platform 11 . Then in total it requires 50 fJ/bit × 20 Gbit/s ×128 = 128 mW.
As we can see from Supplementary Figure 4, the total power consumption will be dominated by the thermal tuning. This portion of power consumption can be further reduced or even eliminated in the future using broadband modulators (e.g. electro-absorption modulators 12 or low-Q microresonator modulator 13 ) or using energy-efficient tuning materials (e.g. phase change material

Supplementary Figure 4. Power consumption comparison between EPALU and conventional electronic ALU (E-ALU).
In this 4-bit experiment, the power consumption per bit of the modulator is estimated to be 10.88 fJ/bit since the swing voltage is 0.8 V and the capacitance of the microdisk modulator is estimated to be 17 fF. The laser power is around 4 mW after eliminating the grating coupling loss. The requirement of the relatively higher laser power in the testing is because the coupling coefficients of the directional couplers have not been optimized yet in this first-generation chip/design. The optical signal (>100 μW) is then coupled out for off-chip detection. The resistance of the heaters is 6.03 kΩ, and around 2V is required for wavelength alignment of each microdisk modulator.

Supplementary Note 8: Power density calculation
The crucial part of the estimation of power density is the area calculation. VLSI simulation could directly output the area value, which is 2936.6 µm 2 for a 64-bit full adder. The 'experimental + scale' data are based on the area value from the reference 6 and the area scaling equation 2 .
Assuming that each bit of the EPALU is 20×40 µm 2 , we can estimate the area of the entire circuit to be 51200 µm 2 . Since the laser is off-chip, the wall-plug efficiency of the laser should not be taken into consideration. Therefore, we cross out 80% of the laser power consumption in this calculation. The result is shown in Supplementary Figure 5. Again, thermal tuning will dominate the total power consumption here, which can be further reduced or even eliminated in the future using broadband modulators (e.g. electro-absorption modulators 12 or ultralow-Q microresonator modulator 13 ) or using more efficient tuning materials (e.g. phase change material 14 ) or more power-efficient methods (e.g. post-fabrication trimming 15 ). are also some applications that are less sensitive to the chip area such as data centers.

Supplementary Figure 5. Power density comparison between EPALU and conventional electronic ALU (E-ALU).
The performance of the EPALU significantly depends on the characteristics of the modulators. A modulator with lower power consumption, higher bandwidth, larger extinction ratio and lower insertion loss is ideal for optical computing. Limited performance such extinction ratio of a single modulator will become an obstacle of the whole circuits. The theoretical analysis of impact of the extinction ratio has been discussed in the reference 16 Table 2 and Supplementary Table 3 show the truth tables for the testing results in Figure 3e and 3f, respectively.